A brief introduction of Leslie Lamport's "logical time" concept in interconnection network.

1. Logical Time
2010/10/15
Yoshi

2. Interfacing the On-Chip Networks

3. Timing Model

4. Happen-Before Relation
• A well-known problem, discovered by Leslie
Lamport
• The model is easy, but the discussion is very
theoretical and difficult
• References
– Time, Clocks, and the Ordering of Events in a
Distributed System”, which received the PODC
Influential Paper Award in 2000
– http://en.wikipedia.org/wiki/Happened-before
– http://en.wikipedia.org/wiki/Leslie_Lamport

5. Assumption
• Asynchronous network model with universal
reliable FIFO buffer
– Where universal is a term to say that it is based on
I/O automation model

6. Trace
• External actions
• The trace of an execution α of A, denoted by trace(α),
is the subsequence of α consisting of all the external
actions
• We say β is a trace of A if β is the trace of an
execution of A
• Denote the set of traces of A by traces(A)

7. Fairness
• Explanation
– Never let a process/component have no chance to
get its turn to run
• Formal definition
– If α is finite, then C is not enabled in the final state
of α
– If α is infinite, then α contains either infinitely
many events from C or infinitely many
occurrences of states in which C is not enabled

8. Indistinguishable
• Let α and α’ are two executions of a system, to
a process i, if i has the properties in α and α’
– The same sequence of states
– The same sequence of outgoing messages
– The same sequence of incoming messages
• We say that α is indistinguishable from α’ to
process i, denoted α ḭ α,
• This definition can be extended to r rounds
(more than one time communications)

9. Theorem
• Let A be an asynchronous send/receive system
with universal reliable FIFO channels, and let β
be a fair trace of A.
• Let γ be a sequence obtained by reordering the
events in β while preserving the β ordering.
Then γ is also a fair trace of A

10. Corollary
• Let A be an asynchronous send/receive system
with universal reliable FIFO channels, and let α
be a fair execution of A.
• Let γ be a sequence that is obtained by
reordering the events in β = trace(α) while
preserving the β ordering.
• Then there is a fair execution α’ of A such that
trace(α’)= γ and such that α and α’ are
indistinguishable to every process Pi

11. Theorem for Logical Time
• Let α be a fair execution of a send/receive network
system A with universal reliable FIFO channels and let
ltime be a logical-time assignment for α. Then there is
another fair execution of A such that
– α’ contains the same events as α
– The events in α’ occur in the order of their ltimes in α
– α‘ is indistinguishable from α to every process automation
• In short, the order of events of each particular process
must be the same in α and α’.
• However, It permits events at different processes to be
reordered.

12. An Example of Logical-Time
Assignment
1 2 3
Send/receive diagram for execution α

13. Results of Different Assignments
1 2 3
A logical-time assignment for α
2
3
4
7
10
9
8
1
5
6
1 2 3
Send/receive diagram for reordered
execution α‘
2
3
4
7
10
9
8
1
5
6

14. Logical t = 7.5
1 2 3
Dotted line for t = 7.5
2
3
4
7
10
9
8
1
5
6
1 2 3
Reordered execution α’ with horizontal
line for t = 7.5
2
3
4
7
10
9
8
1
5
6

15. Summary
• FIFO still holds (?)
– It should be, in most general assumptions
• According to the discussion above, we
conclude that our simulation methodology
gives the corrects results (outputs)
• We further handle the relative speed between
PEs and routers by tuning the clock speeds of
them

16. Routing and Link Speed Descriptions