logic built in self test techniques based on FPGA in verilog using XILINX 14.7 software

1. LOGIC BUILT IN SELF TEST
TECHNIQUE BASED ON FPGA IN
VERILOG.
Submitted by
MOHAMMAD HANNAN
21304014
M.TECH ECE 2nd Sem
DEPARTMENT OF ELECTRONICS ENGINEERING
PONDICHERRY UNIVERSITY
Under the Guidance of
Dr. K. ANUSUDHA

2. Timeline
BIST
BUILT IN LOGIC TEST
LFSR
Linear feedback Shift
register
Code
Code
Simulation
Design Schematic
Cellular Automata
Cellular Automata
Reference
Research Papers IEEE
Youtube
Google
2

3. BIST CONSISTS OF
1.Test Pattern Generator (TPG)
2. Output Response Analyzer (ORA)
3. Circuit Under Test (CUT)
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4. System Inputs
System Outputs
Test Controller
0utput
Response
Analyzer
Circuit Under
Test
Test
Pattern
Generator
Input
Isolation
Circuitry
BIST Implementation
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5. Test Pattern Generators
1. Linear Feedback Shift Register ( LFSR )
2. Cellular Automata
3. Counter
4. Gray Counter
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6. LINEAR FEEDBACK SHIFT
REGISTER

7. Linear Feedback Shift Register
1. The linear feedback shift register (LFSR) is used as a test pattern generator in BIST.
2. The only external signal necessary to generate the test patterns in LFSR is the clock.
3. If 2n patterns are used to test an n input combinational gate, it is called Exhaustive Testing which
generates 100% single and multiple stuck-at faults coverage.
4. However, this process is time-consuming; thus, a subset of 2n is used where n is huge.
5. Data produced by an LFSR depend on its characteristic equation, which is defined in the form of
its feedback.
6. The random numbers produced are used to identify the physical faults in an IC.
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8. CODE OF LFSR
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9. SIMULATION RESULT
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10. SCHEMATIC
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12. Cellular Automata
1. Cellular Automata (CA) was firstly introduced by the scientists Von Neuman and Stanisly
Wlam who found the cellular spaces of CA
2. Cellular automata is another test pattern generation technique for BIST, which is useful in
the sense that it produces more random sequences than LFSRs and does not require global
feedback.
3. It is a collection of cells with forward and backward connections. Each cell can connect only
to its local neighbours (adjacent left and right cells).
4. The connections are expressed as rules. Assuming cell i can only talk with its neighbours i −
1 and i + 1 (Fig. 1)
5. Rule 90 : xið Þ t+1 = xi−1ð Þt + xi+1ðÞ ð t 1Þ
6. Rule 150 : xið Þ t+1 = xi−1ð Þt + xið Þt + xi+1ðÞ
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13. 1. . Linear Feedback Shift Registers (LFSR) and Cellular Automata (CA) are the most frequently
used as pseudo-random pattern generators. Both of them are Linear Finite State Machines
(LFSM)
2. Linear Hybrid Cellular Automata (LHCA) is one of the CA design structure that has different rules
in every single cell. LHCA can be considered as the simplest one-dimensional CA design
structure compared to Uniform Cellular Automata (UCA). It also can generate more randomized
test patterns than LFSR and UCA does.
3. a 4 bit test pattern generator using LHCA can be implemented through Field
Programmable Gate Array (FPGA
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14. Xc[4:1] Xin [4:1]
Done 0
Xc[1] 0 Xc[2]
Xc[2] Xc[1] Xc[2] Xc[3]
Xc[3] Xc[2] Xc[4]
Xc[4] Xc[3] Xc[4] 0
Xout[4:1] Xin [4:1]
Done
Xout[4:1] == Xin [4:1
Start?
reset
0
1
0
1
S0
S1
S2
S3
ASM CHART
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15. Hybrid CA
Xin [1] Xin [2] Xin [3] Xin [4]
Xout[1] Xout[2] Xout[3] Xout[4]
Start Done
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16. INFERENCES
• In Diff techniques of test pattern generation the final element of
BIST is compared based on the critical parameters of delay
power consumption and hardware utilization
• 32-bit programmable BIST architecture was implemented with
LFSR and MISR and tested for ISCAS benchmark circuit. The
fault modeling was done for stuck-at faults, and fault coverage
for different number of test patterns was found in MATLAB for
different seeds
• The more the number of patterns, the more would be the delay
and power consumption. Thus, right choice of seed is critical in
BIST.
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17. Reference
1. Williams TW, Brown NC (1981) Defect level as a
function of fault coverage. IEEE Trans Comput C-
30(12):987–988
2. 2. Thaker PA (2000) Register transfer level fault
modelling and test evaluation technique for VLSI
circuits, PhD thesis. The George Washington
University, May 2000
3. 3. Wang LT, Wu CW, Wen X (2006) VLSI test
principles and architectures: design for testability.
Morgan Kaufmann, 777 p
4. 4. Navabi Z (2011) Digital system test and testable
design: using HDL models and architectures.
Springer Science + Business Media, LLC 2011,
433 p
5. 5. Bushnell ML, Agrawal VD (2000) Essentials of
electronic testing for digital, memory, and mixed-
signal VLSI circuits. Kluwer, Dordecht 17

18. THANK YOU
MOHAMMAD HANNAN
21304014
M.TECH ECE (2 SEM)
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