Shift registers

1. 1
EET 3350 Digital Systems Design
Textbook: John Wakerly
Chapter 8: 8.5
Shift Registers

2. Definition
• A register is a digital circuit with two basic
functions: Data Storage and Data Movement
– A shift register provides the data movement
function
– A shift register “shifts” its output once every clock
cycle
• A shift register is a group of flip-flops set up in
a linear fashion with their inputs and outputs
connected together in such a way that the data
is shifted from one device to another when the
circuit is active
2

3. Shift Register Applications
• converting between
serial data and
parallel data
• temporary storage in
a processor
– scratch-pad memories
• some arithmetic
operations
– multiply, divide
• communications
– UART
• some counter
applications
– ring counter
– Johnson counter
– Linear Feedback Shift
Register (LFSR) counters
• time delay devices
• more …
3

4. Shift Register Characteristics
4
• Types
– Serial-in, Serial-out
– Serial-in, Parallel-out
– Parallel-in, Serial-out
– Parallel-in, Parallel-out
– Universal
• Direction
– Left shift
– Right shift
– Rotate (right or left)
– Bidirectional
n-bit shift
register

5. Data Movement
• The bits in a shift register can move in any of the
following manners
5

6. n-bit shift
register
n-bit shift
register
Data Movement
• Block diagrams for shift registers with various
input/output options:
6
n-bit shift
register
n-bit shift
register

7. n-bit shift
register
Serial-In Serial-Out
• Data bits come in one at a
time and leave one at a time
• One Flip-Flop for each bit to
be handled
• Movement can be left or
right, but is usually only in a
single direction in a given
register
• Asynchronous preset and
clear inputs are used to set
initial values
7

8. Serial-In Serial-Out
• The logic circuit diagram below shows a
generalized serial-in serial-out shift register
– SR Flip-Flops are shown
– Connected to behave as D Flip-Flops
– Input values moved to outputs of each Flip-Flop
with the clock (shift) pulse
8
N-Bit Shift Register
0
N 1

9. Shift Registers
• The simplest shift register is one that uses only Flip-Flops
• The output of a given Flip-Flop is connected to the D input of the
Flip-Flop at its right.
• Each clock pulse shifts the contents of the register one bit
position to the right.
• The Serial input (SI) determines what goes into the leftmost Flip-
Flop during the shift. The Serial output (SO) is taken from the
output of the rightmost Flip-Flop.
9
Q Q Q
Q

10. Serial-In Serial-Out
• A simple way of looking
at the serial shifting
operation, with a focus on
the data bits, is illustrated
at right
• The 4-bit data word
“1011” is to be shifted into
a 4-bit shift register
• One shift per clock pulse
• Data is shown entering at
left and shifting right
10
1
2
3
4
5

11. Serial-In Serial-Out
• The diagram at right
shows the 4-bit
sequence “1010”
being loaded into the
4-bit serial-in serial-
out shift register
• Each bit moves one
position to the right
each time the clock’s
leading edge occurs
• Four clock pulses
loads the register
11

12. Serial-In Serial-Out
• This diagram shows
the 4-bit sequence
“1010” as it is
unloaded from the 4-
bit serial-in serial-out
shift register
• Each bit moves one
position to the right
each time the clock’s
leading edge occurs
• Four clock pulses
unloads the register
12

13. 13
Serial-In Serial-Out
• Serial-in, serial-out
shift registers are
often used for data
communications
– such as RS-232
– modem transmission
and reception
– Ethernet links
– SONET
– etc.

14. Serial-to-Parallel Conversion
• We often need to convert
from serial to parallel
– e.g., after receiving a series
transmission
• The diagrams at the right
illustrate a 4-bit serial-in
parallel-out shift register
• Note that we could also use
the Q of the right-most Flip-
Flop as a serial-out output
14
n-bit shift
register

15. 15
Serial-to-Parallel Conversion
• We would use a
serial-in parallel-out
shift register of
arbitrary length N to
convert an N-bit word
from serial to parallel
• It would require N
clock pulses to LOAD
and one clock pulse
to UNLOAD

16. Serial-to-Parallel Conversion
• These two shift
registers are used
to convert serial
data to parallel data
• The upper shift
register would
“grab” the data
once it was shifted
into the lower
register
16

17. Parallel-to-Serial Conversion
• We use a Parallel-in Serial-out
Shift Register
• The DATA is applied in parallel
form to the parallel input pins PA
to PD of the register
• It is then read out sequentially
from the register one bit at a time
from PA to PD on each clock cycle
in a serial format
• One clock pulse to load
• Four pulses to unload
17
n-bit shift
register

18. 18
Parallel-to-Serial Conversion
• Logic circuit for a parallel-in, serial-out shift register
Mux-like
Mux-like
0
0
1
0
1
1

19. Parallel-In Parallel-Out
• Parallel-in Parallel-out Shift
Registers can serve as a
temporary storage device or
as a time delay device
• The DATA is presented in a
parallel format to the parallel
input pins PA to PD and then
shifted to the corresponding
output pins QA to QD when
the registers are clocked
• One clock pulse to load
• One pulse to unload
19

20. n-bit shift
register
Universal Shift Register
• Universal shift register
• Can do any combination of
parallel and serial
input/output operations
• Requires additional inputs to
specify desired function
• Uses a Mux-like input gating
20
L/S
L/S
A
B
A
B
F
1
0
1
0

21. 21
Universal Shift Register
• Parallel-in, parallel-out shift register
Mux-like
Mux-like
0
0
1
0
1
1

22. Universal Shift Register
• Parallel shift register (can serve as converting
parallel-in to serial-out shifter):
22

23. MSI Shift Registers
• 74LS164 is an 8-Bit Serial-
In Parallel-Out Shift
Register
• Typical Shift Frequency of
35 MHz
• Asynchronous Master
Reset
• Gated Serial Data Input
• Fully Synchronous Data
Transfers
23

24. MSI Shift Registers
24
A LOW level on the Master Reset (MR) input overrides all other
A LOW level on the Master Reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all Q outputs
inputs and clears the register asynchronously, forcing all Q outputs
LOW.
LOW.
• 74LS164 logic diagram

25. MSI Shift Registers
• 74LS164 8-Bit Serial-In Parallel-Out Shift
Register
25

26. MSI Shift Registers
• The 74LS164 is an edge-
triggered 8-bit shift register with
serial data entry and an output
from each of the eight stages.
• Data is entered serially through
one of two inputs (A or B);
– either of these inputs can be used
as an active HIGH Enable for data
entry through the other input
– an unused input must be tied HIGH,
or both inputs connected together
26

27. MSI Shift Registers
• Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right
• This also outputs at Q0 the logical AND of the two data
inputs (A•B) that existed before the rising clock edge.
27

28. MSI Shift Registers
28

29. MSI Shift Registers
• 74LS166 is an 8-Bit Shift
Register
• Parallel-in or serial-in
– shift/load input establishes
the parallel-in or serial-in
mode
• Serial-out
• Synchronous Load
– Serial data flow is inhibited
during parallel loading
• Direct Overriding Clear
29

30. MSI Shift Registers
• 74LS166 is an 8-Bit Shift Register
30

31. MSI Shift Registers
• 74LS166 8-Bit Shift Register is a parallel-in or
serial-in, serial-out shift register
31

32. MSI Shift Registers
• 74LS166 is an 8-Bit Shift
Register
32

33. MSI Shift Registers
• 74LS166 is an 8-Bit Shift Register
33