Serial Link Design - Meeting the Need for Speed

Serial Link Design Principles:
Meeting the Need for Speed
7/18/2019 Serial Link Design Principles 1
A Webinar By EMA Design Automation
Presenter:
Jerry Long

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About Your Presenter
Serial Link Design Principles7/18/2019
Jerry Long is a Senior Applications Engineer for EMA.
With a bachelor's degree in electrical engineering from
UT Austin, Jerry provides high-end customer support for
several Cadence products, and is involved in several
product lines involving verification and timing analysis.
Contact: jerryl@ema-eda.com

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What is a Serial Link Interface
• An interface is typically thought
of as a parallel stream of data
• A Serial Link Interface is where parallel streams of data are
combined (serialized) for high-speed data transmission
• Commonly referred to as a “SerDes” (Serialized/Deserialized)
Serializer De-serializer
Parallel
Data
Serial Data
Parallel
Data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0 D1 D2 D3 D4 D5 …
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Data
Source
Data
Target

4
Asynchronous
RS-232, USB, Ethernet, Serial ATA, Serial
Attached SCSI (SAS), CAN bus, PAM
Common Serial Link Interfaces

5
Synchronous
PS/2, SPI, I2C, JTAG, PCIe, DVI, HDMI
Common Serial Link Interfaces

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Advantages
• Fewer data lines
– Simplifies layout, enables increased density
– Less synchronization issues
– Eliminates bit skew uncertainties
& timing concerns
– Reduces number of vias required
• Cost of Interconnect
– Fewer data pins mean cheaper ICs
– 2-wire vs parallel cables
• Higher Noise Immunity
– Less wires means less noise in proximity of data lines
– Differential signaling provides in-phase cancelling, tight coupling,
controlled impedance characteristics (i.e. less EMI & SSO problems)
– Signal quality maintained over longer distances
• Lower power benefits

Serial Link Interface
Disadvantages / Challenges
7/23/2019 7
• Due to layout simplification the ability to effect change / fix
issues in layout alone is limited
• Visibility into interface performance based on physical
inspection alone can be error prone
• To achieve compliance measurements are required that must
be captured with sophisticated (expensive) equipment
• Serial interfaces often span multiple boards / fabrics.
Analyzing the interface holistically can be challenging

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Reliability Issues
& Field Failures
Reduced Yields Costly Re-spins
Project Delay
Ripple Effect
Increase MFG
Costs
Missed Time to
Market Schedules
Challenges with Serial Link Interfaces
Effects of Serial Link Problems

9Serial Link Design Principles7/18/2019
TX RXChannel/System Interconnect
Physical Layer
(the PHY)
Data Link
Layer
Data Link
Layer
Component “Make-Up” of a Serial Link

TX RX
Channel/System
Interconnect
Receiver
Equalizer
Clock
Recovery
Data
RecoveryDFE
CTLE
Transmitter
Equalizer
Serializer
Pre-emphasis
FIR
FFE
Stripline/
Microstrip
Connectors
Capacitors
Vias
Cables
Backplanes
PCB/PKG
Component “Make-Up” of a Serial Link

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• Escalating data rates
• Passive interconnect modeling
• Modeling SerDes equalization
• Simulation capacity
Driving Factors Creating the Challenge

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• As data rate increases, the normalized jitter &
noise in a given channel will also increase
• Early PCI Express ran at 2.5Gbps
• 10-12.5 Gbps is common
• New interfaces are targeting 25Gbps!
Escalating Data Rates

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• A classic “physical” layer
problem with channel layout
• Need extraction accuracy
at higher frequencies
• Plane modeling becomes
increasingly important
– Example: Swiss cheese
• Via structures are critical!
– Stubs may require back-drill
Passive Interconnect Modeling

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• Associated with the Data Link Layers (Tx & Rx)
• Complex equalization (EQ) often included in SerDes devices
• Some EQ (ex. DFE) is adaptive:
Its settings self-modify while passing Data traffic.
yn
W
cdr
xn dn
+
yn = xn + S wi*di
yn - output
xn - input
di - previous ‘ith’ decision
wi - ith tap weight
Modeling SerDes Equations

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• Consider a lab oscilloscope set on “infinite persistence”
• Initial eye may be open, but as additional traffic is sampled, the eye can close down
• Eye stabilizes as enough samples are taken, & unique bit combos are exhausted
• Time domain simulation is similar; need to run LARGE bit streams to generate stable
eye diagrams, from which reliable measurements can be taken (otherwise optimistic)
• Traditional circuit simulators can run on the order of 100s of bits
• Multi-gigabit serial links can commonly take 1,000,000s of bits to converge, with EQ
• Additional simulation capacity of several orders of magnitude is required!
Simulation Capacity

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• Multi-gigabit serial links need to pass a lot of data traffic to give reliable
eye diagrams and provide enough samples to accurately predict BER
• Multi-gigabit SerDes devices often utilize adaptive equalization, which
need to pass a lot of data traffic before they stabilize and lock in
• Data rates have risen from 2.5 to 25Gbps in about 10 years
• Future designs targeting 400Gbps to 1Tbps
To accurately simulate multi-gigabit serial links, simulate very large bit streams
with accurate “physical” models (i.e. channel, xmtr, & rcvr models) and very fast &
accurate equalization models
Addressing Challenges of Serial Links
Channel Simulation is a Requirement
TX RX
Channel/System
Interconnect

• Characterize the physical channel
• Perform channel simulation
• Post-process outputs
What is Channel Simulation?

19
To characterize the channel: the analog circuit part of channel
(the PHY) is separated from algorithmic EQ (the Data Link)
Package
Interconnect
System
Interconnect
Package
Interconnect
Analog Channel
Tx Rx
Serial Link
Data out
FFE DFE/CDR
Data In
What is Channel Simulation – the “Physical” Channel

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Can simulate millions of bits in minutes
impulse
response
Channel Simulator
Impulse response is
convolved with the bit stream
to produce raw waveforms
Analog channel is
exercised in SPICE
to produce a ramp
response from
which an impulse
response is derived
Package
Interconnect
System
Interconnect
Package
Interconnect
Analog Channel

TX RX
Channel/System
Interconnect
Physical Layer
(the PHY)
Data Link
Layer
Data Link
Layer

Data Link
Layer
Data Link
Layer
TX RX
What is Channel Simulation – “Equalization” Modeling
Xmtr EQ Rcvr EQ
AMI AMI

Data Link
Layer
Data Link
Layer
TX RX
What is Channel Simulation – “Equalization” Modeling
Xmtr EQ Rcvr EQ
FFE
FIR CDR
DFECTLE
AMI AMI

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• Extension made to IBIS in 2007
– Cadence at the forefront of driving AMI through the standardization
process
• Enables executable, software-based, algorithmic models to
work together with traditional IBIS circuit models
– Allows deeper access to on-chip technology (the secret sauce)
• Enables SerDes adaptive equalization algorithms to be
modeled and used during channel simulation
– Fast, accurate and flexible
Algorithmic Modeling Interface (AMI)

7/23/2019 25
Great. So I can accurately simulate my serial
interface at speed.
Now what?
How do I ensure it will meet protocol?

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• Fortunately, standard interfaces provide guidance on
successful operation to help you ensure correct operation
• However…
– What is the “compliance” criteria for my interface?
– How do I verify my design meets the compliance tests necessary?
– What must I know to be able to verify compliancy?
Meeting Standards Compliance

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• Compliance consists of multiple test criteria
• Each will need to be analyzed and documented
• All must pass to be considered ‘compliant’
Compliance Analysis & Reporting

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Compliance Analysis & Reporting
How do we get to this?

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Demo…
(Serial Link Analysis & Compliance with Sigrity tools)

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With A Comprehensive Serial Link Analysis and
Compliance Methodology You Can:
Identify Issues Early in
The Design Process
Prevent Unnecessary
Re-Spins
Eliminate Multiple
Validation Iterations
Improve Time
To Market

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Lots of support help with YouTube Videos
• How to Build an IBIS-AMI Model
• How to Verify a PAM Encoded Multi-Gigabit Serial Link
• How to Test Modules for Automotive Ethernet
Compliance Before Building a Prototype
• How to Accurately Model a Multi-Gigabit Serial Link 10
Times Faster
• How to Accelerate Accurate 3D Full Wave Extraction
Time
• How to Import Optimized 3D Structures into Your Design
Tool After 3D EM Analysis
Sigrity Tech Tips on YouTube

Questions?
EMA Design Automation
800 813-7494
edc@ema-eda.com
www.ema-eda.com
Next Webinar:
Constraint Management
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Thank you for joining us today!

Serial Link Design - Meeting the Need for Speed

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