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16 April 2024 VLSI Design 1
16 April 2024 1
16 April 2024 1
VLSI Design
CMOS Inverter Analysis

Inverter Voltage Transfer
Characteristic (VTC)

General Circuit Structure of an nMOS
Inverter

Voltage Transfer Characteristic (VTC)

Critical Voltages
• VOH:Maximum output voltage when the
output level is logic “1”.
• VOL:Minimum output voltage when the
output level is logic “0”.
• VIL:Maximum input voltage which can be
interpreted as logic “0”.
• VIH:Minimum input voltage which can be
interpreted as logic “1”.
• VTH:Threshold voltage of inverter, is
defined as the point, where Vin=Vout.

Noise Immunity and Noise
Margins
• The ability of an inverter to interpret
an input signal within a voltage
range as either a logic “0” or as a
logic “1”, allows digitals circuits to
operate with a certain tolerance to
external signal perturbations.

Cascaded Inverters

Noise Immunity and Noise Margins

Noise Margins

Noise Margins
• Noise tolerances for digital circuits, called, Noise
Margin (NM).
• NML=VIL-VOL :Noise Margin Low
• NMH=VOH-VIH :Noise Margin High
• The noise immunity of the circuit increases with
NM

Resistive Load Inverter

VTC
• Applying Kirchhoff’s Current Law
(KCL), the Load current is always
equal to the nMOS drain current.
ID (Vin, Vout)=IL(VL)
• Two critical voltage points (VIL,VIH)
defined on this VTC curve, where the
slope of the Vout (Vin) characteristic
becomes equal to -1.

• Calculation of VOH:
Vout= VDD–RL.IR , where (ID=IR)
• When Vin is low, i.e., smaller than the
threshold voltage of the driver MOSFET,
the driver transistor is cut-off.
• So ID=IR =0
• VOH =VDD

• Calculation of VOL:
• IR= IDLinear
• (VDD-VOUT)/RL= Kn/2[2(VDD-VTO).VOL- VOL
2]

• Calculation of VIL:
• IR= IDSaturation
• (VDD-VOUT)/RL= Kn/2[(Vin-VTO)2]

• Calculation of VIH:
• IR= IDLinear
• (VDD-Vout)/RL= Kn/2[(Vin-VTO).Vout-Vout
2]
• Differenting both sides w.r.t Vin and
substituting the slope=-1

Layout of Resistive Load
Inverter

Enhancement-nMOS Load Inverter

Depletion-nMOS Load Inverter

Calculation of VOH:
the driver transistor is cut-off and does
not conduct any drain current.
• ID, Driver, Cutoff=ID, Load, Lin=0 A
• The Load device which operates in the
linear region also has zero drain current.
• So ID, Load=0 A
• Only valid solution in the linear region is
VOH =VDD

Calculation of VOL:
• ID, Driver, Lin = ID, Load, Sat
• ID, Driver, Lin =(Kdriver/2)[2(VOH-VTO).VOL- VOL
2]
• ID, Load, Sat =(KLoad/2)[-VT, Load (VOL)]2

Calculation of VIL:
• ID, Driver, Sat = ID, Load, Lin
• ID, Driver, Sat =(KDriver/2)[Vin-VTO]2
• ID, Load, Sat =(KLoad/2){2[VT, Load (Vout)](VDD-
Vout)- (VDD-Vout)2}

Calculation of VIH:
• ID, Driver, Lin = ID, Load, Sat
• ID, Driver, Lin =(KDriver/2)[2(Vin-VTO) Vout-
Vout
2]
• ID, Load, Sat =(KLoad/2)[-VT, Load (Vout)]2

VTC of a Depletion-Load Inverter
Circuit

VTC of Depletion-Load
Inverter Circuits

Layout of Depletion-Load
Inverters

CMOS Inverter

VTC of CMOS Inverter

Region of Operation
Region Vin Vout nMOS pMOS
A <VT0,n VOH Cut-Off Linear
B VIL high≈VO
H
Saturation Linear
C Vth Vth Saturation Saturation
D VIH Low≈VOL Linear Saturation
E >(VDD+VT0,p) VOL Linear Cut-Off

CMOS Inverter
Calculation of VOH:
the driver transistor is cut-off and does
not conduct any drain current.
• ID, Driver, Cutoff=ID, Load, Lin=0 A
• The Load device which operates in the
linear region also has zero drain current.
• So ID, Load=0 A
• Only valid solution in the linear region is
VOH =VDD

CMOS Inverter
Calculation of VOL:
• ID, Driver, Lin = ID, Load, Cut-off
• ID, Driver, Lin =(Kdriver/2)[2(VDD-VTO).VOL- VOL
2]
• ID, Load, Cut-off =0A
• VOL =0 V

CMOS Inverter
Calculation of VIL:
• ID, nMOS, Sat = ID, pMOS, Lin
• ID, nMOS, Sat=(Kn/2)[VGS,n-VTO,n]2
• ID, pMOS, Lin=(KP/2)[2(VGS,p-VTO,p)VDS,p-VDS,p)2]
• VIL=(2Vout + VTO,p- VDD+ KRVTO,n)/(1+KR)
• Transconductance Ratio(KR)
• KR = Kn/KP

CMOS Inverter
Calculation of VIH:
• ID, Driver, Lin= ID, Load, Sat
• ID, nMOS, Lin= (Kn/2)[2(VGS,n-VTO,n)VDS,n-VDS,n)2]
• ID, pMOS, Sat=(Kp/2)[VGS,p-VTO,p]2
• VIH=(VDD+VTO,p+KR (2Vout+VTO,n))/(1+KR)
• KR = Kn/KP

CMOS Inverter
Calculation of Vth:
• ID, Driver, Sat= ID, Load, Sat
• ID, nMOS, Sat= (Kn/2)(VGS,n-VTO,n)2
• ID, pMOS, Sat=(Kp/2)[VGS,p-VTO,p]2
• Vth=VTO,n+KR
-1/2(VDD+VTO,p)/(1+KR
-1/2)
• KR=Kn/KP

Design of CMOS Inverter

• CMOS inverter doesn’t draw any
significant current from power supply,
except for small leakage and sub-
threshold currents.
• These currents exist when input voltage is
either smaller than VTO,n or larger than
(VDD+VTO,p) repectively.
• The nMOS and pMOS transistors conduct a
non-zero current, during low-to-high and
high-to-low transitions, i.e. in Regions B,
C, D.

• The current drawn from the power supply
during transition reaches its peak value
when Vin=Vth.
• In other words, the maximum current is
drawn when both transistors are operating
in saturation mode.
• VTC of a CMOS inverter and the power
supply current, as a function of the input
voltage, is shown.

VTC & Power Supply Current
of a CMOS Inverter

• The threshold voltage Vth is identified as
one of he most important parameter that
characterize the steady-state input-output
behavior of the CMOS inverter circuit.
• The CMOS inverter, provides a full output
voltage swing between 0 and VDD and
therefore the noise margins (NM) are
relatively wider.
• So, the problem of designing a CMOS
inverter can be reduced to setting the
inverter threshold (Vth) to a desired
voltage value.
Design of CMOS Inverters

• Switching threshold voltage of an
ideal inverter is, Vth, ideal= VDD/2.
• The Inverter threshold voltage Vth
shifts to lower values with increasing
KR ratio.
• For a symmetric CMOS inverter with
VT0,n =VT0,p and KR=1.
• VIL= 1/8(3VDD+2 VT0,n)
• VIH= 1/8(5VDD-2 VT0,n)

• For a symmetric CMOS inverter with
VIL+ VIH= VDD
• The noise margins NML and NMH for
this symmetric CMOS inverter are
now calculated as:
• NML=VIL-VOL=VIL
• NMH=VOH-VIH=VDD-VIH
• NML=NMH=VIL

Supply Voltage Scaling in CMOS
Inverters
VDD
min=VT0,n + VT0,p

VTC of CMOS Inverter at
Lower VDD
min

Design of D-nMOS Load Inverter

Design of E-nMOS Load Inverter

Layout of CMOS Inverter

50
3D Perspective
Polysilicon Aluminum

51
Design Rules
• Interface between designer and process
engineer
• Guidelines for constructing process masks
• Unit dimension: Minimum line width
– scalable design rules: lambda
parameter
– absolute dimensions (micron rules)

52
CMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green

53
Layers in 0.25 mm CMOS
process

54
Intra-Layer Design Rules
Metal2
4
3
10
9
0
Well
Active
3
3
Polysilicon
2
2
Different Potential
Same Potential
Metal1
3
3
2
Contact
or Via
Select
2
or
6
2
Hole

55
Transistor Layout
1
2
5
3
Transistor

56
Vias and Contacts
1
2
1
Via
Metal to
Poly Contact
Metal to
Active Contact
1
2
5
4
3 2
2

57
Select Layer
1
3 3
2
2
2
Well
Substrate
Select
3
5

58
CMOS Inverter Layout
A A’
n
p-substrate Field
Oxide
p+
n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’

Inverter
Layout
Inverter Stick diagram

Example 1

Example 2

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