This document contains the answer to a question about instruction cycles in a computer. It discusses the phases of an instruction cycle, including fetch, decode, and execute. It describes the steps involved in fetching and decoding an instruction, such as loading the program counter, reading from memory, and incrementing the program counter. It also explains how the type of instruction is determined during decoding based on control signals.

1. Page No.... * * * * *
Roll No. (In Figures).12.0010.0.6...(inWords).One..Iuuo.Zero.Zero..One.zero.ero
..Six.B.Tech.CSE Einal.Examinatien-2021. Medium.English.
Name of the Student.Deebak.kuma.. ...Class/Semester. 29E1..B1eCh..cSE..5..
Name ofPaper...GS.A.. .Codeof Paper.110.64/NJ..Total Number of pages written....1.
120010o6
Date ofExam.23/02 202. Signature
LDeebak kumar
* * * * * * * * *
AnSwer Sheet:
An$:1 AProgramre.sidingin the_memory unitof the Combufer_
ConSists of a sequence ot InstrucHons.
The progrom is exe.cuted inthe Combuter by aning
through 0. Gucle tor each Tnstruc.tion.
The þrocesSinginunlve.d intheexecution ota single Tnst
-Tucion is termed as TnstruttionCucle
EachTnstrucion Cucle is in turn Subdivided into a seq-
-Uence ot Subcycles or bhaSes.
Inbasit Combuter each ToStrucion Cucle consists ot he
tollowing bhases:
1.
Fetch the Tnshru.cion from the mmemory
2 Decode he Instruction
. Reod he effec.hiveaddressfrom thememoryi the
Instruction_has an Indifect Addre.ss.
Execute the Tnstrucion
Fetch Cycle Execute Cucle
Start Fetch Fxecute
LTastruction
Halt
Inskruction
Dpon CombleHon ofsBepiv),the Control goeS back ththe
StebLi to Fetth,decode_and Execute theNexk Tnstruotian
TheprocesSiS Coninous unless a Halt InsBruchionEntounBen

2. Roll No..1001006... Paper Code .061IN.. Page No . . *sA******
Fetchand Decode:
Stebs Tnvolued in Fetchanddecode the Inshuction:
Step1:nitially,theþrogam Counter PG 1S loaded withtHheaddress
of the Firstinstrucionin thebrogram.
Step2: The Sequence Counter SC iS cleared to0,proyidingtimmin
Signal To
Step3:Tnemicro-oberation forfetch and decode bhases_Can_be
Specified by heFollouwing reqisBerTransfer StatementS
To:AR PC
T:IR< M[ARI,P¢-PCA1
I2 Do, D DecodeIR(12-14) AR-TR(0-11),K-IR5
S2
To BUS
Memory Unit
AddresS
Read
AR 1
PC 2
IR
peppo
LD
clock Dee1ature

3. 11064/N Poge
Rol No
3 .
Page No12001006
Stepu:The above figure showshow the rst tw0 register transer
Statements are imblementedin fhe bus SyStem.
Steb 5:D þmvide the_dato. both for the transfer ot PGto AR
e mUStabbly immin9 Sianal D o achieve the pllowing
ConnecHpns:
LDI6laCe the aontent o PG onto the bus bs making tne bus-
Selechon inbuts S2Siand Sn egual to 010.
lranster the Content t the bus to AR by enahling the
LD inbut o ARR
STep6: n Order, to imblement the Second Stotement i+ 1S
necessary h use imming Sianal þrouide the Falle-
oina Gonnecinns inthe bus Sustem
iEnable the read inbut o memor
GnSlace the ontent o memory ontn bus by making SoSSo
=111
Li Transfer the_content of thebus to IR byenablimg theID
inbut o Po.
Ltu Intre.ment P¢ byenabling the TNR input 0 PC
Steb Moltible inbut OR 9ates are inclucded in he_dfagram bec
-auSe there are other Conhralunchnnsthet inilinitiaf
the similan dherations.
Determine the ube ot nstruction:
he Timminq Signal hot isACtHiveoer fhe decoding isTa
During ime 1a,th Conirnl nit _dekermine the Tue o
the lnsHuttion thatLuaS read om the memaru
f D4=0 and T1, Memoryreterente luith_lndirëct Address
f DE0 and T:0; Memory reterenc.e Luith direct Address_
1f D 1 and 1=0 indicates Reqister-reference Instruchor
f D =1and T:1 indic.ate.s nbut-outhut TnstrucHons
Deepak (umar
Signature

4. Roll No 120010D6 Paper Code 1061NI Page No_
4.
he Three TnstruciontuhesareSubdiided intotour Seharate
baths
The $elect Oberahion is_activated with_clock tran&iianthat
iS OSSociated uith timingSignal I3.
hisCan be Smbalized as hlo
Da IT3 AR-MIAR]
DiT I3: Nothing
DI132Execute a register-referenc.e Tnshrucion
LD:T3: Execute_an Inbut -Outb1ut LashiiCion
Flnu chart
Start
SC-0
To
AR-TC
Fekch
T
IR-MTARJ, PC<- PCt1
T2
Deco de
Decode oberationCadeIR(2-14
AR4-IR0-11), I4-IR 05)
Execute
CRegister orI/o) =1 0 (Memory-Reference)
6)1/ 0 (register) CTdirect) =i o Cdirec+)
T3
AR-M[AR
T3 T3 T3
Execute Exectie Nothing
Register-
reterence
I/o
InStfucion Execute
SC-O
Memory-reference Ins.
s c-0
SC-0
Deebak kumar
Signature