This resume is for Helen Nguyen, an electrical engineer seeking a challenging position in IC chip development. She has over 10 years of experience in IC chip modeling, implementation, and testing. She is proficient in various design and simulation tools like Hspice, Spectre, and Cadence. She has experience developing design kits, libraries, and IBIS models. She is skilled in acquiring new transistor technologies from foundries and integrating them.
1. HELEN NGUYEN
Cell: 1-(408)-839-1001; Email: helennguyen97@gmail.com
OBJECTIVE
Seeking for a challenging and rewarding electrical engineer position that would assist your company in
meeting business goals, and provide opportunities for me to obtain skills and experiences in other areas of IC chip
development. Willing to take on junior or intermediate positions.
SUMMARY OF QUALIFICATIONS
A highly-motivated, skillful, and experienced electrical engineer with over 10 years in IC chip modeling,
implementation and testing.
A diligent and highly self-motivated professional continuously seeking opportunities to learn and applied
new knowledge in different engineering work.
An open-hearted, enthusiastic and collaborative team player working in synchronization with colleagues
toward a common objective.
Successful experiences and substantial skills in IBIS model development and simulation using Hspice and
Spectre software.
Highly proficient in acquiring and adopting new transistor technologies provided by third parties
semiconductor manufacturing companies
Passionate in applying Mathematics to create concise Electrical Parameters Specification for used in chip
design and verification
Familiar with design and implementation of Pcells library for using in various circuit applications
Practical engineering skills in Circuit Design and Simulation
Understanding in semiconductor device physics: PN junction, Diodes, CMOS
Strong written and clear verbal communication skills
COMPUTER & SOFWARE SKILLS
Electrical Design Tools: Hspice, Spectre, SpectreRF,Cadence Virtuoso, Virtuoso Spectre Cell Design &
Characterization, Virtuoso Visualization & Analysis, , Virtuoso Accelerated Parallel Simulator, Virtuoso AMS
Designer, IC6.1 what’s New Front End-Version 6.1.3, UltraSim, Layout Design in IC615;
OS Systems: UNIX, LINUS, Microsoft Windows , Apple MacOS
Productivity Software: Microsoft Office, Microsoft Word, Microsoft Excel
WORK EXPERIENCE
Feb 2001 – 2012: Exar Corporation Fremont, CA, USA
Sr. Device Engineer
Technology Responsibilities:
2. Developed design kits and libraries based on external foundry technologies.
Reviewed and verified the Process Control Module data of new devices
Integrated foundry technologies of companies acquired by Exar into Exar’s design processes
Supported design and verification teams in using the acquired technologies
Collaborated with members of the Operation department to ensure IC chips designed by Exar would be
fabricated successfully by external foundry companies
Created Electrical Parameters Specifications using transistor technologies such as CSM 0.35um, CSM
0.13um, TSMC HV20V, GF 65nm
Verify the accuracy of Design Rules & Process documents provided by foundry companies (Chartered
Semiconductors Manufacturing, Taiwan Semiconductor Manufactory Company, Global Foundries) by
conducting simulation using Cadence software
Used simulation tools (Hspice, Spectre) with various transistor technologies (0.13um, 65nm) to create and
conduct simulation models of which results provide the design team with insightful information to obtain
optimal chip designs
Implemented and tested the design of a 900MHz Low Noise Amplifier chip
IBIS-related Responsibilities:
Design and implemented IBIS models for Connectivity, Transceiver, Communication & SDH/SONET chips
Verified IBIS models using various software (Hyper Lynx, IBISCHK, and Cadence-Allegro)
Provided the Customer Support team with clarified technical information about Exar’s chips to help
resolve customers’ inquiries and issues
Evaluated development and simulation of IC chips using the IBIS-AMI modeling tool Systemvue by Agilent
Corp
Verified the Rx and Tx IBIS-AMI models by using Agilent’s Advanced Design System software
Organized IBIS modeling workshops conducted by Dr. Lynne Green
Represented Exar as an IBIS expert at the annual IBIS Summit
EDUCATION:
San Jose State University San Jose, CA
Master of Science, Electrical Engineering
May 2000: Master of Science in Electrical Engineering
May 1997: Bachelor of Science in Electrical Engineering with Mathematics minor
September 2009: “IC Layout Design” certificate from Silicon Valley Technical Ins., CA,
May 2011: Attended the class “Essential Principles of Signal Integrity”, a two day Signal Integrity workshop
with Hands on Labs with Dr. Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises