The document proposes optimizing DRAM caches for latency rather than hit rate. It summarizes previous work on DRAM caches like Loh-Hill Cache that treated DRAM cache similarly to SRAM cache. This led to high latency and low bandwidth utilization. The document introduces the Alloy Cache design which avoids tag serialization and keeps tags and data in the same DRAM row for lower latency. It also proposes a simple Memory Access Predictor to use either serial or parallel access models depending on the prediction to reduce latency and bandwidth usage. Simulation results show the Alloy Cache with predictor outperforms previous designs like SRAM-Tags.