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![Ā© Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
GaAs Device Technology
Page 18
THEORY
Gate
Source Drain
L
Id
W
t xd
Vd
For larger values of I and V.
Depletion
Id = Go { V -2/3(2Īµs/qNdt2)0.5 [(ĪØo-Vg+Vd)1.5 - (ĪØo-Vg )1.5]}
Vg
eq. 2.](https://image.slidesharecdn.com/gaas-150924090435-lva1-app6891/85/Gaas-18-320.jpg)
![Ā© Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
GaAs Device Technology
Page 19
THEORY
Gate
Source Drain
L
Isat
W
t
Vd
For Pinch Off
Channel Pinched Off
Isat = Go [ qNd t2 - (ĪØo-Vg ){1- 2/3[2Īµs (ĪØo-Vg ) ]0.5}]
Depletion
Vg
qNdt26Īµs
eq. 3.](https://image.slidesharecdn.com/gaas-150924090435-lva1-app6891/85/Gaas-19-320.jpg)
Uploaded byDr. Prashant Kore
Gaas
This document is a presentation by Dr. Lynn Fuller on Gallium Arsenide (GaAs) devices, technologies, and integrated circuits. It provides an overview and comparison of silicon and GaAs, describes GaAs crystal growth techniques like molecular beam epitaxy (MBE), and discusses GaAs field effect transistors (MESFETs) and the fabrication process for GaAs integrated circuits. The presentation contains numerous diagrams and equations to illustrate concepts in GaAs device physics and fabrication processes.
Careerā¦
Gaas
- 1. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 1 ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Gallium Arsenide Devices, Technologies & Integrated Circuits Dr. Lynn Fuller Motorola Professor Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 LFFEEE@rit.edu 11-4-2001 gaas.ppt
- 2. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 2 OUTLINE Comparison of Silicon and GaAs MBE GaAs MESFET MESFET Test Results IC Process Technology References
- 3. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 3 COMPARISON OF SILICON AND GaAs Silicon GaAs Minority Carrier Lifetime 0.003 1E-8 Electron Mobility 1500 8000 Hole Mobility (cm2/Vs) 600 400 Energy Gap (eV) 1.12 (indirect) 1.43 (direct) Vapor Pressure 1E-8@930C 1@1050C The higher electron mobility for GaAs shows promise for high speed devices and circuits. The direct gap allows for emission of photons in LEDs and LASER devices. Ī» = hc/E = (6.625E-34*3E8)/(1.6E-19*1.43) = 869 nm (infrared)
- 4. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 4 CRYSTAL GROWTH and OXIDES OF GaAs The vapor pressure of As in GaAs is quite low. A GaAs substrate heated to about 500 C begins to lose As from the surface. The wafer can be capped with SiO2 or Si3N4 or the heat treating can be carried out in an Arsenic over pressure. GaAs crystals are often grown in the horizontal Bridgeman technique and the wafers are āDā shaped. Czochralski GaAs wafers are also available up to ~4ā in diameter. GaAs wafers are more brittle than Silicon wafers. 4ā GaAs wafers cost about $300 each. GaAs does not grow a native oxide that is equivalent to SiO2. Ga2O3 and As2O3 and As2O5 oxides that grow on GaAs present more problems than uses.
- 5. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 5 GAAS ON SILICON WAFERS
- 6. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 6 CRYSTAL STRUCTURE x y z 2 1 1 1 2 2 Diamond Lattice (Silicon) Miller Indices (1/x,1,y,1/z) smallest integer set (100) plane (111) plane Zincblende Lattice (GaAs) As Ga Si
- 7. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 7 IMPURITIES IN GaAs Ionization Energy Impurity Type From Ec From Ev S n 0.0061 Se n 0.0059 Te n 0.0058 Sn n 0.0060 C n/p 0.0060 0.026 Ge n/p 0.0061 0.040 Si n/p 0.0058 0.035 Cd p 0.035 Zn p 0.031 Be p 0.028 Mg p 0.028 Li p 0.023 NOTE: Cr acts as a deep electron trap that can make GaAs appear to be undoped as it traps free electrons from silicon donor atoms that come from the quartz used in the crystal growth process.
- 8. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 8 ENERGY BAND STRUCTURE Gallium Arsenide (direct gap semiconductor) Energy gap = 1.43 eV Silicon (indirect gap semiconductor) Energy gap = 1.12 eV
- 9. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 9 ELECTRON AND HOLE MOBILITY 300 Ā°K77 Ā°K 8000 1015 1019 10161013 200,000 Electron Mobility in GaAs at 77 K and 300 K Hole Mobility in GaAs at 77 K and 300 K 1000 400 1015 1020
- 10. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 10 ELECTRON DRIFT VELOCITY GaAs Silicon Electric Field (x1000 V/cm) ElectronVelocity (x107cm/sec) 3 2 1 20 40 Gunn effect oscillation in GaAs diodes is a result of negative drift velocity region.
- 11. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 11 MOLECULAR BEAM EPITAXY GalliumAluminum Shutter n-type Dopant Arsenic p-type Dopant GaAs Substrate Heater Molecular Beams
- 12. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 12 PICTURE OF MBE MACHINE
- 13. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 13 EXAMPLES OF MBE LAYERS FOR BJT DEVICE 1015 1019 1018 1017 1016 Collector n-GaAs Base p-GaAs Emitter n-AlGaAs 1.0 Āµm Depth from Surface NetDopantConcentration(cm-3)
- 14. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 14 METAL CONTACTS TO GaAs Aluminum makes a schottky barrier contact (rectifying) to n-type GaAs. Ohmic contacts are usually made using and alloyed (heated above the eutectic temperature) contact of Gold (Au) and Germanium (Ge) followed by a layer of Nickel (Ni) and alloyed at a temperature above the AuGe eutectic temperature of 356 C. During alloying the Ge dopes the surface of the GaAs n+
- 15. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 15 GaAs DEPLETION MODE MESFET GaAs n+n+ Gate Drain Source n- Depletion Region n- is about 2 Āµm thick doped at 1E17 Si02 As the gate voltage is made more negative the depletion region increases in size and the channel decreases until pinch-off.
- 16. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 16 THEORY Gate Source Drain L I W t I = Vd/R = (W/L)(q Āµn Nd (t-xd) Vd) xd Vd For small values of I and V. eq.1. Depletion Vg
- 17. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 17 THEORY Where xd = (2 ĪµoĪµr/q)(ĪØo-V)/Nd)^0.5 xd = width of space charge layer q = 1.6E-19 Īµo= 8.85e-14 F/cm Īµr = 13.1 for GaAs Nd = n-type dopant concentration ĪØo = built in voltage = KT/q ln (Nd/ni) + Eg/2 Eg is the energy gap for GaAs ~ 1.43 eV V = Applied Voltage Go = 1/R Go = (W/L) (q Āµn Nd (t))
- 18. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 18 THEORY Gate Source Drain L Id W t xd Vd For larger values of I and V. Depletion Id = Go { V -2/3(2Īµs/qNdt2)0.5 [(ĪØo-Vg+Vd)1.5 - (ĪØo-Vg )1.5]} Vg eq. 2.
- 19. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 19 THEORY Gate Source Drain L Isat W t Vd For Pinch Off Channel Pinched Off Isat = Go [ qNd t2 - (ĪØo-Vg ){1- 2/3[2Īµs (ĪØo-Vg ) ]0.5}] Depletion Vg qNdt26Īµs eq. 3.
- 20. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 20 THEORY Vd Id Vg = 0.0 Vg = -2.0 Vg = -1.5 Vg = -0.5 Vg = -1.0 Saturation Region eq.3. Non Saturation Region eq. 2. Linear Region eq.1. Isat
- 21. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 21 DEPLETION TRANSISTOR CHARACTERISTICS Vgs=0 Vgs= -0.6 Vgs= -0.3 Vgs= -0.9 Vgs= -1.2 Vgs= -1.5 Pinch-off
- 22. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 22 ENHANCEMENT MODE TRANSISTOR GaAs n+n+ Gate Drain Source n- Depletion Region Si02 n- is about 2 Āµm thick doped at 1E17 The etched channel allows the space charge layer to pinch off the device with no gate voltage. The gate is biased positive to decrease the space charge layer thus increasing current flow.
- 23. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 23 INVERTER Vout +V Vin D-MESFET E-MESFET Vout Vin
- 24. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 24 GaAs IC PROCESS Semi insulating starting wafer 5 Levels Photo 2 Levels Ion Implant 2 Levels LPCVD SiO2
- 25. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 25 STARTING WAFER GaAs semi insulating with n- epitaxial layer n-
- 26. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 26 1st PHOTO FOR CHANNEL STOP Photoresist GaAs semi insulating with n- epitaxial layer n-
- 27. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 27 ALIGNMENT ETCH AND CHANNEL STOP IMPLANT GaAs semi insulating with n- epitaxial layer n- Note: etch alignment marks with separate mask step
- 28. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 28 1ST ENCAPSULATION LTO SiO2 5000 Ć GaAs semi insulating with n- epitaxial layer n-
- 29. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 29 2nd PHOTO CHANNEL ETCH GaAs semi insulating with n- epitaxial layer n-
- 30. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 30 ETCH OXIDE AND GaAs GaAs semi insulating with n- epitaxial layer n-
- 31. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 31 STRIP RESIST GaAs semi insulating with n- epitaxial layer n-
- 32. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 32 3rd PHOTO FOR GATE LIFT-OFF GaAs semi insulating with n- epitaxial layer n-
- 33. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 33 ETCH LTO GaAs semi insulating with n- epitaxial layer n-
- 34. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 34 EVAPORATE GATE METAL GaAs semi insulating with n- epitaxial layer n- Deposit 3000 Ć Tungsten
- 35. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 35 LIFT-OFF FORMING GATE METAL GaAs semi insulating with n- epitaxial layer n-
- 36. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 36 ETCH REMAINING LTO GaAs semi insulating with n- epitaxial layer n-
- 37. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 37 4th PHOTO FOR D/S IMPLANT GaAs semi insulating with n- epitaxial layer n-
- 38. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 38 DRAIN AND SOURCE ION IMPLANT GaAs semi insulating with n- epitaxial layer n-
- 39. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 39 STRIP RESIST GaAs semi insulating with n- epitaxial layer n-
- 40. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 40 2nd LPCVD SIO2 ENCAPSULATION GaAs semi insulating with n- epitaxial layer n-
- 41. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 41 ANNEAL GaAs semi insulating with n- epitaxial layer
- 42. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 42 5th PHOTO D/S METAL LIFT OFF GaAs semi insulating with n- epitaxial layer
- 43. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 43 LTO ETCH GaAs semi insulating with n- epitaxial layer
- 44. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 44 EVAPORATE D/S METAL GaAs semi insulating with n- epitaxial layer
- 45. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 45 LIFT OFF GaAs semi insulating with n- epitaxial layer
- 46. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 46 ALLOY D/S GaAs semi insulating with n- epitaxial layer Vdd Vout Vin Gnd
- 47. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 47 SUMMARY GaAs has higher electron mobility giving devices with improved radio frequency performance or higher speed digital devices. GaAs has different processing technology from silicon IC technology including: MBE, no oxide growth, encapsulation to prevent loss of arsenic at temperatures above 400 C. The main semiconductor device made is the MESFET. Optical LEDs and LASERs can be made in GaAs or related III-V semiconductors.
- 48. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 48 REFERENCES 1. āA Comparison of GaAs and Si Processing Technologyā, C.E. Weitzel, J.M. Frary, Motorola Semiconductor Research and Development Labs, Semiconductor International, June 1982 2. āGaAs Ics Bid for Commercial Successā, Larry Waller, Electronics June 14, 1984.3. 3. GaAs no longer next yearās technology as digital circuits come to marketā, W. Twaddell, EDN May 17, 1984. 4. āAre MMICs a Fad or Factā, D.R. Decker, MSN, July 1983. 5. āGallium Arsenideā, Inside Technology Today - a Texas Instruments Videotape Series, 18 min.
- 49. Ā© Dr. LynnFuller, Motorola Professor Rochester Institute of Technology Microelectronic Engineering GaAs Device Technology Page 49 HOMEWORK - GaAs 1. Sketch the layout of a GaAs inverter built using the fabrication process described. 2. Why are direct gap semiconductor materials necessary for light emitting devices. 3. What energy gap corresponds to 600 nm (red) and 400 nm (blue).