1. International INTERNATIONAL JOURNAL OF ELECTRONICS AND ISSN 0976 –
Journal of Electronics and Communication Engineering & Technology (IJECET),
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 3, Issue 3, October- December (2012), pp. 170-176
IJECET
© IAEME: www.iaeme.com/ijecet.asp
Journal Impact Factor (2012): 3.5930 (Calculated by GISI) ©IAEME
www.jifactor.com
FPGA IMPLEMENTED MULTICHANNEL HDLC TRANSCEIVER
Ms.Kshitija S. Patil
E & TC Department, GSMCOE Balewadi, Pune, Maharashtra, India.
E-mail: kspatil87@gmail.com
Prof. G.D.Salunke
Asst Prof., E & TC Department, GSMCOE Balewadi, Pune, Maharashtra, India.
E-Mail: geetasalunke@gmail.com
Mrs.Bhavana L. Mahajan
E & TC Department, GSMCOE Balewadi, Pune, Maharashtra, India.
E-Mail: mlbhavana@gmail.com
ABSTRACT
To successfully transmit data over any network, a protocol is required to manage the flow
or pace at which the data is transmitted. This protocol is defined in Layer 2 of OS1 (Open
Systems Interconnection) model. High-level Data Link Control (HDLC) is the most
commonly used Layer 2 protocol and is suitable for bit oriented packet transmission
mode. This project discusses the VHDL modeling of multi-channel HDLC Layer 2
protocol Transceiver and its implementation using FPGA as the target technology. The
HDLC Transceiver is used to transmit the HDLC frame structure from the transmitter
section and at the receiver end frame is received. The frame is check for single bit error if
error is detected that error is corrected by using hamming code. Implementing the multi-
channel HDLC protocol Transceiver in FPGA gives you the flexibility upgradability an
customization benefits of programmable logic
Keywords—HDLC, FPGA, VHDL
1. INTRODUCTION
A bit orientated protocol sends information as a sequence of bits. An example of a
bit orientated protocol is HDLC. Frames are used as a transport mechanism to transport
data from one point to another. A frame contains error checking information which
allows data to be sent reliably from a sender to a receiver.
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2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October December (2012), © IAEME
October-
HDLC is one of the most enduring and fundamental standards in Communications.
HDLC is in itself a group of several protocols or rules for transmitting data betw
between
network points. The HDLC protocol also manages the flow or pace at which the data is
sent. The data is organized into a unit called a frame. Some of the key operations of the
HDLC protocol implemented are handling bit oriented protocol structure and fo formatting
data as per the packet switching protocol, it includes Transmitting and receiving the
packet data serially.
Hamming is best known for his work on error - detecting and error- correcting
error
codes. Hamming codes are of fundamental importance in coding theory and are of
practical use in computer design.
The most common types of error correcting codes used in RAM are based on the
error-correcting
codes devised by R. W. Hamming. In the Hamming code, k parity bits are added to an n-
bit data word, forming a new word of n _ k bits. The bit positions are numbered in
sequence from 1 to n _ k. Those positions numbered with powers of two are reserved for
.
the parity bits. The remaining bits are the data bits. The code can be used with words of
any length.
2. HDLC PROTOCOL
HDLC [High-level Data Link Control] is a group of protocols for transmitting
level
[synchronous] data [Packets] between [Point Point] nodes. In HDLC, data is organized
[Point-to-Point]
into a frame. HDLC protocol resides with Layer 2 of the OSI model, the data link layer.
HDLC uses zero insertion/deletion process [bit stuffing] to ensure that the bit pattern of
s
the delimiter flag does not occur in the fields between flags. The HDLC frame is
synchronous and therefore relies on the physical layer to provide method of clocking and
synchronizing the transmission and reception of frames.
chronizing
Fig 1 Frame Structure
HDLC Address Field
The length of the address field depends on the data link layer protocol used, but is
normally 0, 8 or 16 bits in length. In many cases the address field is typically just a single
byte, but an Extended Address [EA] bit may be used allowing for multi byte addresses. A
multi-byte
one residing in the LSB bit indicates [the end of the field] that the length of the address
field will be 8 bits long. A zero in this bit location [now the first byte of a multi-byte
location multi
field] indicates the continuation of the field [adding 8 additional bits]. The SDLC
protocol will use only an 8 bit address. The SS7 protocol, which is used in point
point-to-point
links, does not use an address field at all. The first [MSB] bit in the Address field
all.
indicates if the frame is a unicast or multicast message. A zero in the MSB bit location
indicates a unicast message; the remaining bits indicate the destination node address. A
one in the MSB bit location indicates multicast message, the remaining bits indicate the
indicates
address.
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3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October December (2012), © IAEME
October-
HDLC Control Field
The Control field is 8 or 16 bits and defines the frame type; Control or Data. The Control
field is protocol dependent.
HDLC Data Field
The Data field may vary in length depending upon the protocol using the frame. Layer 3
frames are carried in the data field.
3. Block Diagram
Transmitter
The transmitter portion of the HDLC core will begin to transmit when the user’s
external logic asserts the TX_DATA_VALID signal. The transmitter will respond by
asserting the TX_LOAD signal to load the first byte of the packet. The timing diagram
assumes that IDLE_SEL is tied to a ‘1’ and the transmitter is generating continuous ‘1’
bits between frames. If IDLE_SEL is set to a ‘0’, the number of clocks from the assertion
of TX_DATA_VALID to TX_LOAD will vary from 5 to 12.Before the transmitter can
begin to send data serially; it must send an opening flag (7E). Immediately after the flag
is sent, the first byte is clocked out of the input shift register. Once a transmit frame has
begun, the user is required to make sure that data is available for each subsequent
requested byte. The transmitter will continue to request data by asserting TX_LOAD
until the user supplies a TX_EOF signal. This informs the transmitter that the last byte is
on the data bus. The transmitter then appends a 16 or 32-bit Frame Checking Sequence
16- bit
(FCS) to the transmitted data. After the FCS is sent, a closing flag (7E) byte is appended
to mark the end of the frame.
Receiver
The receiver clocks serial HDLC frames in continuously through the RXD pin. When an
opening flag is recognized, the receiver locks to all subsequent octet bytes. The user
informs the receiver of the ability to store the frame by asserting the
RX_SPACE_AVAILABLE input
CE_AVAILABLE
Fig. 2 HDLC Core
The receiver informs the user that a data byte is available by asserting the RX_READY
signal. The receiver indicates the beginning of the frame by asserting the RX_SOF signal.
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4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
Bytes will continue being passed to the user until the receiver recognizes the closing flag.
At this point, the last byte of the FCS sequence will be passed to the user coincident with
the RX_EOF signal. It must be stressed that the core does not contain the additional
pipeline registers to "swallow" the 2 or 4 bytes of FCS, and these will therefore be passed
on to the user. If this is undesirable, the corresponding pipeline should be added
externally to keep these bytes from passing on as part of the received frame. After the
reception of the frame has completed, the receiver will pass a byte of status information
to the user by placing the status on the receive data bus and asserting the RX_STATUS
signal.
Flow Chart
4. ERROR DETECTION AND CORRECTION
A number of simple error-detecting codes were used before Hamming codes, but
none were as effective as Hamming codes in the same overhead of space.
Parity Error Detection
Parity works by adding an additional bit to each character word transmitted. The
state of this bit is determined by a combination of factors, the first of which is the type
of parity system employed. The two types are even and odd parity. The second factor is
the number of logic 1 bits in the data character. In an even parity system, the parity bit is
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5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
set to a low state if the number of logic 1s in the data word is even. If the count is odd,
then the parity bit is set high. For an odd parity system, the state of the parity bit is
reversed. For an odd count, the bit is set low, and for an even count, it is set high.
To detect data errors, each character word that is sent has a parity bit computed for
it and appended after the last bit of each character is sent as illustrated in Figure 3-1. At
the receiving site, parity bits are recalculated for each received character. The parity bits
sent with each character are compared to the parity bits the receiver computes. If their
states do not match, then an error has occurred. If the states do match, then the character
may be error free.
A match between transmitted parity and receiver-calculated parity does not
guarantee that the data has not been corrupted. Indeed, if even numbers of errors occur in
a single character, then the parity for the corrupted data will be the same state as the good
data. For instance, suppose the two lowest bits in the character B were bad as seen in
Figure 4. The total number of ones in the data stream would still be an even count and the
parity bit calculated at the receiver would be a low state and would match the one
transmitted. This does not present a major problem, since the occurrence of two errors in
an eight-bit character is excessive and usually indicates a major problem in the system.
Such a problem would cause errors to occur in other characters and one of them would
eventually be detected. Since the occurrence of errors is extremely low, parity is
successful in detecting more than 95% of the errors that occur.
HAMMING CODES
If more error-correcting bits are included with a message, and if those bits can be
arranged such that different incorrect bits produce different error results, then bad bits
could be identified. In a 7-bit message, there are seven possible single bit errors, so three
error control bits could potentially specify not only that an error occurred but also which
bit caused the error.
Hamming studied the existing coding schemes, including two-of-five, and
generalized their concepts. To start with, he developed a nomenclature to describe the
system, including the number of data bits and error-correction bits in a block. For
instance, parity includes a single bit for any data word, so assuming ASCII words with 7-
bits, Hamming described this as an (8,7) code, with eight bits in total, of which 7 are data.
The repetition example would be (3,1), following the same logic. The code rate is the
second number divided by the first, for our repetition example, 1/3.
Hamming was interested in two problems at once; increasing the distance as much
as possible, while at the same time increasing the code rate as much as possible. The first
step in the process is to determine how many Hamming bits (H) are to be inserted
between the message (M) bits. Then their actual placement is selected. The number of
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6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
bits in the message (M) are counted and used to solve the following equation to
determine the number of Hamming (H) bits:
2H ≥ M+H-1
5. RESULT
Encoding waveform
Decoding waveform
6. CONCLUSION
Using HDLC transceiver, the errors present at receiver end can be corrected. To
add flexibility and upgradability in HDLC protocol will be implemented by using FPGA
as a target technology.
The high level data link control (HDLC) protocol defined by the ISO provides a
transparent transmission Service at the data link layer of the ISO reference model. Many
protocol suites use an HDLC link layer, including X.25, The IP point-to-point protocol
(PPT) and SNA. It has been so widely implemented because it supports half duplex and
full duplex communication lines, point-to-point (peer to peer) and multipoint networks,
and switched or non switched channels. The procedures outlined in HDLC are designed
to permit synchronous, code-transparent data transmission. The HDLC Protocol is a
general purpose protocol, which Operates AT the data link layer of the OSI reference
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7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
model. The protocol uses the services of a physical layer, to provide communications
path between the transmitter and receiver. The users of the HDLC service provide PDUs,
which are encapsulated to form data link layer frames.
HDLC is the basis for a wide variety of data link layer protocols. Regardless of the
data link protocol, most HDLC framing, bit stuffing, and CRC generation is performed
by the serial controller chips with the specific protocol stack software supplying the rest
of the necessary fields (see Layer 2 diagram on page two). This means that most WAN
cards can be adapted to any HDLC derived protocol.
7. REFERENCES
1. Guozheng Li Nanlin Tan State Key Lab. of Rail Traffic Control & Safety, Beijing
Jiaotong Univ., Beijing, China “Design and Implementation of HDLC Protocol
and Manchester Encoding Based on FPGA in Train Communication Network”,
International Journal of Scientific & Engineering Research Volume 2, Issue 3,
March-2011 5 ISSN 2229-5518 IJSER © 2011.
2. Arshak, K. Jafer, E. McDonagh, D. Ibala, C.S. Univ. of Limerick, Limerick,
“Modelling and simulation of wireless sensor system for health monitoring using
HDL and Simulink mixed environment” Computers & Digital Techniques, IET
Sept. 2005
3. Gheorghiu, V., S. Kameda, T. Takagi, K. Tsubouchi and F. Adachi, 2008.
"Implementation of frequency domain equalizer for single carrier transmission," In
Proceedings of the 4th International Conference on Wireless Communications,
Networking and Mobile Computing, WiCOM '08.
4. Jun Wang; Wenhao Zhang; Yuxi Zhang; Wei Wu; Weiguang Chang; Sch. of
Electron. & Inf. Eng., Beihang Univ. (BUAA), Beijing, China “Design and
implementation of HDLC procedures based on FPGA” , Anti- ounterfeiting,
Security, and Identification in Communication, 2009. ASID 2009. 3rd
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