proxyc CSAPP Web proxy NAME IMPORTANT Giv.pdfajay1317
/* # INPUT: a node z in the AVL Tree # OUTPUT: the new root node r of the subtree originally
rooted at z before the restructure/rebalancing at z # PRECONDITION: z is the only unbalanced
node in the subtree that it roots; the difference in height of its children is exactly 2 #
POSTCONDITION: the subtree originally rooted at z is a proper AVL subtree with node heights
properly set AVLTreeMap: : Node* AVLTreeMap::rebalance(AVLTreeMap::Node* z) {
AVLTreeMap::Node* r=z; // Your code here return r;.
httplinux.die.netman3execfork() creates a new process by.docxadampcarr67227
http://linux.die.net/man/3/exec
fork() creates a new process by duplicating the calling process. The new process, referred to as the child, is an exact duplicate of the calling process, referred to as the parent#include <unistd.h>pid_t fork(void);
The exec() family of functions replaces the current process image with a new process image. The functions described in this manual page are front-ends for execve(2). (See the manual page for execve(2) for further details about the replacement of the current process image.)
The exec() family of functions include execl, execlp, execle, execv, execvp, and execvpe to execute a file.
The ANSI prototype for execl() is:
int execl(const char *path, const char *arg0,..., const char *argn, 0)
http://www.cems.uwe.ac.uk/~irjohnso/coursenotes/lrc/system/pc/pc4.htm #inciude <stdio.h> #inciude <unistd.h> main() { execl("/bin/ls", "ls", "-l", 0); printf("Can only get here on error\n"); }
The first parameter to execl() in this example is the full pathname to the ls command. This is the file whose contents will be run, provided the process has execute permission on the file. The rest of the execl() parameters provide the strings to which the argv array elements in the new program will point. In this example, it means that the ls program will see the string ls pointed to by its argv[0], and the string -l pointed to by itsargv[1]. In addition to making all these parameters available to the new program, the exec() calls also pass a value for the variable: extern char **environ;
This variable has the same format as the argv variable except that the items passed via environ are the values in the environment of the process (like any exported shell variables), rather than the command line parameters. In the case of execl(), the value of the environ variable in the new program will be a copy of the value of this variable in the calling process.
The execl() version of exec() is fine in the circumstances where you can ex-plicitly list all of the parameters, as in the previous example. Now suppose you want to write a program that doesn't just run ls, but will run any program you wish, and pass it any number of appropriate command line parameters. Obviously, execl() won't do the job.
The example program below, which implements this requirement, shows, however, that the system call execv() will perform as required: #inciude <stdio.h> main(int argc, char **argv) { if (argc==1) { printf("Usage: run <command> [<paraneters>]\n"); exit(1) } execv(argv[l], &argv[1)); printf("Sorry... couldn't run that!\n"); }
The prototype for execv() shows that it only takes two parameters, the first is the full pathname to the command to execute and the second is the argv value you want to pass into the new program. In the previous example this value was derived from the argv value passed into the run command, so that the run command can take the command line parameter values you pass it and just pass them on. int execl(.
proxyc CSAPP Web proxy NAME IMPORTANT Giv.pdfajay1317
/* # INPUT: a node z in the AVL Tree # OUTPUT: the new root node r of the subtree originally
rooted at z before the restructure/rebalancing at z # PRECONDITION: z is the only unbalanced
node in the subtree that it roots; the difference in height of its children is exactly 2 #
POSTCONDITION: the subtree originally rooted at z is a proper AVL subtree with node heights
properly set AVLTreeMap: : Node* AVLTreeMap::rebalance(AVLTreeMap::Node* z) {
AVLTreeMap::Node* r=z; // Your code here return r;.
httplinux.die.netman3execfork() creates a new process by.docxadampcarr67227
http://linux.die.net/man/3/exec
fork() creates a new process by duplicating the calling process. The new process, referred to as the child, is an exact duplicate of the calling process, referred to as the parent#include <unistd.h>pid_t fork(void);
The exec() family of functions replaces the current process image with a new process image. The functions described in this manual page are front-ends for execve(2). (See the manual page for execve(2) for further details about the replacement of the current process image.)
The exec() family of functions include execl, execlp, execle, execv, execvp, and execvpe to execute a file.
The ANSI prototype for execl() is:
int execl(const char *path, const char *arg0,..., const char *argn, 0)
http://www.cems.uwe.ac.uk/~irjohnso/coursenotes/lrc/system/pc/pc4.htm #inciude <stdio.h> #inciude <unistd.h> main() { execl("/bin/ls", "ls", "-l", 0); printf("Can only get here on error\n"); }
The first parameter to execl() in this example is the full pathname to the ls command. This is the file whose contents will be run, provided the process has execute permission on the file. The rest of the execl() parameters provide the strings to which the argv array elements in the new program will point. In this example, it means that the ls program will see the string ls pointed to by its argv[0], and the string -l pointed to by itsargv[1]. In addition to making all these parameters available to the new program, the exec() calls also pass a value for the variable: extern char **environ;
This variable has the same format as the argv variable except that the items passed via environ are the values in the environment of the process (like any exported shell variables), rather than the command line parameters. In the case of execl(), the value of the environ variable in the new program will be a copy of the value of this variable in the calling process.
The execl() version of exec() is fine in the circumstances where you can ex-plicitly list all of the parameters, as in the previous example. Now suppose you want to write a program that doesn't just run ls, but will run any program you wish, and pass it any number of appropriate command line parameters. Obviously, execl() won't do the job.
The example program below, which implements this requirement, shows, however, that the system call execv() will perform as required: #inciude <stdio.h> main(int argc, char **argv) { if (argc==1) { printf("Usage: run <command> [<paraneters>]\n"); exit(1) } execv(argv[l], &argv[1)); printf("Sorry... couldn't run that!\n"); }
The prototype for execv() shows that it only takes two parameters, the first is the full pathname to the command to execute and the second is the argv value you want to pass into the new program. In the previous example this value was derived from the argv value passed into the run command, so that the run command can take the command line parameter values you pass it and just pass them on. int execl(.
Linux kernel tracing superpowers in the cloudAndrea Righi
The Linux 4.x series introduced a new powerful engine of programmable tracing (BPF) that allows to actually look inside the kernel at runtime. This talk will show you how to exploit this engine in order to debug problems or identify performance bottlenecks in a complex environment like a cloud. This talk will cover the latest Linux superpowers that allow to see what is happening “under the hood” of the Linux kernel at runtime. I will explain how to exploit these “superpowers” to measure and trace complex events at runtime in a cloud environment. For example, we will see how we can measure latency distribution of filesystem I/O, details of storage device operations, like individual block I/O request timeouts, or TCP buffer allocations, investigating stack traces of certain events, identify memory leaks, performance bottlenecks and a whole lot more.
Azul Virtual Machine Engineer Douglas Hawkins describes how decisions made by the JVM affect how your code is compiled and run. Learn how this affects application performance and what steps you can take to optimize how the JVM acts on your code.
Program Assignment Process ManagementObjective This program a.docxwkyra78
Program Assignment : Process Management
Objective: This program assignment is given to the Operating Systems course to allow the students to figure out how a single process (parent process) creates a child process and how they work on Unix/Linux(/Mac OS X/Windows) environment. Additionally, student should combine the code for describing inter-process communication into this assignment. Both parent and child processes interact with each other through shared memory-based communication scheme or message passing scheme.
Environment: Unix/Linux environment (VM Linux or Triton Server, or Mac OS X), Windows platform
Language: C or C++, Java
Requirements:
i. You have wide range of choices for this assignment. First, design your program to explain the basic concept of the process management in Unix Kernel. This main idea will be evolved to show your understanding on inter-process communication, file processing, etc.
ii. Refer to the following system calls:
- fork(), getpid(), family of exec(), wait(), sleep() system calls for process management
- shmget(), shmat(), shmdt(), shmctl() for shared memory support or
- msgget(), msgsnd(), msgrcv(), msgctl(), etc. for message passing support
iii. The program should present that two different processes, both parent and child, execute as they are supposed to.
iv. The output should contain the screen capture of the execution procedure of the program.
v. Interaction between parent and child processes can be provided through inter-process communication schemes, such as shared-memory or message passing schemes.
vi. Result should be organized as a document which explains the overview of your program, code, execution results, and the conclusion including justification of your program, lessons you've learned, comments, etc.
Note:
i. In addition, please try to understand how the local and global variables work across the processes
ii. read() or write () functions are used to understand how they work on the different processes.
iii. For extra credit, you can also incorporate advanced features, like socket or thread functions, into your code.
Examples:
1. Process Creation and IPC with Shared Memory Scheme
=============================================================
#include <stdio.h>
#include <sys/shm.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
int main(){
pid_t pid;
int segment_id; //allocate the memory
char *shared_memory; //pointer to memory
const int size = 4096;
segment_id = shmget(IPC_PRIVATE, size, S_IRUSR | S_IWUSR);
shared_memory = (char *) shmat(segment_id, NULL, 0);
pid = fork();
if(pid < 0) { //error
fprintf(stderr, "Fork failed");
return 1;
}
else if(pid == 0){ //child process
char *child_shared_memory;
child_shared_memory = (char *) shmat(segment_id,NULL,0); //attach mem
sprintf(child_shared_memory, "Hello parent process!"); //write to the shared mem
shmdt(child_shared_memory);
}
else ...
Assignment of SOS operating systemThe file lmemman.c has one incom.pdfsktambifortune
Assignment of SOS operating system
The file lmemman.c has one incomplete function with TODO blocks. Finish these blocks to
complete the assignment.
bool init_logical_memory(PCB *p, uint32_t code_size);
This function initializes a process’ logical address space. This involves allocating frames for the
process code, stacks, page directory and page tables, and then setting them up. The PCB is
passed in the argument p, and the number of bytes in the process’ code and data is in the
argument code_size. The function should return TRUE if all goes well; otherwise FALSE. Any
frames allocated in the function must be freed if FALSE is returned.
This should be able to work under SOS operating system.
Here is the lmenman.c file:
////////////////////////////////////////////////////////
// The NAIVE Logical Memory Manager
//
// Divides memory into 4KB pages and allocates from them
#include \"kernel_only.h\"
// kernel page directory will be placed at frame 257
PDE *k_page_directory = (PDE *)(0xC0101000);
// page table entries for the 768th page directory entry will be placed
// at frame 258; 768th entry corresponds to virtual address range
// 3GB to 3GB+4MB-1 (0xC0000000 to 0xC03FFFFF)
PTE *pages_768 = (PTE *)(0xC0102000);
/*** Initialize logical memory for a process ***/
// Allocates physical memory and sets up page tables;
// we need to allocate memory to hold the program code and
// data, the stack, the page directory, and the required
// page tables
// called by runprogram.c; this function does not load the
// program from disk to memory (done in scheduler.c)
bool init_logical_memory(PCB *p, uint32_t code_size) {
// TODO: see background material on what this function should
// do. High-level objectives are:
// 1) calculate the number of frames necessary for program code,
// user-mode stack and kernel-mode stack
// 2) allocate frames for above
// 3) determine beginning physical address of program code,
// user-mode stack and kernel-mode stack
// 4) calculate the number of frames necessary for page directory
// and page tables
// 5) allocate frames for above
// 6) set up page directory and page tables
// 7) set mem struct in PCB: start_code, end_code, start_stack,
// start_brk, brk, and page_directory
// Return value: TRUE if everything goes well; FALSE if allocation
// of frames failed (you should dealloc any frames that may
// have already been allocated before returning)
// TODO: uncomment following line when you start working in
// this function
return FALSE;
}
/*** Initialize kernel\'s page directory and table ***/
void init_kernel_pages(void) {
uint32_t i;
// set up kernel page directory (users cannot touch this)
for (i=0; i<1024; i++) k_page_directory[i] = 0;
k_page_directory[768] = ((uint32_t)pages_768-KERNEL_BASE) | PDE_PRESENT |
PDE_READ_WRITE;
// map virtual (0xC0000000--0xC03FFFFF) to physical (0--0x3FFFFF)
for (i=0; i<1024; i++)
pages_768[i] = (i*4096) | PTE_PRESENT | PTE_READ_WRITE | PTE_GLOBAL;
// load page directory
load_CR3((uint32_t)k_pa.
Finding and fixing bugs is a major chunk of any developers time. This talk describes the basic rules for effective debugging in any language, but shows how the tools available in PHP can be used to find and fix even the most elusive error
Presentation from DICE Coder's Day (2010 November) by Andreas Fredriksson in the Frostbite team.
Goes into detail about Scope Stacks, which are a systems programming tool for memory layout that provides
• Deterministic memory map behavior
• Single-cycle allocation speed
• Regular C++ object life cycle for objects that need it
This makes it very suitable for games.
please read the attached file cearfully before telling me you can do.docxChereCheek752
please read the attached file cearfully before telling me you can do it.
I need a complete
power
point presentation (that incloud outlines and pictures) that pointing
3 main points
on the
topic
that is mentioned in the attached file + the speech for the slides that must be 5-7 min lon.
.
please read my post carefully.then place handshakei have the wor.docxChereCheek752
please read my post carefully.then place handshake
i have the work already but i want u do
introduction, background, and conclusion
for it.
and some changes on the paper that already written.
you just need to
add three pages on my paper
.
deadline 20-24 hours.
i attached my paper,
.
More Related Content
Similar to finalprojtemplatev5finalprojtemplate.gitignore# Ignore the b
Linux kernel tracing superpowers in the cloudAndrea Righi
The Linux 4.x series introduced a new powerful engine of programmable tracing (BPF) that allows to actually look inside the kernel at runtime. This talk will show you how to exploit this engine in order to debug problems or identify performance bottlenecks in a complex environment like a cloud. This talk will cover the latest Linux superpowers that allow to see what is happening “under the hood” of the Linux kernel at runtime. I will explain how to exploit these “superpowers” to measure and trace complex events at runtime in a cloud environment. For example, we will see how we can measure latency distribution of filesystem I/O, details of storage device operations, like individual block I/O request timeouts, or TCP buffer allocations, investigating stack traces of certain events, identify memory leaks, performance bottlenecks and a whole lot more.
Azul Virtual Machine Engineer Douglas Hawkins describes how decisions made by the JVM affect how your code is compiled and run. Learn how this affects application performance and what steps you can take to optimize how the JVM acts on your code.
Program Assignment Process ManagementObjective This program a.docxwkyra78
Program Assignment : Process Management
Objective: This program assignment is given to the Operating Systems course to allow the students to figure out how a single process (parent process) creates a child process and how they work on Unix/Linux(/Mac OS X/Windows) environment. Additionally, student should combine the code for describing inter-process communication into this assignment. Both parent and child processes interact with each other through shared memory-based communication scheme or message passing scheme.
Environment: Unix/Linux environment (VM Linux or Triton Server, or Mac OS X), Windows platform
Language: C or C++, Java
Requirements:
i. You have wide range of choices for this assignment. First, design your program to explain the basic concept of the process management in Unix Kernel. This main idea will be evolved to show your understanding on inter-process communication, file processing, etc.
ii. Refer to the following system calls:
- fork(), getpid(), family of exec(), wait(), sleep() system calls for process management
- shmget(), shmat(), shmdt(), shmctl() for shared memory support or
- msgget(), msgsnd(), msgrcv(), msgctl(), etc. for message passing support
iii. The program should present that two different processes, both parent and child, execute as they are supposed to.
iv. The output should contain the screen capture of the execution procedure of the program.
v. Interaction between parent and child processes can be provided through inter-process communication schemes, such as shared-memory or message passing schemes.
vi. Result should be organized as a document which explains the overview of your program, code, execution results, and the conclusion including justification of your program, lessons you've learned, comments, etc.
Note:
i. In addition, please try to understand how the local and global variables work across the processes
ii. read() or write () functions are used to understand how they work on the different processes.
iii. For extra credit, you can also incorporate advanced features, like socket or thread functions, into your code.
Examples:
1. Process Creation and IPC with Shared Memory Scheme
=============================================================
#include <stdio.h>
#include <sys/shm.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
int main(){
pid_t pid;
int segment_id; //allocate the memory
char *shared_memory; //pointer to memory
const int size = 4096;
segment_id = shmget(IPC_PRIVATE, size, S_IRUSR | S_IWUSR);
shared_memory = (char *) shmat(segment_id, NULL, 0);
pid = fork();
if(pid < 0) { //error
fprintf(stderr, "Fork failed");
return 1;
}
else if(pid == 0){ //child process
char *child_shared_memory;
child_shared_memory = (char *) shmat(segment_id,NULL,0); //attach mem
sprintf(child_shared_memory, "Hello parent process!"); //write to the shared mem
shmdt(child_shared_memory);
}
else ...
Assignment of SOS operating systemThe file lmemman.c has one incom.pdfsktambifortune
Assignment of SOS operating system
The file lmemman.c has one incomplete function with TODO blocks. Finish these blocks to
complete the assignment.
bool init_logical_memory(PCB *p, uint32_t code_size);
This function initializes a process’ logical address space. This involves allocating frames for the
process code, stacks, page directory and page tables, and then setting them up. The PCB is
passed in the argument p, and the number of bytes in the process’ code and data is in the
argument code_size. The function should return TRUE if all goes well; otherwise FALSE. Any
frames allocated in the function must be freed if FALSE is returned.
This should be able to work under SOS operating system.
Here is the lmenman.c file:
////////////////////////////////////////////////////////
// The NAIVE Logical Memory Manager
//
// Divides memory into 4KB pages and allocates from them
#include \"kernel_only.h\"
// kernel page directory will be placed at frame 257
PDE *k_page_directory = (PDE *)(0xC0101000);
// page table entries for the 768th page directory entry will be placed
// at frame 258; 768th entry corresponds to virtual address range
// 3GB to 3GB+4MB-1 (0xC0000000 to 0xC03FFFFF)
PTE *pages_768 = (PTE *)(0xC0102000);
/*** Initialize logical memory for a process ***/
// Allocates physical memory and sets up page tables;
// we need to allocate memory to hold the program code and
// data, the stack, the page directory, and the required
// page tables
// called by runprogram.c; this function does not load the
// program from disk to memory (done in scheduler.c)
bool init_logical_memory(PCB *p, uint32_t code_size) {
// TODO: see background material on what this function should
// do. High-level objectives are:
// 1) calculate the number of frames necessary for program code,
// user-mode stack and kernel-mode stack
// 2) allocate frames for above
// 3) determine beginning physical address of program code,
// user-mode stack and kernel-mode stack
// 4) calculate the number of frames necessary for page directory
// and page tables
// 5) allocate frames for above
// 6) set up page directory and page tables
// 7) set mem struct in PCB: start_code, end_code, start_stack,
// start_brk, brk, and page_directory
// Return value: TRUE if everything goes well; FALSE if allocation
// of frames failed (you should dealloc any frames that may
// have already been allocated before returning)
// TODO: uncomment following line when you start working in
// this function
return FALSE;
}
/*** Initialize kernel\'s page directory and table ***/
void init_kernel_pages(void) {
uint32_t i;
// set up kernel page directory (users cannot touch this)
for (i=0; i<1024; i++) k_page_directory[i] = 0;
k_page_directory[768] = ((uint32_t)pages_768-KERNEL_BASE) | PDE_PRESENT |
PDE_READ_WRITE;
// map virtual (0xC0000000--0xC03FFFFF) to physical (0--0x3FFFFF)
for (i=0; i<1024; i++)
pages_768[i] = (i*4096) | PTE_PRESENT | PTE_READ_WRITE | PTE_GLOBAL;
// load page directory
load_CR3((uint32_t)k_pa.
Finding and fixing bugs is a major chunk of any developers time. This talk describes the basic rules for effective debugging in any language, but shows how the tools available in PHP can be used to find and fix even the most elusive error
Presentation from DICE Coder's Day (2010 November) by Andreas Fredriksson in the Frostbite team.
Goes into detail about Scope Stacks, which are a systems programming tool for memory layout that provides
• Deterministic memory map behavior
• Single-cycle allocation speed
• Regular C++ object life cycle for objects that need it
This makes it very suitable for games.
Similar to finalprojtemplatev5finalprojtemplate.gitignore# Ignore the b (20)
please read the attached file cearfully before telling me you can do.docxChereCheek752
please read the attached file cearfully before telling me you can do it.
I need a complete
power
point presentation (that incloud outlines and pictures) that pointing
3 main points
on the
topic
that is mentioned in the attached file + the speech for the slides that must be 5-7 min lon.
.
please read my post carefully.then place handshakei have the wor.docxChereCheek752
please read my post carefully.then place handshake
i have the work already but i want u do
introduction, background, and conclusion
for it.
and some changes on the paper that already written.
you just need to
add three pages on my paper
.
deadline 20-24 hours.
i attached my paper,
.
Please read the attachment.Please write a pure Essay Paper. Plea.docxChereCheek752
Please read the attachment.
Please write a pure Essay Paper. Please read the instructions. Then follow the grade sheet. Please fully understand both attachments. Also, the essay will be scanned before student upload it for a final grade. Please make sure error is free. And references are given with cited.
.
Please read first because this Assignment is for correction.Plea.docxChereCheek752
Please read first because this Assignment is for correction.
Please, read through the corrections before sending me messages. Because, if you don’t I will not response to your messages. Also, I will attached two more articles for whoever I choose to help me with this assignment. In addition, please, remove the introduction, and also attach a sample of a “Needs Assessment”
Topic Needs Assessment
Title: HIV among Young Men Who Have Sex with Men
Section 1: Background Information
All of this is opinion and needs to come out.
Sex is seemingly as old as the world is. However, sex among men, and especially young men having sex with men has not always been in the books of history. This is arguably one of the latest practices, although some sources have claims of sex among men after the antediluvian period. While sex has positive effects such as procreation, there are some negative effects which include contraction of deadly sexually transmitted diseases.
One such disease is HIV/AIDS.
HIV/AIDS is an acronym for
Human ImmunoDefiency Virus/ Acquired Immune Deficiency Syndrome
not capitalized
. Da
ta
from the Centers for Disease Control and Prevention (2015) sho
ws
that
while
over one million people aged above 13 years of age were living with the disease in the US by the year 2014
,
with
an average of 40,000 new infections are recorded each year (Centers for Disease Control and Prevention [CDC], 2015)
when you use the word while...it indicates as opposite statement coming..and that is not what this sentence did
. The high number of people who are ignorant about their HIV status
and
those who purposely choose to ignore it
has
continued to increase the risk levels for other uninfected people in the world, among them being young men who have sex with men
isn’t it possible that they are one of the above?
.
In this areas and/or introduction...you should be discussing morbidity, mortality,....you need to highlight incidence is higher in this group than in others
Introduction
The issue of young men having sex with other men has continued to be a thorny issue for a number of years, dividing the society between those who support this practice and those who oppose it. Supporters of young men having sex with other men argue that people have a right to decide their sexual orientation and preferences without undue pressure from external forces. However, those who oppose this practice argue that it emanated from social decay and as such should not be supported. One common point of agreement between these two camps is that the practice of young men having sex with men is risk and has the capability to cause grave danger to these men.
opinion
Although sex even among heterosexual could turn out to be risk and a cause of contraction of dangerous sexually transmitted diseases and infections, the risk of contraction of such health complications is doubly higher among young men who have sex with other men.
There are several reasons that c.
Please read below, and write esaay.I need 3 pages.Overvi.docxChereCheek752
Please read below, and write esaay.
I need 3 pages.
Overview
Many people are unaware of just how much they use media. It is important for us to have an awareness of the various types of media that inundate our culture and the degree to which we use those media. This is a component of media literacy.
Instructions
For this assignment, you will keep 3 days of media logs and then write a reflective essay. Please keep a daily journal that records your media use for three days. Track you use of all of the following (even if you don't use something, please make a note of that). Keep track of the time periods when you use it and what you are using it for.
Computer—online
Computer--offline
TV
Newspapers/Magazines
Radio
Stereo/CD
Books
Telephone
Other
For each day, keep a detailed record of how much time you spend using each different medium, and the purpose of the media use (e.g., talking to parents, playing music while studying, recreational TV, etc.) Keep daily logs; you may turn in your "Media Logs" as a list, a table, in columns or in whatever format you choose.
In addition to the 3 days of logs, please write a reflective essay (about 2-4 pages, double spaced) that comments on what you learned about your media use by doing this assignment. For the essay, you may want to think about: what did you learn? did anything surprise you? did you notice any patterns in your media use? has your media use changed? why do you use some forms of media more or less? what role do you think media plays in most people's lives?...)
By Sunday at 11:59 pm PST, please submit:
the 3 days of media logs, AND
your essay
.
Please Read Before RespondingI need assistance with a .docxChereCheek752
***Please Read Before Responding***
I need assistance with a well thought out, well written AWP essay the Essay must use evidence (concrete details from the story) to support your answer. Five paragraphs.
http://www.ciaranhinds.eu/pdf/crucible3.pdf
.
Please provide response to the below post. Topic #1) You are an .docxChereCheek752
Please provide response to the below post.
Topic #1) You are an administrator for the Contoso Corporation and you are responsible for multiple Hyper-V hosts. Often, the developers need to create virtual machines so that they can test their applications. Describe the steps you should take so that developers can create and manage their own machines yet not have direct access to the Hyper-V hosts.
Topic #2) You are an administrator for the Contoso Corporation, which has approximately 400 servers running Windows Server 2012 R2, 50 servers running Windows Server 2012, and 200 servers running Windows Server 2008 R2. You also have several virtual machines running Windows 7 and Windows 8/8.1 and you have approximately 15 domain controllers. From time to time, you field requests in which you need to specify when a user has logged in and when a user has accessed confidential documents. Describe how to handle such requests.
.
Please provide an annotation for the two articles attached AND ide.docxChereCheek752
Please provide an annotation for the two articles attached AND identify three common themes in both articles.
Note the purpose of the article, the participants/subject of the study, the conclusions drawn by the author(s), and the validity of the conclusions. Evaluate the article: is it a credible source? Describe the credibility of the author – are there any biases? How well did the author support his or her assertions? Did they provide an adequate literature review? Were there any limitations?
Due tomorrow, 02/07/2017 at noon.
Note the purpose of the article, the participants/subject of the study, the conclusions drawn by the author(s), and the validity of the conclusions. Evaluate the article: is it a credible source? Describe the credibility of the author – are there any biases? How well did the author support his or her assertions? Did they provide an adequate literature review? Were there any limitations?
.
Please provide a statement that addresses your reasons for transferr.docxChereCheek752
Please provide a statement that addresses your reasons for transferring and the objectives you hope to achieve. You can type directly into the box, or you can paste text from another source. (250-650 words). I'm a Bachelor Student, who wants to transfer to another university, so they need this essay.
.
Please provide a brief response to the following questions1) How .docxChereCheek752
Please provide a brief response to the following questions:
1) How did Dr. Herskovits' discoveries about African people and their cultural practices support Dr. Woodson's beliefs about African history and the effect of Eurocentric thinking on distorting the culture, history, knowledge, and understanding of people of African descent?
2) According to Dr. Cheikh Anta Diop, which people are responsible for Egyptian culture and civilization; how does he support this claim and why is this Afrocentric perspective so controversial?
.
PLEASE NOTE OF SOURCESMATERIALS ALSO INCLUDED---USE THEMT.docxChereCheek752
PLEASE NOTE OF SOURCES/MATERIALS ALSO INCLUDED---USE THEM
TWO ASSIGNMENTS
TWO ASSIGNMENTS
TWO ASSIGNMENTS
TWO ASSIGNMENTS
TWO ASSIGNMENTS
TWO ASSIGNMENTS
.
Please note that the following vignettes represent samples of the ty.docxChereCheek752
Please note that the following vignettes represent samples of the types of questions you will be asked to respond to on the comprehensive exam. You will NOT receive these questions on the comprehensive exam; they are for study purposes only. Vignette Please compose a well-written and organized essay in response to each of the following questions. When writing your essays, please 1.Use APA (6th edition) Style, with 1-inch margins, double-spaced, 12 font, with a reference list at the end. 2.Write clearly and concisely. 3.Cite appropriate, and especially current, literature (empirical and/or theoretical). 4.Avoid all sexist idioms and allusions. 5.Remember to demonstrate your multicultural competence where appropriate. Vignette: Utilize this scenario for all of your responses A 42-year-old African American woman was brought to the emergency room by police officers for evaluation prior to going to jail to await disposition. She reported that she had been shopping when "something happened." She said that she had no recollection of events between the time she entered the store and an hour later, when she was arrested for shoplifting in a nearby department store with a considerable amount of stolen property on her person. She protested her innocence and became so agitated, belligerent, and profane that the arresting officers took her to the hospital for evaluation. At the hospital she reported that two years previously she had been arrested for shoplifting and had had amnesia for the act. The charges against her were then dropped because she explained that both the shoplifting and the amnesia resulted from her forgetting to eat after taking her insulin. Of note, her blood-sugar level on testing in the emergency room was elevated. The patient calmed down appearing asymptomatic after the evaluation and was transferred to jail pending a preliminary hearing. When she learned that her release was planned for the next day and that the charges against her would not be dropped, she became extremely agitated, angry, and abusive to the officers. Shortly thereafter, she complained of a headache and said she had no recollection of her abusive behavior. Later that evening she accosted an officer angrily. When the officer responded and addressed the patient by name, "Naomi," the patient said that her name was "Oprah" and that she would not allow herself to be called "Naomi," whom she described as a "wimp and a loser." "Oprah’s" voice and movement were somewhat different from those of "Naomi." She claimed that she had done the shoplifting and stepped back so that "Naomi" could be caught and humiliated, and that if she had wanted to, she could have evaded detection easily. She was returned to the ER and subsequently admitted to the inpatient psychiatric unit for observation. For the next two days, the patient had many apparent switches of personality, accompanied by conspicuous changes in dress, makeup, and demeanor. On several occasions "Oprah" was disrupti.
Please no plagiarism. I have attached an example to go by. The popul.docxChereCheek752
Please no plagiarism. I have attached an example to go by. The population I chose and currently work with are incarcerated juveniles, so at-risk youth.
Boundary Issues
It may not be possible or reasonable for counselors to always avoid dual relationships with clients. For example, counselors who live and work in small rural communities may attend the same religious institutions as their clients, or use the same libraries, doctors, or other services. In these multiple-relationship situations, counselors would not be in violation of ethical standards if they took reasonable steps to protect their objectivity and efficacy, and to avoid possibilities of exploitation or harm.
Counselors and supervisors usually consider dual relationships on a continuum of risk. As you work through the notion of dual relationships, you should consider the relationship with your client and the context of the situation. It is also important to consider the impact of dual roles on the power dynamics of the therapeutic relationship. For example, clients, students, and supervisees have less experience, knowledge, and power compared with licensed counselors and supervisors. Consequently, they are less likely to recognize inappropriate boundary crossings or to express their concerns about these crossings. It is your responsibility as an ethical practitioner to monitor and ensure appropriate boundaries across all related counseling situations.
For this Discussion, review the
Clinical Mental Health Counseling: Boundary Issues
media and consider the population that you are interested in working with as a professional counselor. Then, review the Learning Resources for this week and explore potential boundary issues you may encounter while working with this population. Reflect on potential benefit or harm related to boundary crossing. Finally, consider potential consultants who might be able to address any boundary issues.
Post by Day 3
a brief description of the population you selected. Then, explain any potential boundary issues you anticipate may be challenging in working with this population and explain why. Explain the potential benefit or harm associated with boundary crossing with this population. Finally, explain who you might consult with to address this boundary issue and why.
Be sure to use the Learning Resources and the current literature to support your response.
Respond by Day 5
and expand on your colleague’s posting by providing an alternate perspective on how you would work with your colleague’s selected population. Provide potential boundary crossing challenges that your colleague did not discuss and offer potential solutions for addressing these challenges.
Required Resources
Note:
To access this week's required library resources, please click on the link to the Course Readings List, found in the
Course Materials
section of your Syllabus.
Readings
Herlihy, B., & Corey, G. (2015).
ACA ethical standards casebook
(7th ed.). Alexandria, VA: American Cou.
PLEASE NO PLAGIARIZE!! Have 10 hours to fullfil this work. 1page or .docxChereCheek752
PLEASE NO PLAGIARIZE!! Have 10 hours to fullfil this work. 1page or few paragraphs.
-- Women have a long history of being considered inferior to men. However, during the middle to the late 20th century, the women’s rights movement began to improve the plight of women in Western society by granting them access to societal positions previously held only by men.
-- Some people claim that women have finally achieved equality with men in the 21st century; others are not convinced.
-- How will you describe the status of equality between men and women in contemporary Western culture?
-- Do you see any major areas where women are still discriminated against on a large scale? If so, give at least two examples. If not, rationalize your views.
.
Please Paraphrase the following into a more scholarly toneI f.docxChereCheek752
Please Paraphrase the following into a more scholarly tone:"
"I feel like after reading these excerpts I feel like the first answer clarified what exactly Gus Casely-Hayford was really trying to figure out about Ethiopian history. It was clear that he was trying to figure out its history, however, it was difficult to put the pieces together and pinpoint things that could lead to it's past. I don't think it was a specific sentence it was really just how they answered it that helped me put it together.
A sentence in another paragraph that clarified what the answer was at number two when it said "After this, Ethiopia switched to Christianity, which has a direct link with the history of the kingdom. The Patriarch claims that the Ark of the Covenant was brought to Ethiopia". It clarifies what the patriarch really meant when he said that they had accepted the old testament.
These excerpts can help when I am doing homework because they can be used as a structure when answering questions for my future homework. In my next homework, I will aim to have more references and actually pinpoint what the answer is because I feel like I do not fully answer the question I only answer it partially. So I can turn in something rather than nothing. It is sometimes difficult to understand the main idea or interpret what some people are saying in the documentaries. The readings, however, are easier to understand.
.
Please only respond if you are familiar with raspberry piIam loo.docxChereCheek752
Please only respond if you are familiar with raspberry pi
Iam looking to send Binary data over the GPIO pins. I need to use one of the input and output pin to send binary data on the output.
If you are very familiar with Raspberry pi please message me.
THank you
.
Please note this is 2 ASSIGNMENTS ......Please only orginial work on.docxChereCheek752
Please note this is 2 ASSIGNMENTS ......Please only orginial work only and please follow the instruction provided
Assignment 1: Week 3 COURSE PROJECT
Week 3: Create the Database
Create the database and associated tables in your database environment.
Assignment 2: Week 3 ILAB
iLab 3: Database Creation and Table Manipulation
.
PLEASE NEED TWO RESPONSES TWO HUNDRED WORDS EACHDistinguish b.docxChereCheek752
PLEASE NEED TWO RESPONSES TWO HUNDRED WORDS EACH:
Distinguish between various factions/denominations within Christianity (Catholic/Protestant/Orthodox/etc) and their impact on mainstream (dominant) expression of how Christianity is viewed by those on the "outside."
Consider the viewpoints we saw represented in
Once I Was a Beehive.
How does it differ or compare to popular or mainstream faith as you know it? Of course, it is one interpretation of faith in Jesus and how it impacts daily life (and during troubling times, as seen in the film).
For example, if I walked into one church, I might find folks picking up and handling snakes, singing rather loudly and outwardly in their expressions of worship. If I went to the congregation next door the following Sunday, I might find a church that barely whispered, used no music at all, and perhaps simply followed a monotone lecture/sermon style delivered over the course of an hour, or two, or three! Both representing the same organism/religion...
Please respond with no less than 200 words, and respond to at least one of your classmate's post.
.
Please no plagiarism and make sure you are able to access all resour.docxChereCheek752
Please no plagiarism and make sure you are able to access all resource on your own before you bid. I need this completed by 10/21/17 at 12pm.
Application:
Applying Theoretical Interventions for Clients Experiencing Life Transition and Developmental Issues, Part II
Marriage, couple, and family counselors have varying caseloads. What they all have in common is that their group of clients—whether large or small—represents the variety of human experience. Even those counselors with a specific clinical focus see variety in the ways in which specific issues manifest in different relationships. Part of the goal of your counseling program is to expose you to varying scenarios so that when you are faced with differing client situations, you will have the evidence-based research knowledge, flexibility, analytical skills, and theory-integration practice to know the best course of action to take with a particular couple or family.
To prepare for this Application Assignment, select and view one movie from the list provided in this week’s Learning Resources. Begin to conceptualize the couple's or family’s problem through your theoretical orientation and identify interventions that you might use. Finally, begin to locate articles in the Walden Library that could be used to justify the interventions you selected.
The assignment (2–3 pages)
Identify the movie you selected and the life transition/developmental issue present in the couple/family.
Conceptualize the couple's/family's problem through your chosen theoretical orientation.
Describe two interventions you would use to address these couple/family issues and how you would use them. (
Note
: The interventions may not emerge from your chosen theoretical orientation.)
Justify the intervention you selected with two evidence-based research articles.
Support your Application Assignment with specific references to all resources used in its preparation. You are asked to provide a reference list for all resources, including those in the Learning Resources for this course.
Submit your assignment by
Day 7
.
Learning Resources
Required Resources
Media
Please select, obtain, and view one of the following movies to use with this week’s Application Assignment:
Please note:
These films are
not
available through Walden Library. Contact your instructor if you are unable to obtain a copy independently.
Movie: Rydell, M. (Director). (1981).
On golden pond
[Motion picture]. [With K. Hepburn, H. Fonda, & J. Fonda]. United States: IPC Films.
Movie: Demme, J. (Director). (2008).
Rachel getting married
[Motion picture]. [With A. Hathaway, R. DeWitt, & D. Winger]. United States: Sony Pictures Classics.
Movie: Redford, R. (Director). (1980).
Ordinary people
[Motion picture]. [With A. Sutherland, M. Tyler Moore, & J. Hirsch]. United States: Paramount Pictures.
Readings
Article: Haggan, P. S. (1998). Counseling adult children of aging parents.
Educational Gerontology
,
24
(4), 333. Ret.
Please need two posts of 200 words each. Discuss the ways in whi.docxChereCheek752
Please need two posts of 200 words each.
Discuss the ways in which Confucianism can or may weave into our everyday lives, given what you've read and watched/reviewed. Consider the ways you saw Confucianism as a religion and/or as a philosophy displayed in the film
Confucius
, focusing on the themes of bravery, self-sacrifice, respect, and loyalty. As you've been reading through the text, you'll find multiple arguments suggesting that Confucianism is less religion, more philosophy. What are your thoughts? Use examples from the film and text to support your conclusions.
.
Introduction to AI for Nonprofits with Tapp NetworkTechSoup
Dive into the world of AI! Experts Jon Hill and Tareq Monaur will guide you through AI's role in enhancing nonprofit websites and basic marketing strategies, making it easy to understand and apply.
Operation “Blue Star” is the only event in the history of Independent India where the state went into war with its own people. Even after about 40 years it is not clear if it was culmination of states anger over people of the region, a political game of power or start of dictatorial chapter in the democratic setup.
The people of Punjab felt alienated from main stream due to denial of their just demands during a long democratic struggle since independence. As it happen all over the word, it led to militant struggle with great loss of lives of military, police and civilian personnel. Killing of Indira Gandhi and massacre of innocent Sikhs in Delhi and other India cities was also associated with this movement.
Model Attribute Check Company Auto PropertyCeline George
In Odoo, the multi-company feature allows you to manage multiple companies within a single Odoo database instance. Each company can have its own configurations while still sharing common resources such as products, customers, and suppliers.
Read| The latest issue of The Challenger is here! We are thrilled to announce that our school paper has qualified for the NATIONAL SCHOOLS PRESS CONFERENCE (NSPC) 2024. Thank you for your unwavering support and trust. Dive into the stories that made us stand out!
How to Make a Field invisible in Odoo 17Celine George
It is possible to hide or invisible some fields in odoo. Commonly using “invisible” attribute in the field definition to invisible the fields. This slide will show how to make a field invisible in odoo 17.
Synthetic Fiber Construction in lab .pptxPavel ( NSTU)
Synthetic fiber production is a fascinating and complex field that blends chemistry, engineering, and environmental science. By understanding these aspects, students can gain a comprehensive view of synthetic fiber production, its impact on society and the environment, and the potential for future innovations. Synthetic fibers play a crucial role in modern society, impacting various aspects of daily life, industry, and the environment. ynthetic fibers are integral to modern life, offering a range of benefits from cost-effectiveness and versatility to innovative applications and performance characteristics. While they pose environmental challenges, ongoing research and development aim to create more sustainable and eco-friendly alternatives. Understanding the importance of synthetic fibers helps in appreciating their role in the economy, industry, and daily life, while also emphasizing the need for sustainable practices and innovation.
Welcome to TechSoup New Member Orientation and Q&A (May 2024).pdfTechSoup
In this webinar you will learn how your organization can access TechSoup's wide variety of product discount and donation programs. From hardware to software, we'll give you a tour of the tools available to help your nonprofit with productivity, collaboration, financial management, donor tracking, security, and more.
The French Revolution, which began in 1789, was a period of radical social and political upheaval in France. It marked the decline of absolute monarchies, the rise of secular and democratic republics, and the eventual rise of Napoleon Bonaparte. This revolutionary period is crucial in understanding the transition from feudalism to modernity in Europe.
For more information, visit-www.vavaclasses.com
Macroeconomics- Movie Location
This will be used as part of your Personal Professional Portfolio once graded.
Objective:
Prepare a presentation or a paper using research, basic comparative analysis, data organization and application of economic information. You will make an informed assessment of an economic climate outside of the United States to accomplish an entertainment industry objective.
4. // initialize the counters
this->globalCycles =0;
this->globalHits =0;
this->globalMisses =0;
this->globalEvictions =0;
// create your cache structure
// ...
// manual test code to see if the cache is behaving properly
// will need to be changed slightly to match the function prototy
pe
/*
cacheAccess(false, 0);
cacheAccess(false, 128);
cacheAccess(false, 256);
cacheAccess(false, 0);
cacheAccess(false, 128);
cacheAccess(false, 256);
*/
}
/*
Starts reading the tracefile and processing memory operations
.
*/
voidCacheController::runTracefile(){
cout <<"Input tracefile: "<< inputFile << endl;
cout <<"Output file name: "<< outputFile << endl;
// process each input line
string line;
// define regular expressions that are used to locate commands
regex commentPattern("==.*");
regex instructionPattern("I .*");
5. regex loadPattern(" (L )(.*)(,)([[:digit:]]+)$");
regex storePattern(" (S )(.*)(,)([[:digit:]]+)$");
regex modifyPattern(" (M )(.*)(,)([[:digit:]]+)$");
// open the output file
ofstream outfile(outputFile);
// open the output file
ifstream infile(inputFile);
// parse each line of the file and look for commands
while(getline(infile, line)){
// these strings will be used in the file output
string opString, activityString;
smatch match;// will eventually hold the hexadecimal addr
ess string
unsignedlongint address;
// create a struct to track cache responses
CacheResponse response;
// ignore comments
if(std::regex_match(line, commentPattern)|| std::regex_match(li
ne, instructionPattern)){
// skip over comments and CPU instructions
continue;
}elseif(std::regex_match(line, match, loadPattern)){
cout <<"Found a load op!"<< endl;
istringstream hexStream(match.str(2));
hexStream >> std::hex >> address;
outfile << match.str(1)<< match.str(2)<< match.str(3)<
< match.str(4);
cacheAccess(&response,false, address, stoi(match.str(4)
));
logEntry(outfile,&response);
}elseif(std::regex_match(line, match, storePattern)){
cout <<"Found a store op!"<< endl;
istringstream hexStream(match.str(2));
6. hexStream >> std::hex >> address;
outfile << match.str(1)<< match.str(2)<< match.str(3)<
< match.str(4);
cacheAccess(&response,true, address, stoi(match.str(4))
);
logEntry(outfile,&response);
}elseif(std::regex_match(line, match, modifyPattern)){
cout <<"Found a modify op!"<< endl;
istringstream hexStream(match.str(2));
// first process the read operation
hexStream >> std::hex >> address;
outfile << match.str(1)<< match.str(2)<< match.str(3)<
< match.str(4);
cacheAccess(&response,false, address, stoi(match.str(4)
));
logEntry(outfile,&response);
outfile << endl;
// now process the write operation
hexStream >> std::hex >> address;
outfile << match.str(1)<< match.str(2)<< match.str(3)<
< match.str(4);
cacheAccess(&response,true, address, stoi(match.str(4))
);
logEntry(outfile,&response);
}else{
throw runtime_error("Encountered unknown line format in trace
file.");
}
outfile << endl;
}
// add the final cache statistics
outfile <<"Hits: "<< globalHits <<" Misses: "<< globalMisse
s <<" Evictions: "<< globalEvictions << endl;
outfile <<"Cycles: "<< globalCycles << endl;
infile.close();
7. outfile.close();
}
/*
Report the results of a memory access operation.
*/
voidCacheController::logEntry(ofstream& outfile,CacheRespons
e* response){
outfile <<" "<< response->cycles;
if(response->hits >0)
outfile <<" hit";
if(response->misses >0)
outfile <<" miss";
if(response->evictions >0)
outfile <<" eviction";
}
/*
Calculate the block index and tag for a specified address.
*/
CacheController::AddressInfoCacheController::getAddressInfo(
unsignedlongint address){
AddressInfo ai;
// this code should be changed to assign the proper index and ta
g
return ai;
}
/*
This function allows us to read or write to the cache.
The read or write is indicated by isWrite.
address is the initial memory address
numByte is the number of bytes involved in the access
*/
voidCacheController::cacheAccess(CacheResponse* response,b
ool isWrite,unsignedlongint address,int numBytes){
8. // determine the index and tag
AddressInfo ai = getAddressInfo(address);
cout <<"tSet index: "<< ai.setIndex <<", tag: "<< ai.tag << e
ndl;
// your code should also calculate the proper number of cycles t
hat were used for the operation
response->cycles =0;
// your code needs to update the global counters that track the n
umber of hits, misses, and evictions
if(response->hits >0)
cout <<"Operation at address "<< std::hex << address <<"
caused "<< response->hits <<" hit(s)."<< std::dec << endl;
if(response->misses >0)
cout <<"Operation at address "<< std::hex << address <<"
caused "<< response-
>misses <<" miss(es)."<< std::dec << endl;
cout <<"-----------------------------------------"<< endl;
return;
}
finalprojtemplatev5/finalprojtemplate/src/CacheController.h
/*
Cache Simulator (Starter Code) by Justin Goins
Oregon State University
Spring Term 2021
9. */
#ifndef _CACHECONTROLLER_H_
#define _CACHECONTROLLER_H_
#include "CacheStuff.h"
#include <string>
#include <fstream>
class CacheController {
private:
struct AddressInfo {
unsigned long int tag;
unsigned int setIndex;
};
unsigned int globalCycles;
unsigned int globalHits;
unsigned int globalMisses;
10. unsigned int globalEvictions;
std::string inputFile, outputFile;
CacheInfo ci;
// function to allow read or write access to the cache
void cacheAccess(CacheResponse*, bool, unsigned
long int, int);
// function that can compute the index and tag
matching a specific address
AddressInfo getAddressInfo(unsigned long int);
// function to add entry into output file
void logEntry(std::ofstream&, CacheResponse*);
public:
CacheController(CacheInfo, std::string);
void runTracefile();
};
11. #endif //CACHECONTROLLER
finalprojtemplatev5/finalprojtemplate/src/CacheSimulator.cppfi
nalprojtemplatev5/finalprojtemplate/src/CacheSimulator.cpp/*
Cache Simulator (Starter Code) by Justin Goins
Oregon State University
Spring Term 2021
*/
#include"CacheSimulator.h"
#include"CacheStuff.h"
#include"CacheController.h"
#include<iostream>
#include<fstream>
#include<thread>
usingnamespace std;
/*
This function creates the cache and starts the simulator.
Accepts core ID number, configuration info, and the name of
the tracefile to read.
*/
void initializeCache(int id,CacheInfo config, string tracefile){
CacheController singlecore =CacheController(config, tracefile);
singlecore.runTracefile();
}
/*
This function accepts a configuration file and a trace file on t
he command line.
12. The code then initializes a cache simulator and reads the requ
ested trace file(s).
*/
int main(int argc,char* argv[]){
CacheInfo config;
if(argc <3){
cerr <<"You need two command line arguments. You shoul
d provide a configuration file and a trace file."<< endl;
return1;
}
// determine how many cache levels the system is using
unsignedint numCacheLevels;
// read the configuration file
cout <<"Reading config file: "<< argv[1]<< endl;
ifstream infile(argv[1]);
unsignedint tmp;
infile >> numCacheLevels;
infile >> config.memoryAccessCycles;
infile >> config.numberSets;
infile >> config.blockSize;
infile >> config.associativity;
infile >> tmp;
config.rp =static_cast<ReplacementPolicy>(tmp);
infile >> tmp;
config.wp =static_cast<WritePolicy>(tmp);
infile >> config.cacheAccessCycles;
infile.close();
// Examples of how you can access the configuration file inform
ation
cout <<"System has "<< numCacheLevels <<" cache(s)."<< e
ndl;
cout << config.numberSets <<" sets with "<< config.blockSiz
e <<" bytes in each block. N = "<< config.associativity << endl;
13. if(config.rp ==ReplacementPolicy::Random)
cout <<"Using random replacement protocol"<< endl;
else
cout <<"Using LRU protocol"<< endl;
if(config.wp ==WritePolicy::WriteThrough)
cout <<"Using write-through policy"<< endl;
else
cout <<"Using write-back policy"<< endl;
// start the cache operation...
string tracefile(argv[2]);
initializeCache(0, config, tracefile);
return0;
}
finalprojtemplatev5/finalprojtemplate/src/CacheSimulator.h
/*
Cache Simulator (Starter Code) by Justin Goins
Oregon State University
Spring Term 2021
*/
#ifndef _CACHESIMULATOR_H_
#define _CACHESIMULATOR_H_
15. WriteThrough,
WriteBack
};
// structure to hold information about a particular cache
struct CacheInfo {
unsigned int numByteOffsetBits;
unsigned int numSetIndexBits;
unsigned int numberSets; // how many sets are in the cache
unsigned int blockSize; // size of each block in bytes
unsigned int associativity; // the level of associativity (N)
ReplacementPolicy rp;
WritePolicy wp;
unsigned int cacheAccessCycles;
unsigned int memoryAccessCycles;
};
// this structure can filled with information about each memory
16. operation
struct CacheResponse {
int hits; // how many caches did this memory operation
hit?
int misses; // how many caches did this memory operation
miss?
int evictions; // did this memory operation involve one or
more evictions?
int dirtyEvictions; // were any evicted blocks marked as
dirty? (relevant for write-back cache)
unsigned int cycles; // how many clock cycles did this
operation take?
};
#endif //CACHESTUFF
For a long time, implementation of social welfare policy was
considered a rather mechanistic and apolitical activity. Early
theories and models of decision-making and policy formulation
were straightforward and top-down: Administrators were
expected to carry out the policies as formulated by political or
other types of leaders. The underlying paradigms were often
adopted without reflection. However, more recently the causal
relationship between paradigms and changes caused by policy
implementation has led to a range of outcomes, such as the
17. following:
· Reformulation of policies
· Adoption of conflicting paradigms
· Unexpected outcomes
· Outright failure
One clear lesson to be learned is that if policy objectives
informed by social welfare paradigms are too ambiguous, street-
level bureaucrats will be given room for adaptation of
objectives to suit their clients’ or their own preferences.
Nowadays, scholars are aware of the fact that implementation is
not an easy task. For one, it has no clear starting point and no
clear ending. Actors at multiple levels have their own needs,
interests, and resources to exert influence on the
implementation of social policy. As a result, we see social
policy migrating toward implementation from the federal to
local level and, through the organization of advocacy groups,
from the local level to the federal level.
Prior to developing your discussion analysis and the associated
paradigms, theories, and ideologies, review your textbook and
required reading materials. Pay particular attention to Chapter
Three’s exploration of the following foundational paradigms of
the social welfare system:
· Social constructivism
· Critical analysis
· Models of justice
· Strengths based model
· Social empathy
First, using a minimum of two Scholarly, Peer Reviewed, and
Other Credible Sources (Links to an external site.), research one
of the areas of interest below. It is suggested that you begin
your research in the Ashford University Library using
[email protected] for initial searches. For additional information
on legislative history, use the Westlaw database via the Journal
Articles button in the Ashford University Library homepage.
Utilize the paradigms, theories, and ideologies found in your
text to understand your state’s and local community’s positions
18. and responses. Support your position with information from
another credible source other than the text. This could include
websites of organizations, including social media, that support
your state or community. However, be sure to identify the
paradigm underlying that organization’s approach to a social
issue.
Some suggested topics are noted below. Other topics are
possible with instructor approval:
· Family violence: The Family Violence Prevention and
Services Act (FVPSA), first authorized in 1984, is the only
federal funding source dedicated directly to domestic violence
shelters and programs. After FVPSA expired in 2008, the
National Network to End Domestic Violence (NNEDV) led the
effort with domestic violence advocates to reauthorize this vital
legislation. On November 10, 2010, Congress passed a bill to
reauthorize FVPSA as part of the Child Abuse Prevention and
Treatment Act (CAPTA) reauthorization through fiscal year
2015. The bill was signed into law by the President on
December 20, 2010. How has your state and local municipality
responded to these national agendas?
· Same sex couples: The U.S. Supreme Court has ruled that
states cannot ban same-sex marriage, thereby requiring all states
to issue marriage licenses to same-sex couples. How is your
state and local community responding to this change? Is it
considered a moral or human rights issue?
· Immigration reform: A deadlocked Supreme Court has
effectively squashed any chance of significant immigration
reform before President Obama leaves office in January. On
June 23, a 4–4 vote by the justices left in place an injunction
blocking Obama’s plan to shield from deportation millions of
undocumented immigrants whose children are U.S. citizens or
legal residents. The plan would also have allowed those
immigrants to apply for work permits. Given these changes led
by Supreme Court rulings, how is your state responding to the
immigration issue.
Next, find a federal social welfare program meant to address
19. your chosen issue. Consider what paradigms are employed by
the program to your chosen topic. In your initial post of 300
words, briefly describe a federal social welfare program meant
to address one particular issue. Address the following in your
initial post:
· What paradigm is assumed or debated in regard to your chosen
program?
· What systems of ideas (theories) to approaching your chosen
social issue are influenced the paradigm you have identified?
· How do those theories then result in a federal approach to the
issue of your choosing ideologies?
Be sure the influence of federal positions in the development of
a local response is the major focus of your initial post. (Your
discussion post can use the following structures: Federal
Program Paradigm Theory Ideology, Local Ideology, and state
how they are linked to a state or local community program).
Guided Response: Please provide substantive and thoughtful
replies of at least 150 words each, responding to at least two
peers. In your replies, ask specific questions of your colleagues
about their reflections to encourage further conversation. In
replies, you might discuss how they responded in similar
fashion or dissimilar ways to your own.
· Using your peer’s analysis and paradigm, how does it compare
to your state or local community in terms of the paradigm it
uses?
· Make at least one suggestion that enhances your classmate’s
analysis. Support your rationale.
· Please be sure to respond to all those who would respond to
your original post or your own responses to peers to develop a
true dialogue
Sample Testing/multi_sample1_config
2
230
20. 8
16
3
1
0
13
8
32
3
1
0
40
Sample Testing/multi_sample1_trace
==multi_sample1_config has an L1 with 16 bytes (13 cycles),
L2 with 32 bytes (40 cycles), RAM is 230 cycles
L 0,4
L 80,8
L 10,4
L 102,6
L 2,6
==The following store involves a "fetch on write" operation
because we had to fetch the original block first
S 180,5
L 100,2
==Note that the following load is spread across two blocks:
L 4,20
L 100,2
L 80,8
M 180,6
L 100,8
S 100,5
S 180,8
L 80,8
M 0,8
21. M 0,4
L 280,4
M 80,8
Sample Testing/multi_sample1_trace.zip
multi_sample1_trace.outL 04 286 L1 miss L2 missL 808 286 L1
miss L2 missL 104 53 L1 miss L2 hitL 1026 286 L1 miss L2
missL 26 13 L1 hitS 1805 572 L1 miss eviction L2 miss hitL
1002 13 L1 hitL 420 26 L1 hitL 1002 13 L1 hitL 808 53 L1
miss eviction L2 hitM 1806 53 L1 miss eviction L2 hitM 1806
286 L1 hit L2 hitL 1008 13 L1 hitS 1005 286 L1 hit L2 hitS
1808 286 L1 hit L2 hitL 808 13 L1 hitM 08 53 L1 miss eviction
L2 hitM 08 286 L1 hit L2 hitM 04 13 L1 hitM 04 286 L1 hit L2
hitL 2804 286 L1 miss eviction L2 missM 808 13 L1 hitM 808
286 L1 hit L2 hitL1 Cache: Hits:15 Misses:9 Evictions:5L2
Cache: Hits:11 Misses:5 Evictions:0Cycles:3761 Reads:16
Writes:7
Sample Testing/multi_sample2_config
3
230
8
16
3
1
0
13
8
32
2
1
0
40
32
22. 32
3
1
0
110
Sample Testing/multi_sample2_trace
== multi_sample2_configuration
== L1: 16 bytes/block, 8 sets, associativity N=3, LRU, 13
cycles
== L2: 32 bytes/block, 8 sets, associativity N=2, LRU, 40
cycles
== L3: 32 bytes/block, 32 sets, associativity N=3, LRU, 110
cycles
== RAM: 230 cycles
L 474,1
L 460,8
S 47c,16
M 7,8
L c7e,2
== this store will hit L2 while fetching:
S c68,8
L 864,10
L 460,8
== the following load is more complex due to multiple cache
impacts...
L 60,4
Sample Testing/multi_sample2_trace.zip
multi_sample2_trace.out
L 474,1 396 L1 miss L2 miss L3 miss
L 460,8 53 L1 miss L2 hit
S 47c,16 959 L1 miss hit L2 miss hit L3 miss hit
M 7,8 396 L1 miss L2 miss L3 miss
23. M 7,8 396 L1 hit L2 hit L3 hit
L c7e,2 396 L1 miss L2 miss L3 miss
S c68,8 449 L1 miss L2 hit L3 hit
L 864,10 396 L1 miss L2 miss eviction L3 miss
L 460,8 13 L1 hit
L 60,4 396 L1 miss eviction L2 miss eviction L3 miss eviction
L1 Cache: Hits:3 Misses:8 Evictions:1
L2 Cache: Hits:6 Misses:6 Evictions:2
L3 Cache: Hits:4 Misses:6 Evictions:1
Cycles:3850 Reads:7 Writes:3
Sample Testing/sample1_config
1
230
8
8
3
1
0
13
Sample Testing/sample1_trace
==Note that sample1_config is designed to hold only 8 bytes
per block
L 0,4
L 80,8
L 10,4
L 102,6
L 2,6
==The following store involves a "fetch on write" operation
because we had to fetch the original block first
S 180,5
L 100,2
==Note that the following load is spread across three blocks
24. == (see next command)
==Blocks 0 and 2 are still in the cache, but block 1 has never
been loaded
==Technically this causes an L1 "hit miss hit" but it is fine if
your output file just indicates
==that there was at least one hit and miss ("L1 miss hit" or "L1
hit miss"). The ordering does not matter as long as
==you correctly indicate their presence.
==The important thing is that ALL block hits and misses are
reflected in the statistics that are printed at the
==very end of the output file.
L 4,20
L 100,2
L 80,8
M 180,6
L 100,8
S 100,5
S 180,8
L 80,8
M 0,8
M 0,4
L 280,4
M 80,8
Sample Testing/sample1_trace.zip
sample1_trace.outL 04 243 L1 missL 808 243 L1 missL 104 243
L1 missL 1026 243 L1 missL 26 13 L1 hitS 1805 486 L1 miss
evictionL 1002 13 L1 hitL 420 269 L1 miss hitL 1002 13 L1
hitL 808 243 L1 miss evictionM 1806 243 L1 miss evictionM
1806 243 L1 hitL 1008 13 L1 hitS 1005 243 L1 hitS 1808 243
L1 hitL 808 13 L1 hitM 08 243 L1 miss evictionM 08 243 L1
hitM 04 13 L1 hitM 04 243 L1 hitL 2804 243 L1 miss evictionM
808 13 L1 hitM 808 243 L1 hitL1 Cache: Hits:15 Misses:10
Evictions:5Cycles:4248 Reads:16 Writes:7
25. Sample Testing/sample2_config
1
230
8
32
3
1
0
13
Sample Testing/sample2_trace==Note that sample2_config is
designed to hold 32 bytes per block==This has several effects
one of which is that the RAM requires (230+1+1+1) cycles to
fetch a 32 byte block.==Another side effect is that the blocks do
not all fall into the same index (hence the lack of evictions). L
04 L 808 L 104 L 1026 L 26 S 1805 L 1002 L 420 L 1002 L 808
M 1806 L 1008 S 1005 S 1808 L 808 M 08 M 04 L 2804 M 808
Sample Testing/sample2_trace.zip
sample2_trace.outL 04 246 L1 missL 808 246 L1 missL 104 13
L1 hitL 1026 246 L1 missL 26 13 L1 hitS 1805 492 L1 missL
1002 13 L1 hitL 420 13 L1 hitL 1002 13 L1 hitL 808 13 L1
hitM 1806 13 L1 hitM 1806 246 L1 hitL 1008 13 L1 hitS 1005
246 L1 hitS 1808 246 L1 hitL 808 13 L1 hitM 08 13 L1 hitM 08
246 L1 hitM 04 13 L1 hitM 04 246 L1 hitL 2804 246 L1 missM
808 13 L1 hitM 808 246 L1 hitL1 Cache: Hits:18 Misses:5
Evictions:0Cycles:3108 Reads:16 Writes:7
Sample Testing/sample3_config
1
230
8
32
26. 3
1
0
13
Sample Testing/sample3_trace
== Note that sample3_config is designed to hold 32 bytes per
block
== Demonstrate the RAM buffering behavior
L 0,4
L 1f,1
L 20,1
Sample Testing/sample3_trace.zip
sample3_trace.out
L 0,4 246 L1 miss
L 1f,1 13 L1 hit
L 20,1 17 L1 miss
L1 Cache: Hits:1 Misses:2 Evictions:0
Cycles:276 Reads:3 Writes:0
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Final Project
Due Jun 10 by 11:59pm Points 200 Submitting a file upload
File Types pdf and tar Available after May 13 at 12am
27. Start Assignment
ECE/CS 472/572 Final Exam Project
Submit your final project to Canvas by Thursday June 10th, at
11:59pm
Late submissions will be penalized 15 points per day.
Remember to check the errata section (at the very bottom of the
page) for updates.
Your submission should be comprised of two items: a .pdf file
containing your written report and
a .tar file containing a directory structure with your C or C++
source code. Your grade will be reduced
if you do not follow the submission instructions.
All written reports (for both 472 and 572 students) must be
composed in MS Word, LaTeX, or some
other word processor and submitted as a PDF file.
Please take the time to read this entire document. If you have
questions there is a high likelihood that
another section of the document provides answers.
Introduction
In this final project you will implement a cache simulator. Your
simulator will be configurable and will
be able to handle caches with varying capacities, block sizes,
levels of associativity, replacement
policies, and write policies. The simulator will operate on trace
files that indicate memory access
properties. All input files to your simulator will follow a
specific structure so that you can parse the
contents and use the information to set the properties of your
simulator.
28. After execution is finished, your simulator will generate an
output file containing information on the
number of cache misses, hits, and miss evictions (i.e. the
number of block replacements). In addition,
the file will also record the total number of (simulated) clock
cycles used during the situation. Lastly,
the file will indicate how many read and write operations were
requested by the CPU.
It is important to note that your simulator is required to make
several significant assumptions for the
sake of simplicity.
1. You do not have to simulate the actual data contents. We
simply pretend that we copied data from
main memory and keep track of the hypothetical time that would
have elapsed.
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2. Accessing a sub-portion of a cache block takes the exact
same time as it would require to access
the entire block. Imagine that you are working with a cache that
uses a 32 byte block size and has
an access time of 15 clock cycles. Reading a 32 byte block from
this cache will require 15 clock
cycles. However, the same amount of time is required to read 1
byte from the cache.
29. 3. In this project assume that main memory RAM is always
accessed in units of 8 bytes (i.e. 64 bits
at a time).
When accessing main memory, it's expensive to access the first
unit. However, DDR memory
typically includes buffering which means that the RAM can
provide access to the successive
memory (in 8 byte chunks) with minimal overhead. In this
project we assume an overhead of 1
additional clock cycle per contiguous unit.
For example, suppose that it costs 255 clock cycles to access
the first unit from main memory.
Based on our assumption, it would only cost 257 clock cycles to
access 24 bytes of memory.
4. Assume that all caches utilize a "fetch-on-write" scheme if a
miss occurs on a Store operation.
This means that you must always fetch a block (i.e. load it)
before you can store to that location (if
that block is not already in the cache).
Additional Resources
Sample trace files
Students are required to simulate the instructor-provided trace
files (although you are welcome to
simulate your own files in addition).
Trace files are available on Flip in the following directory:
/nfs/farm/classes/eecs/spring2021/cs472/public/tracefiles
You should test your code with all three tracefiles in that
directory (gcc, netpath, and openssl).
Starter Code
In order to help you focus on the implementation of the cache
30. simulator, starter code is provided
(written in C++) to parse the input files and handle some of the
file I/O involved in this assignment.
You are not required to use the supplied code (it's up to you).
Note that you will need to adapt this
code to work with your particular design.
The starter code is available here:
https://classes.engr.oregonstate.edu/eecs/spring2021/cs472/fi nal
projtemplatev5.zip
(https://classes.engr.oregonstate.edu/eecs/spring2021/cs472/fina
lprojtemplatev5.zip)
Basic-Mode Usage (472 & 572 students)
L1 Cache Simulator
All students are expected to implement the L1 cache simulator.
Students who are enrolled in 472 can
ignore the sections that are written in brown text. Graduate
students will be simulating a multiple-level
cache (an L1 cache, an L2 cache, and even an L3 cache).
https://classes.engr.oregonstate.edu/eecs/spring2021/cs472/final
projtemplatev5.zip
2021/6/2 Final Project
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Input Information
Your cache simulator will accept two arguments on the
command line: the file path of a configuration
file and the file path of a trace file containing a sequence of
31. memory operations. The cache simulator
will generate an output file containing the simulation results.
The output filename will have “.out”
appended to the input filename. Additional details are provided
below.
# example invocation of cache simulator
cache_sim ./resources/testconfig ./resources/simpletracefile
Output file written to ./resources/simpletracefile.out
The first command line argument will be the path to the
configuration file. This file contains
information about the cache design. The file will contain only
numeric values, each of which is on a
separate line.
Example contents of a configuration file:
1 <-- this line will always contain a "1" for 472 students
230 <-- number of cycles required to write or read a unit from
main memory
8 <-- number of sets in cache (will be a non-negative power of
2)
16 <-- block size in bytes (will be a non-negative power of 2)
3 <-- level of associativity (number of blocks per set)
1 <-- replacement policy (will be 0 for random replacement, 1
for LRU)
1 <-- write policy (will be 0 for write-through, 1 for write-back)
13 <-- number of cycles required to read or write a block from
the cache (consider this to be the
access time per block)
Here is another example configuration file specifying a direct-
mapped cache with 64 entries, a 32
byte block size, associativity level of 1 (direct-mapped), least
recently used (LRU) replacement policy,
32. write-through operation, 26 cycles to read or write data to the
cache, and 1402 cycles to read or write
data to the main memory. CS/ECE472 projects can safely ignore
the first line.
1
1402
64
32
1
1
0
26
The second command line argument indicates the path to a trace
file. This trace file will follow the
format used by Valgrind (a memory debugging tool). The file
consists of comments and memory
access information. Any line beginning with the ‘=’ character
should be treated as a comment and
ignored.
==This is a comment and can safely be ignored.
==An example snippet of a Valgrind trace file
I 04010173,3
I 04010176,6
S 04222cac,1
I 0401017c,7
L 04222caf,8
I 04010186,6
I 040101fd,7
L 1ffefffd78,8
M 04222ca8,4
I 04010204,4
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Memory access entries will use the following format in the trace
file:
[space]operation address,size
Lines beginning with an ‘I’ character represent an instruction
load. For this assignment, you can
ignore instruction read requests and assume that they are
handled by a separate instruction
cache.
Lines with a space followed by an ‘S’ indicate a data store
operation. This means that data needs
to be written from the CPU into the cache or main memory
(possibly both) depending on the write
policy.
Lines with a space followed by an ‘L’ indicate a data load
operation. Data is loaded from the cache
into the CPU.
Lines with a space followed by an ‘M’ indicate a data modify
operation (which implies a special
case of a data load, followed immediately by a data store).
The address is a 64 bit hexadecimal number representing the
address of the first byte that is being
requested. Note that leading 0's are not necessarily shown in the
file. The size of the memory
operation is indicated in bytes (as a decimal number).
34. If you are curious about the trace file, you may generate your
own trace file by running Valgrind on
arbitrary executable files:
valgrind --log-fd=1 --log-file=./tracefile.txt --tool=lackey --
trace-mem=yes name_of_executable_t
o_trace
Cache Simulator Output
Your simulator will write output to a text file. The output
filename will be derived from the trace
filename with “.out” appended to the original filename. E.g. if
your program was called using the
invocation “cache_sim ./dm_config ./memtrace” then the output
file would be written to
“./memtrace.out”
(S)tore, (L)oad, and (M)odify operations will each be printed to
the output file (in the exact order that
they were read from the Valgrind trace file). Lines beginning
with “I” should not appear in the output
since they do not affect the operation of your simulator.
Each line will have a copy of the original trace file instruction.
There will then be a space, followed by
the number of cycles used to complete the operation. Lastly,
each line will have one or more
statements indicating the impact on the cache. This could be one
or more of the following: miss, hit,
or eviction.
Note that an eviction is what happens when a cache block needs
to be removed in order to make
space in the cache for another block. It is simply a way of
indicating that a block was replaced. In our
simulation, an eviction means that the next instruction cannot
35. be executed until after the existing
cache block is written to main memory. An eviction is an
expensive cache operation.
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It is possible that a single memory access has multiple impacts
on the cache. For example, if a
particular cache index is already full, a (M)odify operation
might miss the cache, evict an existing
block, and then hit the cache when the result is written to the
cache.
The general format of each output line (for 472 students) is as
follows (and will contain one or more
cache impacts):
operation address,size <number_of_cycles> L1
<cache_impact1> <cache_impact2> <...>
The final lines of the output file are special. They will indicate
the total number of hits, misses, and
evictions. The last line will indicate the total number of
simulated cycles that were necessary to
simulate the trace file, as well as the total number of read and
write operations that were directly
requested by the CPU.
These lines should exactly match the following format (with
values given in decimal):
36. L1 Cache: Hits:<hits> Misses:<misses> Evictions:<evictions>
Cycles:<number of total simulated cycles> Reads:<# of CPU
read requests> Writes:<# of CPU write r
equests>
In order to illustrate the output file format let’s look at an
example. Suppose we are simulating a
direct-mapped cache operating in write-through mode. Note that
the replacement policy does not
have any effect on the operation of a direct-mapped cache.
Assume that the configuration file told us
that it takes 13 cycles to access the cache and 230 cycles to
access main memory. Keep in mind that
a hit during a load operation only accesses the cache while a
miss must access both the cache and
the main memory. For this scenario, assume that memory access
is aligned to a single block and
does not straddle multiple cache blocks.
In this example the cache is operating in write-through mode so
a standalone (S)tore operation takes
243 cycles, even if it is a hit, because we always write the block
into both the cache and into main
memory. If this particular cache was operating in write-back
mode, a (S)tore operation would take
only 13 cycles if it was a hit (since the block would not be
written into main memory until it was
evicted).
The exact details of whether an access is a hit or a miss is
entirely dependent on the specific cache
design (block size, level of associativity, number of sets, etc).
Your program will implement the code
to see if each access is a hit, miss, eviction, or some
combination.
37. Since the (M)odify operation involves a Load operation
(immediately followed by a Store operation), it
is recorded twice in the output file. The first instance represents
the load operation and the next line
will represent the store operation. See the example below...
==For this example we assume that addresses 04222cac,
04222caf, and 04222ca8 are all in the same
block at index 2
==Assume that addresses 047ef249 and 047ef24d share a block
that also falls at index 2.
==Since the cache is direct-mapped, only one of those blocks
can be in the cache at a time.
==Fortunately, address 1ffefffd78 happens to fall in a different
block index (in our hypothetical
example).
==Side note: For this example a store takes 243 cycles (even if
it was a hit) because of the writ
e-through behavior.
==The output file for our hypothetical example:
S 04222cac,1 486 L1 miss <-- (243 cycles to fetch the block and
write it to L1) + (243 cycles to
update the cache & main memory)
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L 04222caf,8 13 L1 hit
M 1ffefffd78,8 243 L1 miss <-- notice that this (M)odify has a
38. miss for the load and a hit for th
e store
M 1ffefffd78,8 243 L1 hit <-- this line represents the Store of
the modify operation
M 04222ca8,4 13 L1 hit <-- notice that this (M)odify has two
hits (one for the load, one for the
store)
M 04222ca8,4 243 L1 hit <-- this line represents the Store of
the modify operation
S 047ef249,4 486 L1 miss eviction <-- 486 cycles for miss, no
eviction penalty for write-through
cache
L 04222caf,8 243 L1 miss eviction
M 047ef24d,2 243 L1 miss eviction <-- notice that this (M)odify
initially misses, evicts the bloc
k, and then hits
M 047ef24d,2 243 L1 hit <-- this line represents the Store of the
modify operation
L 1ffefffd78,8 13 L1 hit
M 047ef249,4 13 L1 hit
M 047ef249,4 243 L1 hit
L1 Cache: Hits:8 Misses:5 Evictions:3
Cycles:2725 Reads:7 Writes:6 <-- total sum of simulated cycles
(from above), as well as the numbe
r of reads and writes that were requested by the CPU
NOTE: The example above is assuming that the cache has a
block size of at least 8 bytes. Simulating
a cache with a smaller blocksize would affect the timing and
could also lead to multiple evictions in a
single cache access. For example, if the blocksize was only 4
bytes it's possible that an 8 byte load
might evict 3 different blocks. This happens because the data
might straddle two or more blocks
(depending on the starting memory address).
39. Sample Testing Information
Some students have asked for additional test files with "known"
results that they can compare
against. I've created my own implementation of the cache
simulator and provided students with the
following files (and results).
Note: These files are not an exhaustive representation of the
testing that your cache will undergo. It is
your job to independently test your code and verify proper
behavior.
Sample 1
sample1_config
(https://canvas.oregonstate.edu/courses/1808623/files/87822466
/download?
download_frd=1)
sample1_trace
(https://canvas.oregonstate.edu/courses/1808623/files/87822454
/download?
download_frd=1)
sample1_trace.out
(https://canvas.oregonstate.edu/courses/1808623/files/87822458
/download?download_frd=1)
Sample 2
sample2_config
(https://canvas.oregonstate.edu/courses/1808623/files/87822460
/download?
download_frd=1)
sample2_trace
(https://canvas.oregonstate.edu/courses/1808623/files/87822462
/download?
download_frd=1)
sample2_trace.out
(https://canvas.oregonstate.edu/courses/1808623/files/87822464
/download?download_frd=1)
40. Facts and Questions (FAQ):
Your "random" cache replacement algorithm needs to be
properly seeded so that multiple runs of
the same tracefile will generate different results.
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41. https://canvas.oregonstate.edu/courses/1808623/assignments/84
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I will never test your simulator using a block size that is smaller
than 8 bytes.
During testing, the cache will not contain more than 512
indexes.
For our purposes the level of associativity could be as small as
N=1 (direct mapped) or as large
as N=64.
The last line of your output will indicate the total number of
simulated cycles that were necessary
to simulate the trace file, as well as the total number of read and
write operations that were
directly requested by the CPU. In other words, this is asking
how many loads and stores the CPU
directly requested (remember that a Modify operation counts as
both a Load and a Store).
572 students: For our purposes an L2 cache will always have a
block size that is greater than or
equal to the L1 block size. The L3 block size will be greater
than or equal to the L2 block size.
Implementation Details
You may use either the C or the C++ programming language.
Graduate students will have an
additional component to this project.
In our simplified simulator, increasing the level of associativity
has no impact on the cache access
time. Furthermore, you may assume that it does not take any
additional clock cycles to access non-
data bits such as Valid bits, Tags, Dirty Bits, LRU counters, etc.
Your code must support the LRU replacement scheme and the
random replacement scheme. For the
42. LRU behavior, a block is considered to be the Least Recently
Used if every other block in the cache
has been read or written after the block in question. In other
words, your simulator must implement a
true LRU scheme, not an approximation.
You must implement the write-through cache mode. You will
receive extra credit if your code correctly
supports the write-back cache mode (specified in the
configuration file).
Acceptable Compiler Versions
The flip server provides GCC 4.8.5 for compiling your work.
Unfortunately, this version is from 2015
and may not support newer C and C++ features. If you call the
program using “gcc” (or “g++”) this is
the version you will be using by default.
If you wish to use a newer compiler version, I have compiled a
copy of GCC 10.3 (released April 8,
2021). You may write your code using this compiler and you’re
allowed to use any of the compiler
features that are available. The compiler binaries are available
in the path:
/nfs/farm/classes/eecs/spring2021/cs472/public/gcc/bin
For example, in order to compile a C++ program with GCC
10.3, you could use the following
command (on a single terminal line):
/nfs/farm/classes/eecs/spring2021/cs472/public/gcc/bin/g++ -
ocache_sim -Wl,-rpath,/nfs/farm/class
es/eecs/spring2021/cs472/public/gcc/lib64 my_source_code.cpp
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If you use the Makefile that is provided in the starter code, it is
already configured to use GCC 10.3.
L2/L3 Cache Implementation (required for CS/ECE 572
students)
Implement your cache simulator so that it can support up to 3
layers of cache. You can imagine that
these caches are connected in a sequence. The CPU will first
request information from the L1 cache.
If the data is not available, the request will be forwarded to the
L2 cache. If the L2 cache cannot fulfill
the request, it will be passed to the L3 cache. If the L3 cache
cannot fulfill the request, it will be
fulfilled by main memory.
It is important that the properties of each cache are read from
the provided configuration file. As an
example, it is possible to have a direct-mapped L1 cache that
operates in cohort with an associative
L2 cache. All of these details will be read from the
configuration file. As with any programming project,
you should be sure to test your code across a wide variety of
scenarios to minimize the probability of
an undiscovered bug.
Cache Operation
When multiple layers of cache are implemented, the L1 cache
44. will no longer directly access main
memory. Instead, the L1 cache will interact with the L2 cache.
During the design process, you need to
consider the various interactions that can occur. For example, if
you are working with three write-
through caches, than a single write request from the CPU will
update the contents of L1, L2, L3, and
main memory!
++++++++++++ ++++++++++++ ++++++++++++
++++++++++++ +++++++++++++++
| | | | | | | | | |
| CPU | <----> | L1 Cache | <----> | L2 Cache | <----> | L3
Cache | <----> | Main Memory |
| | | | | | | | | |
++++++++++++ ++++++++++++ ++++++++++++
++++++++++++ +++++++++++++++
Note that your program should still handle a configuration file
that specifies an L1 cache (without any
L2 or L3 present). In other words, you can think of your project
as a more advanced version of the
472 implementation.
572 Extra Credit
By default, your code is only expected to function with write-
through caches. If you want to earn extra
credit, also implement support for write-back caches.
In this situation, you will need to track dirty cache blocks and
properly handle the consequences of
evictions. You will earn extra credit if your write-back design
works with simple L1 implementations.
You will receive additional extra credit if your code correctly
handles multiple layers of write-back
caches (e.g. the L1 and L2 caches are write-back, but L3 is
write-through) .
45. Simulator Operation
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Your cache simulator will use a similar implementation as the
single-level version but will parse the
configuration file to determine if multiple caches are present.
Input Information
The input configuration file is as shown below. Note that it is
backwards compatible with the 472
format.
The exact length of the input configuration file will depend on
the number of caches that are specified.
3 <-- this line indicates the number of caches in the simulation
(this can be set to a maximum of
3)
230 <-- number of cycles required to write or read a block from
main memory
8 <-- number of sets in L1 cache (will be a non-negative power
of 2)
16 <-- L1 block size in bytes (will be a non-negative power of
2)
4 <-- L1 level of associativity (number of blocks per set)
1 <-- L1 replacement policy (will be 0 for random replacement,
1 for LRU)
46. 1 <-- L1 write policy (will be 0 for write-through, 1 for write-
back)
13 <-- number of cycles required to read or write a block from
the L1 cache (consider this to be
the access time)
8 <-- number of sets in L2 cache (will be a non-negative power
of 2)
32 <-- L2 block size in bytes (will be a non-negative power of
2)
4 <-- L2 level of associativity (number of blocks per set)
1 <-- L2 replacement policy (will be 0 for random replacement,
1 for LRU)
1 <-- L2 write policy (will be 0 for write-through, 1 for write-
back)
40 <-- number of cycles required to read or write a block from
the L2 cache (consider this to be
the access time)
64 <-- number of sets in L3 cache (will be a non-negative power
of 2)
32 <-- L3 block size in bytes (will be a non-negative power of
2)
8 <-- L3 level of associativity (number of blocks per set)
0 <-- L3 replacement policy (will be 0 for random replacement,
1 for LRU)
0 <-- L3 write policy (will be 0 for write-through, 1 for write-
back)
110 <-- number of cycles required to read or write a block from
the L3 cache (consider this to be
the access time)
Cache Simulator Output
The output file will contain nearly the same information as in
the single-level version (see the general
description provided in the black text). However, the format is
expanded to contain information about
47. each level of the cache.
The general format of each output line is as follows (and can
list up to 2 cache impacts for each level
of the cache):
operation address,size <total number_of_cycles> L1
<cache_impact1> <cache_impact2> <...> L2 <cach
e_impact1> <cache_impact2> <...> L3 <cache_impact1>
<cache_impact2> <...>
The exact length of each line will vary, depending how many
caches are in the simulation (as well as
their interaction). For example, imagine a system that utilizes
an L1 and L2 cache.
If the L1 cache misses and the L2 cache hits, we might see
something such as the following:
L 04222caf,8 53 L1 miss L2 hit
In this scenario, if the L1 cache hits, then the L2 cache will not
be accessed and does not appear in
the output.
L 04222caf,8 13 L1 hit
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Suppose L1, L2, and L3 all miss (implying that we had to access
48. main memory):
L 04222caf,8 393 L1 miss L2 miss L3 miss
(M)odify operations are the most complex since they involve
two sub-operations... a (L)oad
immediately followed by a (S)tore.
M 1ffefffd78,8 163 L1 miss eviction L2 miss L3 hit <-- notice
that the Load portion of this (M)od
ify operation caused an L1 miss, L2 miss, and L3 hit
M 1ffefffd78,8 13 L1 hit <-- this line belongs to the store
portion of the (M)odify operation
The final lines of the output file are special. They will indicate
the total number of hits, misses, and
evictions for each specific cache. The very last line will
indicate the total number of simulated cycles
that were necessary to simulate the trace file, as well as the
total number of read and write operations
that were directly requested by the CPU.
These lines should exactly match the following format (with
values given in decimal):
L1 Cache: Hits:<hits> Misses:<misses> Evictions:<evictions>
L2 Cache: Hits:<hits> Misses:<misses> Evictions:<evictions>
L3 Cache: Hits:<hits> Misses:<misses> Evictions:<evictions>
Cycles:<number of total simulated cycles> Reads:<# of CPU
read requests> Writes:<# of CPU write r
equests>
Project Write-Up
Note: Any chart or graphs in your written report must have
labels for both the vertical and horizontal
axis.
49. Undergraduates (CS/ECE 472)
Part 1: Summarize your work in a well-written report. The
report should be formatted in a professional
format. Use images, charts, diagrams or other visual techniques
to help convey your information to
the reader.
Explain how you implemented your cache simulator. You should
provide enough information that a
knowledgeable programmer would be able to draw a reasonably
accurate block diagram of your
program.
What data structures did you use to implement your design?
What were the primary challenges that you encountered while
working on the project?
Is there anything you would implement differently if you were
to re-implement this project?
How do you track the number of clock cycles needed to execute
memory access instructions?
Part 2: There is a general rule of thumb that a direct-mapped
cache of size N has about the same
miss rate as a 2-way set associative cache of size N/2.
Your task is to use your cache simulator to conclude whether
this rule of thumb is actually worth
using. You may test your simulator using instructor-provided
trace files (see the sample trace files
section) or you may generate your own trace files from Linux
executables (“wget oregonstate.edu”,
“ls”, “hostid”, “cat /etc/motd”, etc). Simulate at least three trace
files and compare the miss rates for a
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direct-mapped cache versus a 2-way set associative cache of
size N/2. For these cache simulations,
choose a block size and number of indices so that the direct-
mapped cache contains 64KiB of data.
The 2-way set associative cache (for comparison) should then
contain 32KiB of data. You are
welcome to experiment with different block sizes/number of
indices to see how your simulation results
are affected. You could also simulate additional cache sizes to
provide more comparison data. After
you have obtained sufficient data to support your position, put
your simulation results into a graphical
plot and explain whether you agree with the aforementioned
rule of thumb. Include this information in
your written report.
Part 3: If you chose to implement any extra credit tasks, be sure
to include a thorough description of
this work in the report.
Graduate Students (CS/ECE 572)
Part 1: Summarize your work in a well-written report. The
report should be formatted in a professional
format. Use images, charts, diagrams or other visual techniques
to help convey your information to
the reader.
Explain how you implemented your cache simulator. You should
provide enough information that a
51. knowledgeable programmer would be able to draw a reasonably
accurate block diagram of your
program.
What data structures did you use to implement your multi-level
cache simulator?
What were the primary challenges that you encountered while
working on the project?
Is there anything you would implement differently if you were
to re-implement this project?
How do you track the number of clock cycles needed to execute
memory access instructions?
Part 2: Using trace files provided by the instructor (see the
sample trace files section), how does the
miss rate and average memory access time (in cycles) vary when
you simulate a machine with
various levels of cache? Note that you can compute the average
memory access time by considering
the total number of read and write operations (requested by the
CPU), along with the total number of
simulated cycles that it took to fulfill the requests.
Research a real-life CPU (it must contain at least an L2 cache)
and simulate the performance with L1,
L2, (and L3 caches if present). You can choose the specific
model of CPU (be sure to describe your
selection in your project documentation). This could be an Intel
CPU, an AMD processor, or some
other modern product. What is the difference in performance
when you remove all caches except the
L1 cache? Be sure to run this comparison with each of the three
instructor-provided trace files.
Provide written analysis to explain any differences in
performance. Also be sure to provide graphs or
charts to visually compare the difference in performance.
52. Part 3: If you chose to implement any extra credit tasks, be sure
to include a thorough description of
this work in the report.
Submission Guidelines
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You will submit both your source code and a PDF file
containing the typed report.
Any chart or graphs in your written report must have labels for
both the vertical and horizontal axis!
For the source code, you must organize your source code/header
files into a logical folder structure
and create a tar file that contains the directory structure. Your
code must be able to compile on
flip.engr.oregonstate.edu. If your code does not compile on the
engineering servers you should
expect to receive a 0 grade for all implementation portions of
the grade.
Your submission must include a Makefile that can be used to
compile your project from source code.
It is acceptable to adapt the example Makfile from the starter
code. If you need a refresher, please
see this helpful page
(https://www.cs.swarthmore.edu/~newhall/unixhelp/howto_mak
53. efiles.html) . If
the Makefile is written correctly, the grader should be able to
download your TAR file, extract it, and
run the “make” command to compile your program. The
resulting executable file should be named:
“cache_sim”.
Grading and Evaluation
CS/CE 472 students can complete the 572 project if they prefer
(and must complete the 572 write-up,
rather than the undergraduate version). Extra credit will be
awarded to 472 students who choose to
complete this task.
Your source code and the final project report will both be
graded. Your code will be tested for proper
functionality. All aspects of the code (cleanliness, correctness)
and report (quality of writing, clarity,
supporting evidence) will be considered in the grade. In short,
you should be submitting professional
quality work.
You will lose points if your code causes a segmentation fault or
terminates unexpectedly.
The project is worth 200 points (100 points for the written
report and 100 points for the the C/C++
implementation).
Extra Credit Explanation
The extra credit is as follows. Note that in order to earn full
extra credit, the work must be well
documented in your written report.
ECE/CS 472 Extra Credit Opportunities
54. 10 points - Implement and document write-back cache support.
30 points - Implement and document the 572 project instead of
the 472 project. All 572 expectations
must be met.
ECE/CS 572 Extra Credit Opportunities
10 points - Implement and document write-back cache support
for a system that contains only an L1
cache.
10 points (additional) - Extend your implementation so that it
works with multiple layers of write-back
caches. E.g. if a dirty L1 block is evicted, it should be written
to the L2 cache and the corresponding
https://www.cs.swarthmore.edu/~newhall/unixhelp/howto_make
files.html
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L2 block should be marked as dirty. Assuming that the L2 cache
has sufficient space, the main
memory would not be updated (yet).
Errata
This section of the assignment will be updated as changes and
clarifications are made. Each entry
here should have a date and brief description of the change so
that you can look over the errata and
easily see if any updates have been made since your last review.
55. May 13th - Released the project guidelines.
May 15th - Added note about fetch-on-write behavior for all
caches. Added link to the starter code
(written in C++).
May 16th - Refined explanation to clarify that "fetch-on-write"
only comes into play when the CPU
tries to store a block that is not currently contained in the
cache.
May 31st - Added some additional configuration files that
students can use while they are verifying
their cache behavior. Updated information regarding GCC 10.3
(dropped GCC 11.1 because Valgrind
wasn't entirely compatible). Added a "FAQ" section to clarify
other details based on student questions.
June 1st - The last line of the output file reflects the number of
Load and Store operations (with a
Modify counting as one of each) that the CPU directly
requested. For clarification, even if a Load
operation affects multiple cache blocks, it still counts as a
single CPU read request. A similar
reasoning applies to the CPU write counter.
![else
CFLAGS += -DNDEBUG -O3
endif
SRCEXT = cpp
SOURCES = $(shell find $(SRCDIR) -type f -name
*.$(SRCEXT))
OBJECTS = $(patsubst
$(SRCDIR)/%,$(BUILDDIR)/%,$(SOURCES:.$(SRCEXT)=.o))
LDFLAGS += -Wl,-
rpath,/usr/local/classes/eecs/spring2021/cs472/public/gcc/lib64
LIB += -pthread
INC += -I $(SRCDIR)
$(TARGET): $(OBJECTS)
@echo "Linking..."
@echo " $(CC) $^ -o $(TARGET) $(LIB) $(LDFLAGS)";
$(CC) $^ -o $(TARGET) $(LIB) $(LDFLAGS)
$(BUILDDIR)/%.o: $(SRCDIR)/%.$(SRCEXT)
@mkdir -p $(BUILDDIR)
@echo " $(CC) $(CFLAGS) $(INC) -c -o [email protected]
$<"; $(CC) $(CFLAGS) $(INC) -c -o [email protected] $<
clean:
@echo "Cleaning...";
@echo " $(RM) -r $(BUILDDIR) $(TARGET)"; $(RM) -r
$(BUILDDIR) $(TARGET)
.PHONY: clean
finalprojtemplatev5/finalprojtemplate/resources/simpletracefile
==This is a simple tracefile for testing purposes L 08 L 808 L
1006 L 08 S 1805 L 1002 L 808 M 1806 L 1008 S 1005 S 1808
L 808 M 08 M 04 L 2804 M 808](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)