COMPARATIVE ANALYSIS OF SWITCHING STRATEGIES FOR HARMONIC MINIMIZATION

COMPARATIVE ANALYSIS OF SWITCHING
STRATEGIES FOR HARMONIC MINIMIZATION
A PROJECT REPORT
Submitted by
ARAVIND N.KUMAR BL.EN.U4EEE13006
DIWAGAR S.V BL.EN.U4EEE13025
SANDRA JOJI BL.EN.U4EEE13055
ARUNA.T BL.EN.U4EEE13506
In the partial fulfilment for the award of the degree
Of
BACHELOR OF TECHNOLOGY
IN
ELECTRICAL AND ELECTRONICS ENGINEERING
AMRITA SCHOOL OF ENGINEERING, BENGALURU
AMRITA VISHWA VIDYAPEETHAM ,BENGALURU- 560035
MAY 2017

AMRITA VISHWA VIDYAPEETHAM
AMRITA SCHOOL OF ENGINEERING, BENGALURU- 560035
BONAFIDE CERTIFICATE
This is to certify that the Major project report entitled COMPARATIVE
ANALYSIS OF SWITCHING STRATEGIES FOR HARMONIC
MINIMIZATION IN MULTI-LEVEL INVERTER submitted by ARAVIND N
KUMAR (BL.EN.EEE13006), DIWAGAR S.V. (BL.EN.EEE13025),SANDRA
JOJI (BL.EN.EEE13055), ARUNA.T (BL.EN.U4EEE13506) in partial fulfillment
of the requirements for the award of the Degree of Bachelor of Technology in
ELECTRICALS AND ELECTRONICS ENGINEERING is a bonafide record of
the work carried out under my guidance and supervision at Amrita School of
Engineering, Bengaluru.
SUPERVISOR CHAIRMAN
Mrs Mini Sujith Dr. Ravishankar S.
Vice-Chair Professor
Department of EEE Department of EEE
This project report was evaluated by us on …………………..
EXAMINER I EXAMINER II EXAMINER II

MAY 2017
Department of EEE, ASE, Bangalore
ACKNOWLEDGEMENT
We humbly dedicate this project at the lotus feet of our beloved AMMA, Mata
Amritanandamayi Devi.
We would like to convey our thankfulness to Dr. Rakesh S. G., Associate Dean,
Amrita school of Engineering, Bengaluru.
We also take this opportunity to thank Dr. Ravishankar S. Chairman, Electrical and
Electronics Engineering Department, for his motivation and valuable help during the
project work.
We express our sincere gratitude to our guide, Mrs. Mini Sujith, Vice–Chairperson,
Department of Electrical and Electronics Engineering for her inestimable guidance,
immense and sincere help and encouragement given during the entire course of
project work.
We deeply obliged to my Professor Mrs. Lekshmi S. Project Coordinator who have
been of great help throughout this endeavor.
We express our sincere thanks to all the staff of Department of EEE and Lab
Instructors for their kind help and cooperation.
We express our special thanks to all my classmates, friends and our families who
helped a lot to complete this project successfully.
Above all, I thank Almighty for giving us the strength, courage and blessings to
complete this project.

CONTENTS MAY 2017
CONTENTS
CHAPTER TITLE PAGE NO.
ABSTRACT i
LIST OF FIGURES ii
LIST OF ABBREVIATIONS iii
LIST OF TABLES iv
1 INTRODUCTION
1.1 General Introduction 1
1.2 Advantages of MLI 2
1.3 Disadvantages of MLI 3
1.4 Applications 3
1.5 Objective of Project 4
2 LITERATURE SURVEY
2.1 Introduction 5
2.2 Literature Survey 5
2.3 Conclusion 7
3 REDUCED SWITCH TOPOLOGY
3.1 Introduction 8
3.2 Circuit Diagram 8
3.3 Working 9
3.4 Switching Sequence 9
3.5 Modes of Operation 10
3.5.1 Modes of Operation for 7-level MLI 12
3.5.2 Modes of Operation for 31-level MLI 13

CONTENTS MAY 2017
3.6 Conclusion 18
4 MODULATION METHODS
4.1 Introduction 19
4.2 Fundamental Reference Method 19
4.3 Level-Shifted PWM 20
4.3.1 Phase Disposition PWM Strategy (PD-PWM) 20
4.3.2 Phase Opposed Disposition PWM Strategy (POD-
PWM)
21
4.3.3 Alternate Phase Opposition Disposition PWM
Strategy (APOD-PWM)
22
4.4 Conclusion 22
5 SIMULATIONS AND ANALYSIS
5.1 Introduction 23
5.2 Simulation Results 23
5.3 Simulation Of 31-level Single Phase Reduced Switch
Topology
23
5.3.1 Fundamental Switching Frequency Control 24
5.3.1.1 Simulation Model 24
5.3.1.2 Inverter Output for Fundamental Reference
Method
25
5.3.1.3 FFT Analysis for Fundamental Reference Method 26
5.3.2 Level Shifted PWM 27
5.3.2.1 Phase Disposition PWM Strategy (PD-PWM) 28
5.3.2.1.1 Circuit Model 28
5.3.2.1.2 Inverter Output for PD-PWM Strategy 29
5.3.2. 5.3.2.1.3 FFT Analysis for PD-PWM Strategy 30
5 5.3.2.2 Phase Opposition Disposition PWM Strategy
( (POD-PWM)
31

CONTENTS MAY 2017
5.3.2.2.1 Inverter Output for POD-PWM Strategy 31
5.3.2.2.2 FFT Analysis for POD-PWM Strategy 32
5.3.2.3 Alternate Phase Opposed Disposition PWM
Strategy (APOD-PWM)
33
5.3.2.3.2 Inverter Output for APOD-PWM Strategy 33
5.3.2.3.3 FFT Analysis for APOD-PWM Strategy 34
5.4 Switching Pulses 35
5.4.1 Gate Switching Pattern for Fundamental Frequency
Method for 31-level topology
35
5.4.2 Gate Switching Pattern for Fundamental Frequency
Method for 7-level topology
37
5.4.3 Gate Switching Pattern for Phase Disposition PWM
Strategy (PD-PWM) for 31-level top
38
5.4.4 Gate Switching Pattern For Phase Disposition
PWM Strategy (PD-PWM) For 7-level
39
5.4.5 Gate Switching Pattern for Phase Opposition
Disposition PWM Strategy (POD-PWM) for 31-level
topology
40
5.4.6 Gate Switching Pattern for Phase Opposition
Disposition PWM Strategy (POD-PWM) for 7-level
topology
42
5.4.7 Gate Switching Pattern for Alternate Phase
Opposition Disposition PWM Strategy (APOD-PWM)
for 31-level topology
43
5.4.8 Gate Switching Pattern for Alternate Phase
Opposition Disposition PWM Strategy (APOD-PWM)
for 7-Level Topology
45
5.5 Comparison 46
5.6 Conclusion 47

CONTENTS MAY 2017
6 HARDWARE RESULTS
6.1 Introduction 48
6.2 Power Circuit 48
6.3 Transformer 48
6.4 Voltage Regulator 49
6.5 Gate Driver Circuit 49
6.6 Atmega 2560 50
6.7 Gate Pulse Produced By ATMEGA 2560 51
6.8 Gate Pulse Produced By ATMEGA 2560-
complementary switches
53
6.9 Gate Pulse Produced By Gate Driver TLP250 54
6.10 Switching Device 55
6.11 Hardware 56
6.12 Conclusion 57
7 CONCLUSION
7.1 General Conclusion 58
7.2 Conclusion 58
7.3 Future Scope 58
REFERENCES 60
APPENDIX

ABSTRACT MAY 2017
Department of EEE, ASE, Bangalore Page ii
ABSTRACT
Multilevel inverters have been developed to handle high power and high voltage
in the flexible power systems. They have emerged as one of the most powerful
power electronic devices with their dexterity to produce a high quality power in
the high voltage applications. They have received more appreciation due to their
potentiality to provide high voltage operation along with higher efficiency and
low electromagnetic interference (EMI). These inverters offer some inherent
advantages over conventional 2-level inverters. High quality of the output
voltage of the multilevel inverters is one of the most important advantages. In
this paper, new asymmetric multilevel inverter topology is proposed. The
proposed multilevel inverter uses reduced number of switching devices and dc
sources for a specified number of output voltage levels in comparison with the
conventional multilevel inverters and other non-conventional topologies. The
topology is analysed for level shift pulse width modulation over fundamental
frequency method. In order to validate it, the simulation is performed in
MATLAB software and comparative study is presented.

LIST OF FIGURES MAY 2017
LIST OF FIGURES
Figure No. Title Page No.
Fig 3.1 7-level topology 8
Fig 3.2 31-level topology 8
Fig 3.3.1 Mode 1, Output Voltage = VL1 12
Fig 3.3.2 Mode 2, Output Voltage = VR1 12
Fig 3.3.3 Mode 3, Output Voltage = VL1+VR1 12
Fig 3.3.4 Mode 4(a), Output Voltage = 0 12
Fig 3.3.5 Mode 4(b), Output Voltage = 0 12
Fig 3.3.6 Mode 5, Output Voltage = -VL1 12
Fig 3.3.7 Mode 6, Output Voltage = -VR1 13
Fig 3.3.8 Mode 7, Output Voltage = -( VL1+VR1) 13
Fig 3.4.1 Mode 1, Output Voltage = VL2+VR2 13
Fig 3.4.2 Mode 2, Output Voltage = VL2+VR2-VL1 13
Fig 3.4.3 Mode 3, Output Voltage = VL2+VR2 – VR1 13
Fig 3.4.4 Mode 4, Output Voltage = VL2+VR2-VL1- VR1 13
Fig 3.4.5 Mode 5, Output Voltage = VR2+VL1 14
Fig 3.4.7 Mode 7, Output Voltage = VL1- VR1+ VR2 14
Fig 3.4.8 Mode 8, Output Voltage = VR2 - VR1 14
Fig 3.4.9 Mode 9, Output Voltage = VL2+ VR1 14
Fig 3.4.10 Mode 10, Output Voltage = VL2+ VR1-VL1 14
Fig 3.4.13 Mode 13, Output Voltage = VL1+ VR1 15
Fig 3.4.16 Mode 16(a), Output Voltage = 0 15
Fig 3.4.17 Mode 16(b) 4, Output Voltage = 0 16
Fig 3.4.19 Mode 18, Output Voltage = - VR 1 16
Fig 3.4.20 Mode 19, Output Voltage = -(VL1+VR1) 16
Fig 3.4.21 Mode 20, Output Voltage = -(VL2 -VL1) 16

Fig 3.4.23 Mode 22, Output Voltage = - (VL2 -VL1+ VR1) 17
Fig 3.4.24 Mode 23, Output Voltage = - (VL2+ VR1) 17
Fig 3.4.25 Mode 24, Output Voltage = - (VR2- VR1) 17
Fig 3.4.26 Mode 25, Output Voltage = - (VL1-VR1+ VR2) 17
Fig 3.4.27 Mode 26, Output Voltage = -VR2 17
Fig 3.4.28 Mode 27, Output Voltage = - (VL1+VR2) 17
Fig 3.4.29 Mode 28, Output Voltage = - (VL2+VR2-VL1- VR1) 18
Fig 3.4.30 Mode 29, Output Voltage = - (VR2+VL2-VR1) 18
Fig 3.4.31 Mode 30, Output Voltage = - (VL2+VR2-VL1) 18
Fig 3.4.32 Mode 31 Output Voltage = - (VL2+VR2) 18
Fig 4.1 Fundamental Frequency Control 20
Fig 4.2 Carrier arrangement for PD-PWM strategy 21
Fig 4.3 Carrier arrangement for POD-PWM strategy 21
Fig 4.4 Carrier arrangement for APOD-PWM strategy 22
Fig 5.1 Single phase 7-level MLI 24
Fig 5.2 Single phase 31-level MLI 25
Fig 5.3 Voltage Waveform Output of 7-level MLI 25
Fig 5.4 Current Waveform Output of 31-level MLI 25
Fig 5.5 Voltage Waveform Output of 31-level MLI 26
Fig 5.6 Current Waveform Output of 31-level MLI 26
Fig 5.7 FFT Analysis of Voltage Waveform for 7-level MLI 27
Fig 5.8 FFT Analysis of Current Waveform for 7-level MLI 27
Fig 5.11 Simulation model for carrier based PWM strategy for 7 level
MLI
28
Fig 5.12 Simulation model for PD-PWM strategy for 31 level MLI 28
Fig 5.13 Voltage output waveform for 7- Level MLI 29
Fig 5.14 Current output waveform for 7- Level MLI 29
Fig 5.15 Voltage output waveform for 31 Level MLI 29
Fig 5.16 Current output waveform for 31 Level MLI 29

Fig 5.21 Voltage output waveform for 7- Level MLI 31
Fig 5.22 Current output waveform for 7-Level MLI 31
Fig 5.23 Voltage output waveform for 31 Level MLI 31
Fig 5.24 Current output waveform for 31 Level MLI 31
Fig 5.25 FFT Analysis of voltage waveform for 7-level MLI 32
Fig 5.26 FFT Analysis of current waveform for 7-level MLI 32
Fig 5.27 FFT Analysis of voltage waveform for 31-level MLI 32
Fig 5.28FF FFT Analysis of current waveform for 31-level MLI 32
Fig 5.29 Voltage output waveform of 7- Level MLI 33
Fig 5.30 Current output waveform of 7- Level MLI 33
Fig 5.31 Voltage output waveform of 31 Level MLI 33
Fig 5.32 C Current output waveform of 31 Level MLI 33
Fig 5.33 FFT Analysis of Voltage waveform for 7-level MLI 34
Fig 5.34FFT FFT Analysis of current waveform for 7-level MLI 34
Fig 5.35 FFT Analysis of Voltage waveform for 31-level MLI 34
Fig 5.36FFT FFT Analysis of current waveform for 31-level MLI 34
Fig 5.37.1 Pulse pattern for switches SL1 using fundamental reference
method for 31-level topology
35
Fig 5.37.2Puls Pulse pattern for switches SL2 using fundamental reference
35
35
35
Fig 5.37.5 Pulse pattern for switches SR1 using fundamental reference
36
36
36
36
Fig 5.37.9 Pulse pattern for switches Sa using fundamental reference
36
Fig 5.37.10 Pulse pattern for switches Sb using fundamental reference 36

method f for 7-level topology
37
37
37
37
Fig 5.38.5 Pulse pattern for switches Sa using fundamental reference
37
Fig 5.38.6 Pulse pattern for switches Sb using fundamental reference
37
Fig 5.39.1 Pulse pattern for switches SL1 using PD-PWM for 31-level
topology topology
38
topology topology
38
topology topology
38
topology topology
38
Fig 5.39.5 Pulse pattern for switches SR1 using PD-PWM for 31-level
topology topology
38
topology topology
38
topology topology
39
topology topology
39
Fig 5.39.9 Pulse pattern for switches Sa using PD-PWM for 31-level
topology topology
39
Fig 5.39.10 Pulse pattern for switches Sb using PD-PWM for 31-level
topolog topology
39
topology topology
39

topology topology
39
topology topology
40
topology topology
40
Fig 5.40.5 Pulse pattern for switches Sa using PD-PWM for 7-level
topology topology
40
Fig 5.40.6 Pulse pattern for switches Sb using PD-PWM for 7-level
topology topology
40
Fig 5.41.1 Pulse pattern for switches SL1 using POD-PWM for 31-level
topology topology
40
topology topology
40
topology topology
41
topology topology
41
Fig 5.41.5 Pulse pattern for switches SR1 using POD-PWM for 31-level
topology topology
41
topology topology
41
topology topology
41
topology topology
41
Fig 5.41.9 Pulse pattern for switches Sa using POD-PWM for 31-level
topology topology
42
Fig 5.41.10 Pulse pattern for switches Sb using POD-PWM for 31-level
topology topology
42
topology topology
42
topology topology
42
Fig 5.42.3 Pulse pattern for switches SR1 using POD-PWM for 7-level 42

topology topology
topology topology
42
Fig 5.42.5 Pulse pattern for switches Sa using POD-PWM for 7-level
topology topology
43
Fig 5.42.6 Pulse pattern for switches Sb using POD-PWM for 7-level
topology topology
43
Fig 5.43.1 Pulse pattern for switches SL1 using APOD-PWM for 31-
level top topology
43
level top topology
43
level top topology
43
level top topology
44
Fig 5.43.5 Pulse pattern for switches SR1 using APOD-PWM for 31-
level top topology
44
level top topology
44
level top topology
44
level top topology
44
Fig 5.43.9 Pulse pattern for switches Sa using APOD-PWM for 31-level
topology topology
44
Fig 5.43.10 Pulse pattern for switches Sb using APOD-PWM for 31-level
topology topology
44
Fig 5.44.1 Pulse pattern for switches SL1 using APOD-PWM for 7-level
topology topology
45
Fig 5.44.2 Pulse pattern for switches SL2 using APOD-PWM for 7-level
topology topology
45
Fig 5.44.3 Pulse pattern for switches SR1 using APOD-PWM for 7-level
topology topology
45
Fig 5.44.4 Pulse pattern for switches SR2 using APOD-PWM for 7-level
topology topology
45

Fig 5.44.5 Pulse pattern for switches Sa using APOD-PWM for 7-level
topology topology
45
Fig 5.44.6 Pulse pattern for switches Sb using APOD-PWM for 7-level
topology topology
45
Fig 6.1 Pin configuration of IC TLP250 49
Fig 6.2 Gate pulse produced by Atmega 2560 for switch SL1 51
Fig 6.3 Gate pulse produced by Atmega 2560 for switch SL2 51
Fig 6.4 Gate pulse produced by Atmega 2560 for switch SR1 52
Fig 6.5 Gate pulse produced by Atmega 2560 for switch SR2 52
Fig 6.6 Ga Ga Gate pulse produced by Atmega 2560 for switch Sa 52
Fig 6.7 Gate p Gate pulse produced by Atmega 2560 for switch Sb 52
Fig 6.8 Gat Gate pulses of complimentary switches SL1 &SL2 53
Fig 6.9 Ga Gate pulses of complimentary switches SR1 &SR2 53
Fig 6.10Gate Gate pulses of complimentary switches Sa &Sb 53
Fig 6.11Gate D Gate Driver TLP250 Output for switch SL1 54
Fig 6.12Gate D Gate Driver TLP250 Output for switch SL2 54
Fig 6.13Gate D Gate Driver TLP250 Output for switch SR1 54
Fig 6.14Gate D Gate Driver TLP250 Output for switch SR2 54
Fig 6.15Gate D Gate Driver TLP250 Output for switch Sa 54
Fig 6.16Gate D Gate Driver TLP250 Output for switch Sb 54
Fig 6.17 Delay between Complementary switches 0.5 µs 55
Fig 6.18 Hardware setup for 7-level topology 56
Fig 6.19Vo Voltage Output Waveform of 7 Level MLI 56

LIST OF ABBREVIATIONS MAY 2017
Department of EEE, ASE, Bangalore Page iii
LIST OF ABBREVIATIONS
APOD-PWM Alternate Phase Opposed Disposition Pulse Width
Modulation
CHB Cascaded h-bridge
CM Common Mode
CSI Current Source Inverter
EMI Electromagnetic interference
FC Flying Capacitor
HVDC High Voltage Direct Current
MC Multi-Cell Converter
MLI Multilevel Inverter
NPC Neutral Point Clamped
PD-PWM Phase Disposition Pulse Width Modulation
POD-PWM Phase Opposed Disposition Pulse Width Modulation
PWM Pulse Width Modulation
THD Total Harmonic distortion
VSI Voltage Source Inverter

LIST OF TABLES MAY 2017
Department of EEE, ASE, Bangalore Page iv
LIST OF TABLE
Table No. Title Page No.
Table 1 Output voltage of the proposed 31-level inverter as
presented in [12]
10
Table 2 Output voltage of the proposed 31-level inverter as
presented in [12]
11
Table 3 Comparative Analysis of Switching Strategies in 7-level
and 31-level topology
46

INTRODUCTION MAY2017
Department of EEE, ASE, Bangalore Page 1
CHAPTER 1
INTRODUCTION
1.1 GENERAL INTRODUCTION
A multilevel inverter (MLI) is a power electronic device which is capable of
providing desired alternating voltage level at the output using multiple lower level
DC voltages as an input. Mostly a two-level inverter is used in order to generate the
AC voltage from DC voltage. Multilevel converters are considered today as the state-
of-the-art power conversion systems for high-power and power quality demanding
applications. MLI are an enabling technology for industrial processes powered by
electric drive systems. They are potentially useful for a wide range of applications:
transport (train traction, ship propulsion, and automotive applications), energy
conversion, manufacturing, mining, and petrochemical, to name a few.
MLI are power-conversion systems composed of power semiconductors and
dc voltage sources that, when properly connected and controlled, can generate a
multiple-step voltage waveform with variable and controllable frequency, phase, and
amplitude. The number of levels of a converter can be defined as the number of steps
or constant voltage values that can be generated by the converter between the output
terminal and any arbitrary internal reference node within the converter.
Many different inverter topologies have been reported. Based on their
operation they are broadly classified into Voltage Source Inverters (VSI) and Current
Source Inverters (CSI). The most known and established topologies include the
neutral point clamped (NPC) or diode clamped, the flying capacitor (FC) or capacitor
clamped, and the cascaded H-bridge (CHB), each introduced for the first time in
respectively. The FC and CHB are also referred as multi-cell converters (MCs) due to
their modular structure composed of several smaller power converters called power
cells.
An NPC converter is basically composed of two traditional two-level VSCs
stacked one over the other with some minor modifications. Diode clamped multilevel

INTRODUCTION MAY 2017
inverters use clamping diodes in order to limit the voltage stress of power devices.
The negative bar of the upper converter and the positive bar of the lower one are
joined together to form the new phase output, while the original phase outputs are
connected via two clamping diodes to form the neutral point N, dividing the dc-link
voltage in two. The FC topology is in some way similar to the NPC, with the main
difference being that the clamping diodes are replaced by flying capacitors. Here the
load cannot be directly connected to the neutral of the converter to generate the zero
voltage level. Instead, the zero level is obtained by connecting the load to the Positive
or negative bar through the flying capacitor with opposite polarity with respect to the
dc-link. Like the NPC, only two gating signals are necessary per phase to avoid dc
link and flying capacitor short-circuit.
CHBs are multilevel inverters formed by the series connection of two or more
single-phase H-bridge inverters, hence the name. Each H-bridge corresponds to two
voltage source phase legs, where the line–line voltage is the inverter output.
Therefore, a single H-bridge inverter is able to generate three different voltage levels.
Each leg has only two possible switching states, to avoid dc-link capacitor short-
circuit. Since there are two legs, four different switching states are possible, although
two of them have redundant output voltage. When two or more H-bridges are
connected in series, their output voltages can be combined to form different output
levels, increasing the total inverter output voltage and also its rated power. CHB
presents more redundancies than the previous topologies, since each H-bridge or
power cell has one redundant switching state, and the series connection inherently
introduces more redundancies. The number of redundancies grows over
proportionally when increasing the number of cells. These redundancies and the
natural modularity of this topology are advantages that enable fault tolerant operation;
another advantage is the effective increase in the output voltage and power, since all
semiconductors have only to block Vdc.
1.2 ADVANTAGES OF MLI
 They can generate output voltages with very low distortion and lower dv/dt.

 The input current has very low distortion.
 They can produce smaller common mode (CM) voltage, therefore, reducing
the stress in the motoring bearings. In addition, by using complicated
modulation methods, CM voltages can be eliminated.
 They can be implemented with a much lower switching frequency.
1.3 DISADVANTAGES OF MLI
 It requires a huge number of semiconductor switches. It should be noted that
lower voltage rated switches can be used which does not considerably
increase the cost but each active switch requires associated gate drive circuitry
and adds further complication to the converter hardware layout.
 The small voltage steps are typically formed by isolated voltage sources or a
bank of series capacitors. Isolated voltage sources may not always be readily
available and series capacitors require voltage balance. To some extend, the
voltage balancing can be addressed by using an uncalled-for switching states,
which exist due to the high number of semiconductor devices. Nevertheless,
for a complete solution to the voltage-balancing problem, another MLI maybe
is required.
1.4 APPLICATIONS
 Power supply: An inverter converts dc from sources such as batteries, solar
panels, or fuel cells to ac (Uninterruptible power supplies). Grid tie inverters
can feed energy back into the distribution network as they produce voltage of
the same magnitude and frequency as that of supply. They can also switch off
automatically in the event of a blackout.

 High voltage direct current (HVDC) power transmission: In HVDC power
transmission, alternating current (AC) power is rectified and high voltage
direct current (DC) power is transmitted to another location. At the receiving
location, an inverter in a static inverter plant converts the power back to AC.
 Variable-frequency drives: A variable-frequency drive controls the operating
speed of an AC motor by controlling the frequency and voltage of the power
supplied to the motor. An inverter provides controlled power. In most cases,
the variable-frequency drive includes a rectifier so that DC power for the
inverter can be provided from AC mains. Since an inverter is the key
component, variable-frequency drives are sometimes called inverter drives or
just inverters.
 Electric vehicle drives: Adjustable speed motor control inverters are currently
used to power the traction motors in some electric and diesel-electric rail
vehicles as well as some battery electric vehicles and hybrid electric highway
vehicles such as the Toyota Prius. Various improvements in inverter
technology are being developed specifically for electric vehicle applications.
In vehicles with regenerative braking, the inverter also takes power from the
motor (now acting as a generator) and stores it in the batteries.
1.5 OBJECTIVE OF PROJECT
This project emphasizes on different modulation techniques on a single phase
extendable topology. The topology is analyzed for different levels of output voltage
generated with a comparative study of voltage and current total harmonic distortion
(THD) for various pulse width modulation (PWM) control strategies. The extendable
topology uses receded number of dc sources and switching devices over the
conventional cascaded H-bridge inverter, thereby reducing the circuit ramification
and cost. The performance of the switching strategies for 7-level and 31-level is
verified by simulation & hardware results. Validation of performance of 7-level
topology using fundamental frequency method is carried out using hardware.

LITERATURE SURVEY MAY 2017
CHAPTER 2
LITERATURE SURVEY
2.1 INTRODUCTION
In past years there has been many researches in the field of conventional inverter
topologies in order to improve the total harmonic distortion (THD) and reduce the losses in
the power electronic components. Various improved topologies came into existence with
advanced Pulse Width Modulated (PWM) techniques creating alternative solutions for the
development of Multi Level Inverter (MLI).
2.2 LITERATURE SURVEY
The cross switched inverter architecture is stressed upon in [1]. The proposed
framework utilizes low voltage switches making it perfect for high voltage applications. As
an added trait, the standing voltage of switches are relatively low with diminished number of
devices in the current path way. The negative mark of this symmetric topology is that, as the
quantity of yield voltage level increases, the number of required power electronic switches
increments appreciably. This results in high cost, sophisticated equipment circuit and lesser
productivity as the related switching losses significantly accumulates. A conceivable answer
for increment in the quantity of voltage levels with shortened number of switches is to utilize
dc voltage sources of unequal qualities. These architectures are named as asymmetrical.
To comprehend the focal points and inconveniences of the proposed topology, it is
contrasted with diverse topologies in view of the number of switches, voltage sources, and
the assortment of the size of DC voltage sources. In an examination, the traditional
asymmetrical cascaded H-bridge multilevel inverter indicates lessening in the number of
power electronic gadgets and apprehended modularity with emphasizes on limiting the cost
and intricacy. [2] Notices three unique techniques for deciding the magnitude of DC voltages
for the given topology.
In [3] - [6], distinctive structures have been displayed for the cascaded multilevel
inverter with new procedures and adjusted topologies with the lessened number of switches.

In [7] the circuit comprises of K dc voltage sources (cells) and 2(K+ 1) bi-directional
switches. Every essential component can create a step progressive voltage waveform. The
mix of these step voltages will yield a top notch voltage.
Another topology with various calculations have been displayed in [8] and [9] which
emphasizes on the reduction in power electronic devices and sources. This single-phased
MLI utilizing switched arrangement comprising of series/parallel dc Voltage Sources
proposed in [10] can yield more amplitude of voltage levels with the similar number of power
switches. This diminishes the quantity of gate driving circuits which prompts the
compactness of the structure and power utilization in the driving circuits. It is seen that THD
of the yield waveform is additionally diminished.
The inferred inverter architecture is driven by the hybrid modulation (HM) technique.
As the capacitors are associated in the series arrangement, the voltage of the switches is
diminished when a few of them are associated in a series arrangement. It can be reasoned that
the same number of voltage sources are expected to yield a similar number of voltage levels
when contrasted with traditional CHB inverters. In this switching, the reference waveform is
made to cut on the amplitude of the carrier waveform. Inferable from this certain factors such
modulation scheme, the number of switches and harmonics are enormously decreased.
Capacitors, batteries and other dc voltage sources can be utilized as the voltage sources for
the proposed inverter.
In [12], two essential topologies have been proposed for MLI to create seven voltage
levels at the yield. The prominent topologies can be created up to any number of levels at the
yield where the 31-level, 127-level, and general topologies are thus introduced. The
calculation decreases the quantity of dc sources, the number of switches yet the main
impediment being the utilization of the more extensive variety of the dc voltage sources in
the examination with those of all the previously mentioned topologies.
[11] depicts the different PWM methodologies involving Multicarrier Level Shift that
incorporates Phase Disposition (PD-PWM), Phase Opposed Disposition (POD-PWM) and
Alternate Phase Opposed Disposition (APOD-PWM) for better execution and reduction in
THD. These procedures incorporate the examination of the sinusoidal wave with different
carrier waves to deliver variable switching patterns. The carrier frequency relies on upon the

modulation indices. The carrier wave can be level displaced, phase shifted, then level and
phase manipulated, generating alternate positive and negative cycles with varied level and
phase properties. The signal quality deviates from one PWM to other.
2.3 CONCLUSION
According to the comparison results the proposed topology [12] requires
lesser number of IGBTs, power diodes, driver circuits and dc voltage sources.
Moreover, the magnitude of the blocking voltage of the switches is lower than that of
conventional topologies. Due to this feature this extendable topology provides high
voltage operation along with higher efficiency and low EMI. Together with the
development of multilevel inverter topologies appears the challenge to extend
traditional modulation methods to the multilevel case. The modulation algorithms are
classified depending on the average switching frequency with which they operate.

REDUCED SWITCH TOPOLOGY MAY 2017
CHAPTER 3
REDUCED SWITCH TOPOLOGY
3.1 INTRODUCTION
In order to increase the number of output voltage levels and reduce the
number of power switches, driver circuits and the total cost of the inverter, a new
topology is proposed in [12]. This chapter discusses the topology, switching pattern
and mode of operation of the presented topology.
3.2 CIRCUIT DIAGRAM
The circuit diagram for the proposed topology 7 level and 31 are shown in
Fig. 3.1 and Fig. 3.2
Fig. 3.1 7-level topology
Fig. 3.2 31-level topology

In the general topology, the number of output voltage levels (Nstep), number
of switches (Nswitch), number of dc voltage sources (Nsource), and the maximum
magnitude of the generated voltage (Vo,max) are calculated as follows:
Nstep =22n+1
-1
Nswitch =4n + 2
Nsource =2n
Vo, max =VL,n + VR,n
The magnitudes of the dc voltage sources of the proposed general multilevel
inverter can be obtained as follows:
VL,j =5j−1
Vdc for j = 1,2,3,...,n
VR,j =2× 5j−1
Vdc for j = 1,2,3,...,n
3.3 WORKING
To synthesize a 7-level and 31-level output the switches are turned on and off
according to the switching pattern described in table 3.1and 3.2. The operation can be
explained as during the positive cycle switch Sb is turned on and level selecting
switches are operated to get different voltage levels. To generate the negative half
cycle switch Sa is conducting while other switches are operated in a particular pattern
to get a staircase voltage at output. To obtain first level VL1 is connected to the load.
To generate the second level VL1 and VL2 must be connected to load. The rest of the
sources are connected in a similar manner. The switches are controlled in such a way
that respective sources are connected to the load during desired time intervals.
3.4 SWITCHING SEQUENCE
Table 3.1 and 3.2 shows the output voltages of the proposed inverter for
different states of the switches as presented in paper [12]. In these tables, 1 and 0

indicate the ON and OFF states of the switches respectively. From the table it is well
understood that if (SL1, SL2), (SL3, SL4), (SR1, SR2) and (SR3, SR4) are turned on
simultaneously, the dc voltage sources of VL1, VL2, VR1 and VR2 will be short-
circuited respectively. In addition, Sa and Sb should not turn on simultaneously.
3.5 MODES OF OPERATION
Operation of the proposed 7-level Multi Level Inverter can be easily
explained with the help of Fig.3.3.1-3.3.8 and table 3.1. The magnitudes of the dc
voltage sources of the proposed 31-level inverter are given as VL1 =Vdc, VR1
=2Vdc where Vdc is taken as 5V. The proposed inverter can generate all negative
and positive voltage levels from 0 to 3Vdc with steps of Vdc.
Working of the proposed 31-level Multi Level Inverter can be well
understood with the help of Fig.3.4.1-3.4.32 and table 3.2. The magnitudes of the
dc voltage sources of the proposed 31-level inverter are given as VL1 =Vdc, VR1
=2Vdc, VL2 =5Vdc VR2 =10Vdc where Vdc is taken as 15V.The proposed
inverter can generate all negative and positive voltage levels from 0 to 15Vdc with
steps of Vdc.
TABLE 3.1
Output voltage of the proposed 7-level inverter as presented in [12]

TABLE 3.2
Output voltage of the proposed 31-level inverter as presented in [12]

3.5.1 MODE OF OPERATION FOR 7-LEVEL MLI
Fig. 3.3.1 Mode 1, Output Voltage = VL1 Fig. 3.3.2 Mode 2, Output voltage =VR1
Fig. 3.3.3 Mode 3, Output Voltage = VL1+VR1 Fig. 3.3.4 Mode 4(a) Output Voltage = 0
Fig. 3.3.5 Mode 4(b), Output Voltage = 0 Fig. 3.3.6 Mode 5, Output Voltage = -VL1

Fig.3.3.7 Mode 6, Output Voltage = -VR1 Fig.3.3.8 Mode 7, Output Voltage = -( VL1+VR1)
3.5.2 MODE OF OPERATION FOR 31-LEVEL MLI
Fig. 3.4.1 Mode 1, Output Voltage = VL2+VR2 Fig. 3.4.2 Mode 2, Output Voltage =
VL2+VR2-VL1
Fig.3.4 .3 Mode 3, Output Voltage = VL2+VR2- Fig.3.4.4 Mode 4 Output Voltage = VL2+VR2-
VR1 VL1- VR1

Fig. 3.4 .5 Mode 5, Output Voltage = VR2+VL1 Fig.3.4 .6 Mode 6, Output Voltage = VR2
Fig. 3.4.7 Mode 7, Output Voltage = VL1- VR1 Fig 3.4.8 Mode 8, Output Voltage = VR2 - VR1
+ VR2
Fig.3.4 .9 Mode 9, Output Voltage = VL2+ VR1 Fig.3.4.10 Mode 10, Output Voltage =
VL2+ VR1-VL1

Fig. 3.4.11 Mode 11, Output Voltage = VL2+VR1 Fig. 3.4.12 Mode 12, Output Voltage = VL1
+VR1
Fig. 3.4.13 Mode 13, Output Voltage = VL1+ VR1 Fig. 3.4.14 Mode 14, Output Voltage = VR1
Fig. 3.4.15 Mode 15, Output Voltage = VL1 Fig. 3.4.16 Mode 16(a), Output Voltage = 0

Fig. 3.4 .17 Mode 16(b) 4, Output Voltage = 0 Fig. 3.4.18 Mode 17, Output Voltage = -VL1
Fig.3.4.19 Mode 18, Output Voltage = - VR 1 Fig.3.4..20 Mode 19, Output Voltage =
-(VL1+VR1)
Fig.3.4.21 Mode 20, Output Voltage = Fig. 3.4 .22 Mode 21, Output Voltage = -VL2
-(VL2 -VL1)

Fig. 3.4 .23 Mode 22, Output Voltage =- Fig. 3.4 .24 Mode 23, Output Voltage = - (VL2+
(VL2 -VL1+ VR1) VR1)
Fig. 3.4 .25 Mode 24, Output Voltage = - (VR2- VR1) Fig. 3.4.26 Mode 25, Output Voltage = -
(VL1-VR1+ VR2)
Fig. 3.4.27 Mode 26, Output Voltage = -VR2 Fig. 3.4 .28 Mode 27, Output
Voltage (VL1+VR2)

Fig. 3.4 .29 Mode 28, Output Voltage = Fig. 3.4 30 .Mode 29, Output Voltage= -
- (VL2+VR2-VL1- VR1) (VR2+VL2-VR1)
Fig. 3.4 .31 Mode 30, Output Voltage = - (VL2+VR2-VL1) Fig. 3.4 .32 Mode 31 Output Voltage = -
(VL2+VR2)
3.6 CONCLUSION
The modes of operation and switching pattern for the topology to obtain
various levels of output voltage are discussed in detail in this chapter. Using the
details, gate driving pulses to drive the switches can be easily developed

MODULATION METHODS MAY 2017
CHAPTER 4
MODULATION METHODS
4.1 INTRODUCTION
Together with the development of multilevel inverter topologies appeared the
challenge to extend traditional modulation methods to the multilevel case. On one
hand, there is the inherent additional complexity of having more power-electronics
devices to control, and on the other the possibility to take advantage of the extra
degrees of freedom provided by the additional switching states generated by these
topologies. As a consequence, a large number of different modulation algorithms
have been adapted or developed depending on the application and the converter
topology, each one having unique advantages and drawbacks. The various PWM
techniques implemented for the proposed topology are discussed in this chapter.
4.2 FUNDAMENTAL REFERENCE METHOD
The fundamental frequency control method tends to generate a staircase
voltage which minimizes the error with respect to the reference voltage and is known
as nearest level (or round) control method [1]. The principle of the nearest level
control method is shown in Fig.4.1. In this method, the sinusoidal reference voltage
(50 Hz) is compared with the available dc voltage levels and the level is chosen that
is nearest to the reference voltage. Consequently, the proper switches are turned on to
generate the desired voltage level. For example, if the reference voltage is between −
0.5Vdc and 1.5Vdc, then the staircase output voltage will be zero. Similarly, if the
reference voltage is between 1.5Vdcand 2.5Vdc, then the staircase output voltage will
be equal to 2Vdc

Fig. 4.1 Fundamental Frequency Control
4.3 LEVEL-SHIFTED PWM
Level-shifted PWM (LSPWM) is the natural extension of bipolar PWM for
multilevel inverters. Bipolar PWM uses one carrier signal that is compared to the
reference to decide between two different voltage levels, typically the positive and
negative bus bars of a VSI. By generalizing this idea, for a multilevel inverter, N-1
carriers are needed. They are arranged in vertical shifts instead of the phase-shift used
in PS-PWM. Each carrier is set between two voltage levels; hence the name level
shifted. Since each carrier is associated to two levels, the same principle of bipolar
PWM can be applied, taking into account that the control signal has to be directed to
the appropriate semiconductors in order to generate the corresponding levels. The
carriers span the whole amplitude range that can be generated by the converter. They
can be arranged in vertical shifts, with all the signals in phase with each other, called
phase disposition (PD-PWM); with all the positive carriers in phase with each other
and in opposite phase of the negative carriers, known as phase opposition disposition
(POD-PWM); and alternate phase opposition disposition (APOD-PWM), which is
obtained by alternating the phase between adjacent carriers.
4.3.1 PHASE DISPOSITION PWM STRATEGY (PD-PWM)
In PD PWM method (m-1) carrier signals with the same frequency fc and
same amplitude Ac are positioned such that the bands they occupy are contiguous.
The reference wave form is a single sinusoidal wave. During the continuous
comparison, if the reference wave form is greater than a carrier waveform, then the

active switching device corresponding to that carrier is switched on. Otherwise, that
concerned device is switched off. Amplitude of modulation index for PD PWM is
ma = 2A m / (m-1) Ac
Fig. 4.2 Carrier arrangement for PD-PWM strategy
4.3.2 PHASE OPPOSED DISPOSITION PWM STRATEGY (POD-PWM)
In this control strategy the carrier waveforms above the zero reference are in
phase whereas the carrier waveforms below are 180 degrees phase shifted from those
above zero. The reference wave form is a single sinusoidal wave. During the
continuous comparison, if the reference wave form is greater than a carrier waveform,
then the active switching device corresponding to that carrier is switched on.
Otherwise, that concerned device is switched off. Amplitude of modulation index for
POD-PWM is ma = 2Am / (m-1)* Ac
Fig. 4.3 Carrier arrangement for POD-PWM strategy

4.3.3 ALTERNATE PHASE OPPOSITION DISPOSITION PWM STRATEGY
(APOD-PWM)
In APOD strategy multiple carriers having same amplitude are phase
displaced from each other by 180 degrees alternately. During the continuous
comparison, if the reference wave form is more than a carrier waveform, then the
active switching device corresponding to that carrier is switched on. Otherwise, that
concerned device is switched off. Amplitude of modulation index for APOD-PWM is
ma= 2Am / (m-1)* A
Fig. 4.4Carrier arrangement for APOD-PWM strategy
4.4 CONCLUSION
The main advantages of PWM methods mentioned above include (i) control
over output voltage magnitude (ii) reduction in magnitudes of unwanted harmonic
voltages (iii) Good quality output voltage. The simulation for the same is performed
and analyzed for reduction in THD.

SIMULATION AND ANALYSIS MAY 2017
CHAPTER 5
SIMULATIONS AND ANALYSIS
5.1 INTRODUCTION
The 7 level and 31 Level reduced switch topology is modeled and tested in
Matlab Simulink. Matlab is one of the powerful tools for simulation and used for design
in power electronics, motor drives and dynamic system simulations. It is a software
development environment that offers high-performance numerical computation, data
analysis, visualization capabilities and application development tools. It also offers
higher accuracy as compared to other simulation tools such as PSCAD.
5.2 SIMULATION RESULTS
The simulation of reduced 7 level and 31 level topology with RL load proposed
in [1 ] has been implemented using Matlab. The different modes of operation have been
realized according to the corrected switching pattern. The topology is analyzed for
various control strategies to study the reduction in THD.
5.3 SIMULATION OF 31-LEVEL SINGLE PHASE REDUCED SWITCH
TOPOLOGY
In all processes of the simulation, the load is assumed as R–L with R = 55Ω and
L = 47 mH. Moreover, to generate 7 levels, the magnitude of VL,1 is taken as 5 V, so
based on equations, the magnitudes of the other dc voltage source VR,1 will be 10. The
maximum output voltage of this inverter will be 15 V. Correspondingly, to obtain 31
levels the magnitude of VL,1 is taken as 15 V, so based on the equations the magnitudes
of the other dc voltage sources will be 30, 75, and 150 V, which are related to VR,1, VL,2,
and VR,2, respectively. The maximum output voltage of this inverter will be 225 V. The
pulse pattern for all the switches has been implemented in Matlab Simulink in
accordance with topology switching table generated for the 7 level and 31 level output.

Simulation results for fundamental frequency method, PD-PWM strategy POD-PWM
strategy and APOD-PWM strategy are discussed below
5.3.1 FUNDAMENTAL SWITCHING FREQUENCY CONTROL
In this method the sinusoidal reference voltage (50 Hz) is compared with the
available dc voltage levels and the level is chosen that is nearest to the reference
voltage. Consequently, the proper switches are turned on to generate the desired voltage
level. The output will be a staircase voltage with minimum possible error with respect to
the reference voltage.
5.3.1.1 SIMULATION MODEL
Fig. 5.1 Single phase 7-level MLI

Fig. 5.2 Single phase 31-level MLI
5.3.1.2 INVERTER OUTPUT FOR FUNDAMENTAL REFERENCE METHOD
The 7-level and 31-level inverter output has multi levels of voltages of unequal
step time width, hence it resembles much more to a sine wave. As a result, the
harmonics spectrum of the output voltage and current is improved. The simulation
results prove that the switching frequency is low, thereby reducing the switching
losses.The inverter output is connected to a RL load of R=55Ω &L=47mH which causes
current to lag. The peak output voltage and current for 7-level and 31-level topology is
observed as shown in Fig 5.3 to 5.6.
Fig. 5.3 Voltage Waveform Output of 7- Level MLI Fig.5.4 Current Waveform Output of 7-Level MLI

Fig 5.5 Voltage Waveform Output of 31-level MLI Fig.5.6 Current Waveform Output of 31-level MLI
The output is connected to a RL load of R=55Ω &L=47mH which causes
observed as shown in Fig. 5.3 to 5.6.
5.3.1.3 FFT ANALYSIS FOR FUNDAMENTAL REFERENCE METHOD
Fast Fourier Transform [FFT] has been performed on 7 level and 31 level
current and voltage waveforms in order to determine the Total Harmonic Distortion
[THD] in each signal. The simulated results are as shown in Fig. 5.7 to 5.10. We
observe that all the higher order harmonics are eliminated.

Fig. 5.7 FFT Analysis of Voltage Waveform for Fig. 5.8 FFT Analysis of Current Waveform for
7-level MLI 7-level MLI
Fig.5.9 FFT Analysis of Voltage Waveform for Fig. 5.10 FFT Analysis of Current Waveform for
31-level MLI 31-level MLI
5.3.2 LEVEL SHIFTED PWM
In this section three types of level shifted PWM has been implemented in order
to perform a comparative study on the THD using PD-PWM, POD-PWM and APOD-
PWM. The single sinusoidal reference signal is continuously compared with all the
carrier waveforms to generate a pulse, whenever the single sinusoidal reference signal is
greater than the carrier signal.

5.3.2.1 PHASE DISPOSITION PWM STRATEGY (PD-PWM)
5.3.2.1.1 CIRCUIT MODEL
Fig. 5.11 Simulation model for carrier based PWM strategy for 7 level MLI
Fig. 5.12 Simulation model for PD-PWM strategy for 31 level MLI
In these simulation models as shown in Fig 5.11 and 5.12 dc offset carrier
signals with the same frequency fc and same amplitude Ac are positioned such that the
bands they occupy are contiguous. The reference wave form is a single sinusoidal wave.
During the continuous comparison, if the reference wave form is more than a carrier
waveform, then the active switching device corresponding to that carrier is switched on.
Otherwise, that concerned device is switched off.

5.3.2.1.2 INVERTER OUTPUT FOR LEVEL SHIFTED PD PWM STRATEGY
Fig. 5.13 Voltage output waveform for 7- level MLI Fig.5.14 Current output waveform for 7- level MLI
Fig.5.15 Voltage output waveform for 3-level MLI Fig .5.16 Current output waveform for 31 Level MLI
The inverter output is connected to a RL load of R=55Ω &L=47mH causing
observed as shown in figure 5.13 to 5.16. Unlike fundamental frequency method, PD-
PWM method gives a pulse width modulated sinusoidal wave. Hence the synthesized
wave is more sinusoidal in nature compared to critically stepped output voltage
waveforms.

5.3.2.1.3 FFT ANALYSIS LEVEL SHIFTED PD PWM STRATEGY
Fig. 5.17 FFT Analysis of Voltage Waveform for 7-level MLI Fig. 5.18 FFT Analysis of Current
Waveform for 7-level MLI
Fig. 5.19 FFT Analysis of Voltage Waveform for Fig. 5.20 FFT Analysis of Current Waveform
31-level MLI for 31-level MLI

5.3.2.2 PHASE OPPOSED DISPOSITION PWM STRATEGY (POD-PWM)
In this simulation model, carrier waveforms are 180 degrees phase shifted from
those above zero. The reference wave form is single sinusoidal. During the continuous
comparison, if the reference wave form is more than a carrier waveform, then the active
switching device corresponding to that carrier is switched on.
5.3.2.2.2 INVERTER OUTPUT FOR POD –PWM STRATEGY
Fig.5.21 Voltage output waveform for 7- Level MLI Fig.5.22 Current output waveform for 7-level MLI
Fig.5.23 Voltage output waveform for 31 -level MLI Fig.5.24 Current output waveform for 31- level
MLI
The waveforms are connected to a RL load of R=55Ω &L=47mH causing current to lag.
The peak output voltage and current for 7-level and 31-level topology is observed as
shown in Fig 5.21 to 5.24. Unlike fundamental frequency method, PD-PWM method
gives a pulse width modulated sinusoidal wave. Hence the synthesized wave is more
sinusoidal in nature compared to critically stepped output voltage waveforms.

5.3.2.2.3 FFT ANALYSIS FOR POD –PWM STRATEGY
Fig.5.25 FFT Analysis of voltage waveform for 7-level Fig.5.26 FFT Analysis of current waveform for 7-
level MLI
Fig.5.27 FFT Analysis of voltage waveform Fig. 5.28 FFT Analysis of current
for 31-level MLI waveform for 31-level MLI

5.3.2.3 ALTERNATE PHASE OPPOSED DISPOSITION PWM STRATEGY
(APOD- PWM)
In this simulation model, the carrier waveforms are 180 degrees phase shifted
alternatively. The reference wave form is single sinusoidal wave. During the continuous
comparison, if the reference wave form is more than a carrier waveform, then the active
switching device corresponding to that carrier is switched on. Otherwise, that concerned
device is switched off.
5.3.2.3.2 INVERTER OUTPUT FOR APOD- PWM STRATEGY
Fig 5.29 Voltage output waveform of 7-level MLI Fig.5.30 Current output waveform of 7- level MLI
Fig. 5.31 Voltage output waveform of 31-level MLI Fig.5.32 Current output waveform of 31-level MLI

The waveforms are connected to a RL load of R=55Ω &L=47mH causing current to lag.
The peak output voltage and current for 7-level and 31-level topology is observed as
shown in Fig. 5.29 to 5.32. Unlike fundamental frequency method, APOD-PWM
method gives a pulse width modulated sinusoidal wave. Hence the synthesized wave is
more sinusoidal in nature compared to critically stepped output voltage waveforms.
5.3.2.3.3 FFT ANALYSIS
observe that all the higher order harmonics are eliminated
Fig. 5.33 FFT Analysis of Voltage waveform Fig. 5.34 FFT Analysis of Current waveform for
for 7-level MLI 7-level MLI
Fig. 5.35 FFT Analysis of Voltage waveform Fig. 5.36 FFT Analysis of Current waveform
for 31-level MLI for 31-level MLI

5.4 SWITCHING PULSES
The switching pulses for each active switch for the above discussed control
strategies are shown below. It is observed that switching frequency varies for each
PWM technique giving a better THD thereby reducing distortion.
5.4.1 GATE SWITCHING PATTERN FOR FUNDAMENTAL FREQUENCY
METHOD FOR 31-LEVEL
Fig. 5.37.1 Pulse pattern for switches SL1 Fig. 5.37.2 Pulse pattern for switches SL2
Fig. 5.37.3Pulse pattern for switches SL3 Fig. 5.37.4 Pulse pattern for switches SL4

Fig.5.37.5 Pulse pattern for switches SR1 Fig. 5.37.6 Pulse pattern for switches SR2
Fig.5.37.7 Pulse pattern for switches SR3 Fig.5.37.8 Pulse pattern for switches SR4
Fig.5.37.9 Pulse pattern for switches Sa Fig.5.37.10 Pulse pattern for switches Sb

5.4.2 GATE SWITCHING PATTERN FOR FUNDAMENTAL FREQUENCY
METHOD FOR 7-LEVEL
Fig. 5.38.1 Pulse pattern for switches SL1 Fig. 5.38.2 Pulse pattern for switches SL2
Fig. 5.38.3 Pulse pattern for switches SR1 Fig. 5.38.4 Pulse pattern for switches SR2
Fig. 5.8.5 Pulse pattern for switches Sa Fig. 5.38.6 Pulse pattern for switches Sb

5.4.3 GATE SWITCHING PATTERN FOR PHASE DISPOSITION PWM
STRATEGY (PD-PWM) 31-LEVEL
Fig. 5.39.1 Pulse pattern switches SLl Fig. 5.39.2 Pulse pattern switches SL2
Fig. 5.39.3 Pulse pattern switches SL3 Fig. 5.39.4 Pulse pattern switches SL4
Fig. 5.39.5 Pulse pattern switches SR1 Fig. 5.39.6 Pulse pattern switches SR2

Fig.5.39.7 Pulse pattern switches SR3 Fig.5.39.8 Pulse pattern switches SR4
Fig.5.39.9 Pulse pattern switches Sa Fig.5.39.10 Pulse pattern switches Sb
5.4.4 GATE SWITCHING PATTERN FOR PHASE DISPOSITION PWM
STRATEGY (PD-PWM) FOR 7-LEVEL
Fig.5.40.1 Pulse pattern switches SLl Fig.5.40.2 Pulse pattern switches SL2

Fig.5.40.3 Pulse pattern switches SR1 Fig.5.40.4 Pulse pattern switches SR2
Fig. 5.40.5 Pulse pattern switches Sa Fig. 5.40.6 Pulse pattern switches Sb
5.4.5 GATE SWITCHING PATTERN FOR PHASE OPPOSITION
DISPOSITION PWM STRATEGY (POD-PWM) FOR 31-LEVEL MLI

5.4.6 GATE SWITCHING PATTERN FOR PHASE OPPOSITION
DISPOSITION PWM STRATEGY (POD-PWM) FOR 7-LEVEL

5.4.7 GATE SWITCHING PATTERN FOR ALTERNATE PHASE OPPOSITION
DISPOSITION PWM STRATERGY (APOD-PWM) FOR 31-LEVEL
Fig. 5.43.1 Pulse pattern switch SL1 Fig. 5.43.2 Pulse pattern switch SL2
Fig. 5.43.3 Pulse pattern switch SL3 Fig.5.43.4 Pulse pattern switch SL4

Fig. 5.43.5 Pulse pattern switch SR1 Fig. 5.43.6 Pulse pattern switches SR2

5.4.8 GATE SWITCHING PATTERN FOR ALTERNATE PHASE
OPPOSITION DISPOSITION PWSTRATERGY (APOD-PWM) FOR 7-LEVEL
Fig. 5.44.5 Pulse pattern switch Sa Fig. 5.44.6 Pulse pattern switch Sb

5.5 COMPARISON
Compared to fundamental frequency method, Multi-carrier PWM techniques
offer reduced voltage and current THD thereby reducing the losses and achieving
higher efficiency. According to the table given below the simulation results henceforth
proves that PD-PWM, POD-PWM and APOD-PWM furnish better results.
TABLE 5.1
Comparative Analysis of Switching Strategies in 7-level and 31-level topology

5.6 CONCLUSION
The comparative study of different modulation techniques show that
POD-PWM produces reduced THD as compared to Fundamental frequency method,
PD-PWM and APOD-PWM. It is observed that lower order harmonics are minimized.

HARDWARE RESULTS MAY 2017
CHAPTER 6
HARDWARE RESULTS
6.1 INTRODUCTION
The 7 Level Multilevel Inverter with reduced switch topology is implemented
using fundamental frequency method and switching pulses are generated using a
microcontroller. The various requirements for the circuit includes Regulated Power
Supplies, transformers ,gate driver, regulators, switches.
6.2 POWER CIRCUIT
The load used for the application is an RL load with R=47Ω and
L=55mH.The inverter has been designed for an output voltage with 15V peak
amplitude. The design can be extended for inductive loads. The output has been
verified using simulations for 7 level Multilevel Inverter. The hardware photograph is
shown in the Fig. Two DC voltage sources are required for the stressed topology. For
this purpose a Regulated Power Supply(RPS) of output voltage +10,+5 has been
utilized.
6.3 TRANSFORMER
The transformer is a static electrical device that transfers energy by inductive
coupling between its winding circuits. A varying current in the primary winding
creates a varying magnetic flux in the transformer's core and thus a varying magnetic
flux through the secondary winding. This varying magnetic flux induces a varying
electromotive force (E.M.F) or voltage in the secondary winding. The transformer has
cores made of high permeability silicon steel. The steel has a permeability many
times that of free space and the core thus serves to greatly reduce the magnetizing
current and confine the flux to a path which closely couples the windings. The
transformer used in this project is a general purpose chassis mounting mains
transformer. Transformer has 240 V primary windings and centre tapped secondary
winding. It acts as a step down transformer reducing AC - 240V to AC - 12V.The

Transformer gives two outputs of 24V, 12V and 0V. The Transformer is made of soft
iron core with 500mA current rating.
6.4 VOLTAGE REGULATOR
Each switching circuit has been provided with a 230V step down transformer
of 12 0 12 which feeds a voltage regulator which outputs 12V DC voltage which
drives the VCC of IC TLP250 gate driver circuit in order to amplify the signals.
6.5 GATE DRIVER CIRCUIT
The pulses produced by the control unit is only of 5V which is less than the
threshold value for driving the switches. A gate driver is a power amplifier that
accepts a low-power input from ATMEGA2560 and produces a high-current drive
input for the gate of the high-power IGBT. TLP250 is used for driver circuit to
amplify the gate pulses applied to each switch. The connections for the IC TLP 250
are as shown in the Figure. The second pin of the gate driver is being actuated by the
digital high pin of the Arduino and the ground is being provided to the third pin.VCC
input of 12V is fed to pin 8 and pin 5 is grounded. Pin 6 is the Output pin .
Fig. 6.1 Pin configuration of IC TLP250

6.6 ATMEGA 2560
The ATmega2560 is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture. By executing powerful instructions in a single
clock cycle, the ATmega2560 achieves throughputs approaching 1 MIPS per MHz
allowing the system designed to optimize power consumption versus processing
speed. The device is manufactured using the Atmel high-density nonvolatile memory
technology. By combining an 8-bit RISC CPU with In-System Self-Programmable
Flash on a monolithic chip, the Atmel ATmega2560 is a powerful microcontroller
that provides a highly flexible and cost effective solution to many embedded control
applications. The ATmega2560 AVR is supported with a full suite of program and
system development tools including: C compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits. The control gate pulses
produced to drive the switches as shown in Fig. 6.2 to 6.7
1) ATMEGA2560-16AU Features:
 High Performance, Low Power Atmel AVR 8-Bit Microcontroller
 Advanced RISC Architecture
o 135 Powerful Instructions – Most Single Clock Cycle Execution
o 32 × 8 General Purpose Working Registers
o Fully Static Operation
o Up to 16 MIPS Throughput at 16MHz
o On-Chip 2-cycle Multiplier
 High Endurance Non-volatile Memory Segments
o 64K/128K/256KBytes of In-System Self-Programmable Flash
o 4Kbytes EEPROM
o 8Kbytes Internal SRAM
o Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

o Optional Boot Code Section with Independent Lock Bits
o In-System Programming by On-chip Boot Program
o True Read-While-Write Operation
o Programming Lock for Software Security
 I/O and Packages
o 54/86 Programmable I/O Lines
o 100-lead TQFP, 100-ball CBGA
 Temperature Range:40°C to 85°C
 Ultra-Low Power Consumption
o Active Mode: 1MHz, 1.8V: 500μA
o Power-down Mode: 0.1μA at 1.8V
6.7 GATE PULSE PRODUCED BY ATMEGA 2560
Fig. 6.2 Gate pulse produced by Atmega 2560 Fig. 6.3 Gate pulse produced by Atmega 2560
for switch SL1 for switch SL1

Fig. 6.4 Gate pulse produced by Atmega 2560 Fig. 6.5 Gate pulse produced by Atmega 2560 for
for switch SR1 switch SR2
Fig. 6.6 Gate pulse produced by Atmega 2560 Fig. 6.7 Gate pulse produced by Atmega 2560 for
switch Sb for switch Sa

6.8 GATE PULSE PRODUCED BY ATMEGA 2560- COMPLIMENTARY
SWITCHES
Fig. 6.8 Gate pulses of complimentary switches Fig.6.9 Gate pulses of complimentary switches
SL1 &SL2 SR1 &SR2
Fig. 6.10 Gate pulses of complimentary switches Sa &Sb

6.9 GATE PULSE PRODUCED BY GATE DRIVER TLP250
Fig. 6.11Gate Driver TLP250 Output for switch SL1 Fig. 6.12 Gate Driver TLP250 Output
for switch SL2
Fig. 6.13 Gate Driver TLP250 Output for Fig. 6.14 Gate Driver TLP250 Output for switch
switch SR1 SR2
Fig. 6.15 Gate Driver TLP250 Output for switch Sa Fig.6.16 Gate Driver TLP250 Output for
switch Sb

6.10 SWITCHING DEVICE
Switch IRG4BC20UD has been selected for the MLI the output voltage and
current been analyzed through simulations and the particular switch has been chosen
with specifications greater than three times as a safety factor. The datasheet has been
added in the reference. A switching delay of 0.5 µs has been incorporate as shown in Fig.
6.18 to avoid shorting of complimentary switches. The voltage specifications of the
switch include VCES = 600V,VCE (on) = 1.85V,VGE = 15V, IC = 6.5A.The first
terminal represents the gate terminal, second collector and third represents emitter.
The delay between two complimentary switches on the same leg of the inverter is
provided as shown in Fig.6.17.
Fig 6.17 Delay between Complementary switches 0.5 µs

6.11 HARDWARE RESULTS
The hardware setup was rigged up on the wooden plank by connecting the
circuits through patch chords.The gate pulses are actuated by the TLP250 which
drives the switch soldered on the PCB board. The hardware for the seven level
topology is as shown in Fig.6.18 .The output voltage waveform of seven levels has
being observed across the RL load.
Fig 6.18 Hardware setup for 7-level topology
Fig. 6.19 Voltage Output Waveform of 7 Level MLI

6.12 CONCLUSION
Single phase 7 level and 31 level MLI inverter performance has been analyzed
for various multi carrier sinusoidal PWM strategies using Matlab simulation. This
topology has the credit of having only ten switches and four voltage sources
compared to other topologies thereby aiding to reduction in switching losses, cost and
circuit complexity. Performance factors like %THD, voltage and current have been
measured, and analyzed for fundamental frequency method and three different, level
shifted carrier wave arrangements. It is found that the POD-PWM strategy provides
less %THD and acceptable output voltage and current with elimination of dominant
harmonics than the other strategies. Hardware implementation of 7 level proposed
topology has been carried out using fundamental frequency method and output results
are obtained for the same.

CONCLUSION MAY 2017
CHAPTER 7
CONCLUSION
7.1 GENERAL CONCLUSION
The performance of 7 level and 31 level reduced switch topology was
analyzed using different control techniques. The MATLAB simulation for different
PWM techniques for the proposed topology is performed and analyzed for reduction
in THD. The output voltage, current and harmonic analysis for fundamental
frequency method, PD-PWM, POD-PWM, APOD-PWM is studied and compared.
7.2 CONCLUSION
Single phase 7 level and 31 level MLI inverter performance has been analyzed
for various multi carrier sinusoidal PWM strategies using Matlab simulation. This
topology has the credit of having only ten switches and four voltage sources
compared to other topologies thereby aiding to reduction in switching losses, cost and
circuit complexity. Performance factors like %THD, voltage and current have been
measured, and analyzed for fundamental frequency method and three different, level
shifted carrier wave arrangements. It is found that the POD-PWM strategy provides
less %THD and acceptable output voltage and current with elimination of dominant
harmonics than the other strategies. Hardware implementation of 7 level proposed
topology has been carried out using fundamental frequency method and partial
outputs are obtained for the same
7.3 FUTUTRE SCOPE
The THD of the existing topology can be further decreased by using more
complex PWM methods like space vector modulation and hybrid modulation.
Validation of simulation results can be done using hardware setup for carrier based
PWM techniques. Initially, the higher power rates together with the improved power
quality have been the major market drive and trigger for research and development of

CONCLUSION MAY 2017
multilevel converters. However, the continuous development of technology and the
evolution of industrial applications will open new challenges and opportunities that
could motivate further improvements to multilevel converter technology.

REFERENCE MAY 2017
REFERENCES
[1] M. Farhadi Kangarlu and E. Babaei, “Cross-switched multilevel inverter:An
innovative topology,” IET Power Electron., vol. 6, no. 4, pp. 642–651,Apr. 2013.
[2] E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M. Tarafdar Haque, and M.
Sabahi, “Reduction of DC voltage sources and switches in asymmetrical
multilevel converters using a novel topology,” Elect. Power Syst. Res.,vol. 77, no.
8, pp. 1073–1085, Jun. 2007.
[3] Y. Hinago and H. Koizumi, “A single-phase multilevel inverter using switched
series/parallel dc voltage sources,” IEEE Trans. Ind. Electron.,vol. 57, no. 8, pp.
2643–2650, Aug. 2010.
[4] G. Waltrich and I. Barbi, “Three-phase cascaded multilevel inverter using
power cells with two inverter legs in series,” IEEE Trans. Ind. Appl.,vol. 57, no.
8, pp. 2605–2612, Aug. 2010.
[5] W. K. Choi and F. S. Kang, “H-bridge based multilevel inverter using PWM
switching function,” in Proc. INTELEC, 2009, pp. 1–5.
[6] E. Babaei, M. Farhadi Kangarlu, and F. Najaty Mazgar, “Symmetric and
asymmetric multilevel inverter topologies with reduced switching devices,” Elect.
Power Syst. Res., vol. 86, pp. 122–130, May 2012.
[7] E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M. Tarafdar Haque, and M.
Sabahi, “Reduction of DC voltage sources and switches in asymmetrical
multilevel converters using a novel topology,” Elect. Power Syst. Res.,vol. 77, no.
8, pp. 1073–1085, Jun. 2007.
[8] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new multilevel converter
topology with reduced number of power electronic components,”IEEE Trans. Ind.
Electron., vol. 59, no. 2, pp. 655–667, Feb. 2012

REFERENCE MAY 2017
[9] E. Babaei and S. H. Hosseini, “New cascaded multilevel inverter topology
with minimum number of switches,” Energy Convers. Manage., vol. 50,no. 11,
pp. 2761–2767, Nov. 2009
[10] Y. Hinago and H. Koizumi, “A single-phase multilevel inverter using
switched series/parallel dc voltage sources,” IEEE Trans. Ind. Electron., vol. 57,
no. 8, pp. 2643–2650, Aug. 2010.
[11] P. Satheesh Kumar, Dr. S. P. Natarajan,Dr. Alamelu Nachiappan and Dr. B.
Shanthi ,“Performance Evaluation of Nine Level Modified CHB Multilevel
Inverter for Various PWM Strategies,” International Journal of Modern
Engineering Research (IJMER), Vol. 3, Issue. 5, pp-2758-2766,Oct. 2013.
[12] Ebrahim Babaei, Somayeh Alilu, and Sara Laali,”A New General Topology
for Cascaded Multilevel Inverters With Reduced Number of Components Based
on Developed H-Bridge”, IEEE Trans. Ind. Electron., vol.61, Issue. 8, pp-3932-
3939,Aug.2013.

APPENDIX

K A78X X /K A78X X A
3-Terminal 1A Positive Voltage Regulator
Features
· Output Current up to 1A
· Output Voltages of 5, 6, 8, 9, 10, 12, 15, 18, 24V
· Thermal Overload Protection
· Short Circuit Protection
· Output Transistor Safe Operating Area Protection 
Internal Block Digram
Description
The KA78XX/KA78XXA series of three-terminal positive
regulator are available in the TO-220/D-PAK package and
with several fixed output voltages, making them useful in a
wide range of applications. Each type employs internal current
limiting, thermal shut down and safe operating area protection,
making it essentially indestructible. If adequate heat sinking is
provided, they can deliver over 1A output
current. Although designed primarily as fixed voltage
regulators, these devices can be used with external
components to obtain adjustable voltages and currents.

Absolute Maximum Ratings
Electrical Characteristics (KA7805/KA7805R)
(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =10V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Note:
1. Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions
KA7805
Unit
Min. Typ. Max.
Output Voltage VO
TJ =+25 oC 4.8 5.0 5.2
V5.0mA ≤ Io ≤ 1.0A, PO ≤ 15W
VI = 7V to 20V 4.75 5.0 5.25
Line Regulation (Note1) Regline TJ=+25 oC
VO = 7V to 25V - 4.0 100
mV
VI = 8V to 12V - 1.6 50
Load Regulation (Note1) Regload TJ=+25 oC
IO = 5.0mA to1.5A - 9 100
mV
IO =250mA to 750mA - 4 50
Quiescent Current IQ TJ =+25 oC - 5.0 8.0 mA
Quiescent Current Change ∆IQ
IO = 5mA to 1.0A - 0.03 0.5
mA
VI= 7V to 25V - 0.3 1.3
Output Voltage Drift ∆VO/∆T IO= 5mA - -0.8 - mV/ oC
Output Noise Voltage VN f = 10Hz to 100KHz, TA=+25 oC - 42 - µV/VO
Ripple Rejection RR
f = 120Hz
VO = 8V to 18V
62 73 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 oC - 2 - V
Output Resistance rO f = 1KHz - 15 - mΩ
Short Circuit Current ISC VI = 35V, TA =+25 oC - 230 - mA
Peak Current IPK TJ =+25 oC - 2.2 - A
Parameter Symbol Value Unit
Input Voltage (for VO = 5V to 18V)
(for VO = 24V)
VI VI 35
40
V
V
Thermal Resistance Junction-Cases (TO-220) RθJC 5 °C/W
Thermal Resistance Junction-Air (TO-220) RθJA 65 °C/W
Operating Temperature Range (KA78XX/A/R) TOPR 0 ~ +125 °C
Storage Temperature Range TSTG -65 ~ +150 °C

Note:
1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
KA7806
Unit
Min. Typ. Max.
Output Voltage VO
TJ =+25 oC 5.75 6.0 6.25
V5.0mA ≤ IO ≤ 1.0A, PO ≤ 15W
VI = 8.0V to 21V 5.7 6.0 6.3
Line Regulation (Note1) Regline TJ =+25 oC
VI = 8V to 25V - 5 120
mV
VI = 9V to 13V - 1.5 60
Load Regulation (Note1) Regload TJ =+25 oC
IO =5mA to 1.5A - 9 120
mV
IO =250mA to750mA - 3 60
IO = 5mA to 1A - - 0.5
mA
VI = 8V to 25V - - 1.3
Output Voltage Drift ∆VO/∆T IO = 5mA - -0.8 -
mV/
oC
Output Noise Voltage VN f = 10Hz to 100KHz, TA =+25 oC - 45 - µV/Vo
Ripple Rejection RR
f = 120Hz
VI = 9V to 19V
59 75 - dB
Short Circuit Current ISC VI= 35V, TA=+25 oC - 250 - mA

Note:
KA7808
Unit
Min. Typ. Max.
Output Voltage VO
TJ =+25 oC 7.7 8.0 8.3
V5.0mA ≤ IO ≤ 1.0A, PO ≤ 15W
VI = 10.5V to 23V 7.6 8.0 8.4
VI = 10.5V to 25V - 5.0 160
mV
VI = 11.5V to 17V - 2.0 80
IO = 5.0mA to 1.5A - 10 160
mVIO= 250mA to
750mA
- 5.0 80
IO = 5mA to 1.0A - 0.05 0.5
mA
VI = 10.5A to 25V - 0.5 1.0
Output Voltage Drift ∆VO/∆T IO = 5mA - -0.8 - mV/ oC
Ripple Rejection RR f = 120Hz, VI= 11.5V to 21.5V 56 73 - dB
Dropout Voltage VDrop IO = 1A, TJ=+25 oC - 2 - V
Short Circuit Current ISC VI= 35V, TA =+25 oC - 230 - mA

Note:
KA7809
Unit
Min. Typ. Max.
Output Voltage VO
TJ =+25 oC 8.65 9 9.35
V5.0mA≤ IO ≤1.0A, PO ≤15W
VI= 11.5V to 24V 8.6 9 9.4
Line Regulation (Note1) Regline TJ=+25 oC
VI = 11.5V to 25V - 6 180
mV
VI = 12V to 17V - 2 90
Load Regulation (Note1) Regload TJ=+25 oC
IO = 5mA to 1.5A - 12 180
mV
IO = 250mA to 750mA - 4 90
Quiescent Current IQ TJ=+25 oC - 5.0 8.0 mA
IO = 5mA to 1.0A - - 0.5
mA
VI = 11.5V to 26V - - 1.3
Output Voltage Drift ∆VO/∆T IO = 5mA - -1 - mV/ oC
Ripple Rejection
RR
f = 120Hz
VI = 13V to 23V
56 71 - dB
Peak Current IPK TJ= +25 oC - 2.2 - A

Electrical Characteristics (KA7810)
Note:
KA7810
Unit
Min. Typ. Max.
Output Voltage VO
TJ =+25 oC 9.6 10 10.4
V5.0mA ≤ IO ≤ 1.0A, PO ≤ 15W
VI = 12.5V to 25V 9.5 10 10.5
VI = 12.5V to 25V - 10 200
mV
VI = 13V to 25V - 3 100
IO = 5mA to 1.5A - 12 200
mV
IO = 250mA to 750mA - 4 400
IO = 5mA to 1.0A - - 0.5
mA
VI = 12.5V to 29V - - 1.0
Ripple Rejection RR
f = 120Hz
VI = 13V to 23V
56 71 - dB
Short Circuit Current ISC VI = 35V, TA=+25 oC - 250 - mA

Note:
KA7812/KA7812R
Unit
Min. Typ. Max.
Output Voltage VO
TJ =+25 oC 11.5 12 12.5
V
5.0mA ≤ IO≤1.0A, PO≤15W
VI = 14.5V to 27V 11.4 12 12.6
VI = 14.5V to 30V - 10 240
mV
VI = 16V to 22V - 3.0 120
IO = 5mA to 1.5A - 11 240
mV
IO = 250mA to 750mA - 5.0 120
IO = 5mA to 1.0A - 0.1 0.5
mA
VI = 14.5V to 30V - 0.5 1.0
Ripple Rejection RR
f = 120Hz
VI = 15V to 25V
55 71 - dB
Peak Current IPK TJ = +25 oC - 2.2 - A

Note:
KA7815
Unit
Min. Typ. Max.
Output Voltage VO
TJ =+25 oC 14.4 15 15.6
V5.0mA ≤ IO≤1.0A, PO≤15W
VI = 17.5V to 30V 14.25 15 15.75
VI = 17.5V to 30V - 11 300
mV
VI = 20V to 26V - 3 150
IO = 5mA to 1.5A - 12 300
mV
IO = 250mA to 750mA - 4 150
IO = 5mA to 1.0A - - 0.5
mA
VI = 17.5V to 30V - - 1.0
Ripple Rejection RR
f = 120Hz
VI = 18.5V to 28.5V
54 70 - dB

Note:
KA7818
Unit
Min. Typ. Max.
Output Voltage VO
TJ =+25 oC 17.3 18 18.7
V5.0mA ≤ IO ≤1.0A, PO ≤15W
VI = 21V to 33V 17.1 18 18.9
VI = 21V to 33V - 15 360
mV
VI = 24V to 30V - 5 180
IO = 5mA to 1.5A - 15 360
mV
IO = 250mA to 750mA - 5.0 180
IO = 5mA to 1.0A - - 0.5
mA
VI = 21V to 33V - - 1
Ripple Rejection RR
f = 120Hz
VI = 22V to 32V
53 69 - dB

Note:
KA7824
Unit
Min. Typ. Max.
Output Voltage VO
TJ =+25 oC 23 24 25
V5.0mA ≤ IO ≤ 1.0A, PO ≤ 15W
VI = 27V to 38V 22.8 24 25.25
VI = 27V to 38V - 17 480
mV
VI = 30V to 36V - 6 240
IO = 5mA to 1.5A - 15 480
mV
IO = 250mA to 750mA - 5.0 240
IO = 5mA to 1.0A - 0.1 0.5
mA
VI = 27V to 38V - 0.5 1
Output Voltage Drift ∆VO/∆T IO = 5mA - -1.5 -
mV/
oC
Ripple Rejection RR
f = 120Hz
VI = 28V to 38V
50 67 - dB

Electrical Characteristics (KA7805A)
(Refer to the test circuits. 0oC < TJ < +125 oC, Io =1A, V I = 10V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:
1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VO
TJ =+25 oC 4.9 5 5.1
VIO = 5mA to 1A, PO ≤ 15W
VI = 7.5V to 20V
4.8 5 5.2
Line Regulation (Note1)
Regline
VI = 7.5V to 25V
IO = 500mA
- 5 50
mVVI = 8V to 12V - 3 50
TJ =+25 oC
VI= 7.3V to 20V - 5 50
VI= 8V to 12V - 1.5 25
Load Regulation (Note1)
Regload
TJ =+25 oC
IO = 5mA to 1.5A
- 9 100
mV
IO = 5mA to 1A - 9 100
IO = 250mA to 750mA - 4 50
Quiescent Current
Change
∆IQ
IO = 5mA to 1A - - 0.5
mAVI = 8 V to 25V, IO = 500mA - - 0.8
VI = 7.5V to 20V, TJ =+25 oC - - 0.8
Output Voltage Drift ∆V/∆T Io = 5mA - -0.8 - mV/ oC
Output Noise Voltage VN
f = 10Hz to 100KHz
TA =+25 oC
- 10 - µV/Vo
Ripple Rejection RR
f = 120Hz, IO = 500mA
VI = 8V to 18V
- 68 - dB
Peak Current IPK TJ= +25 oC - 2.2 - A

Note:
Output Voltage VO
TJ =+25 oC 5.58 6 6.12
VI = 8.6V to 21V
5.76 6 6.24
Regline
VI= 8.6V to 25V
IO = 500mA
- 5 60
mVVI= 9V to 13V - 3 60
TJ =+25 oC
VI= 8.3V to 21V - 5 60
VI= 9V to 13V - 1.5 30
Regload
TJ =+25 oC
IO = 5mA to 1.5A
- 9 100
mV
IO = 5mA to 1A - 4 100
IO = 250mA to 750mA - 5.0 50
IO = 5mA to 1A - - 0.5
mAVI = 9V to 25V, IO = 500mA - - 0.8
VI= 8.5V to 21V, TJ =+25 oC - - 0.8
Output Voltage Drift ∆V/∆T IO = 5mA - -0.8 - mV/ oC
f = 10Hz to 100KHz
TA =+25 oC
- 10 - µV/Vo
Ripple Rejection RR
f = 120Hz, IO = 500mA
VI = 9V to 19V
- 65 - dB
Peak Current IPK TJ=+25 oC - 2.2 - A

Note:
Output Voltage VO
TJ =+25 oC 7.84 8 8.16
VIO = 5mA to 1A, PO ≤15W
VI = 10.6V to 23V
7.7 8 8.3
Regline
VI= 10.6V to 25V
IO = 500mA
- 6 80
mVVI= 11V to 17V - 3 80
TJ =+25 oC
VI= 10.4V to 23V - 6 80
VI= 11V to 17V - 2 40
Regload
TJ =+25 oC
IO = 5mA to 1.5A
- 12 100
mV
IO = 5mA to 1A - 12 100
IO = 250mA to 750mA - 5 50
IO = 5mA to 1A - - 0.5
mAVI = 11V to 25V, IO = 500mA - - 0.8
VI= 10.6V to 23V, TJ =+25 oC - - 0.8
Output Voltage Drift ∆V/∆T IO = 5mA - -0.8 - mV/ oC
f = 10Hz to 100KHz
TA =+25 oC
- 10 - µV/Vo
Ripple Rejection RR
f = 120Hz, IO = 500mA
VI = 11.5V to 21.5V
- 62 - dB
Peak Current IPK TJ=+25 oC - 2.2 - A

Note:
Output Voltage VO
TJ =+25°C 8.82 9.0 9.18
VIO = 5mA to 1A, PO≤15W
VI = 11.2V to 24V
8.65 9.0 9.35
Regline
VI= 11.7V to 25V
IO = 500mA
- 6 90
mVVI= 12.5V to 19V - 4 45
TJ =+25°C
VI= 11.5V to 24V - 6 90
VI= 12.5V to 19V - 2 45
Regload
TJ =+25°C
IO = 5mA to 1.0A
- 12 100
mV
IO = 5mA to 1.0A - 12 100
IO = 250mA to 750mA - 5 50
Quiescent Current IQ TJ =+25 °C - 5.0 6.0 mA
VI = 11.7V to 25V, TJ=+25 °C - - 0.8
mAVI = 12V to 25V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5
Output Voltage Drift ∆V/∆T IO = 5mA - -1.0 - mV/ °C
f = 10Hz to 100KHz
TA =+25 °C
- 10 - µV/Vo
Ripple Rejection RR
f = 120Hz, IO = 500mA
VI = 12V to 22V
- 62 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 °C - 2.0 - V
Short Circuit Current ISC VI= 35V, TA =+25 °C - 250 - mA
Peak Current IPK TJ=+25°C - 2.2 - A

Note:
Output Voltage VO
TJ =+25°C 9.8 10 10.2
VI =12.8V to 25V
9.6 10 10.4
Regline
VI= 12.8V to 26V
IO = 500mA
- 8 100
mVVI= 13V to 20V - 4 50
TJ =+25 °C
VI= 12.5V to 25V - 8 100
VI= 13V to 20V - 3 50
Regload
TJ =+25 °C
IO = 5mA to 1.5A
- 12 100
mV
IO = 5mA to 1.0A - 12 100
IO = 250mA to 750mA - 5 50
VI = 13V to 26V, TJ=+25 °C - - 0.5
mAVI = 12.8V to 25V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5
f = 10Hz to 100KHz
TA =+25 °C
- 10 - µV/Vo
Ripple Rejection RR
f = 120Hz, IO = 500mA
VI = 14V to 24V
- 62 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25°C - 2.0 - V
Peak Current IPK TJ=+25 °C - 2.2 - A

Note:
Output Voltage VO
TJ =+25 °C 11.75 12 12.25
VI = 14.8V to 27V
11.5 12 12.5
Regline
VI= 14.8V to 30V
IO = 500mA
- 10 120
mVVI= 16V to 22V - 4 120
TJ =+25 °C
VI= 14.5V to 27V - 10 120
VI= 16V to 22V - 3 60
Regload
TJ =+25 °C
IO = 5mA to 1.5A
- 12 100
mV
IO = 5mA to 1.0A - 12 100
IO = 250mA to 750mA - 5 50
Quiescent Current IQ TJ =+25°C - 5.1 6.0 mA
VI = 15V to 30V, TJ=+25 °C - 0.8
mAVI = 14V to 27V, IO = 500mA - 0.8
IO = 5mA to 1.0A - 0.5
Output Voltage Drift ∆V/∆T IO = 5mA - -1.0 - mV/°C
f = 10Hz to 100KHz
TA =+25°C
- 10 - µV/Vo
Ripple Rejection RR
f = 120Hz, IO = 500mA
VI = 14V to 24V
- 60 - dB

(Refer to the test circuits. 0oC < TJ < +125 oC, Io =1A, V I =23V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:
Output Voltage VO
TJ =+25 °C 14.7 15 15.3
VI = 17.7V to 30V
14.4 15 15.6
Regline
VI= 17.9V to 30V
IO = 500mA
- 10 150
mVVI= 20V to 26V - 5 150
TJ =+25°C
VI= 17.5V to 30V - 11 150
VI= 20V to 26V - 3 75
Regload
TJ =+25 °C
IO = 5mA to 1.5A
- 12 100
mV
IO = 5mA to 1.0A - 12 100
IO = 250mA to 750mA - 5 50
VI = 17.5V to 30V, TJ =+25 °C - - 0.8
mAVI = 17.5V to 30V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5
Output Voltage Drift ∆V/∆T IO = 5mA - -1.0 - mV/°C
f = 10Hz to 100KHz
TA =+25 °C
- 10 - µV/Vo
Ripple Rejection RR
f = 120Hz, IO = 500mA
VI = 18.5V to 28.5V
- 58 - dB
Peak Current IPK TJ=+25°C - 2.2 - A

Note:
Output Voltage VO
TJ =+25 °C 17.64 18 18.36
VI = 21V to 33V
17.3 18 18.7
Regline
VI= 21V to 33V
IO = 500mA
- 15 180
mVVI= 21V to 33V - 5 180
TJ =+25 °C
VI= 20.6V to 33V - 15 180
VI= 24V to 30V - 5 90
Regload
TJ =+25°C
IO = 5mA to 1.5A
- 15 100
mV
IO = 5mA to 1.0A - 15 100
IO = 250mA to 750mA - 7 50
VI = 21V to 33V, TJ=+25 °C - - 0.8
mAVI = 21V to 33V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5
f = 10Hz to 100KHz
TA =+25°C
- 10 - µV/Vo
Ripple Rejection RR
f = 120Hz, IO = 500mA
VI = 22V to 32V
- 57 - dB
Short Circuit Current ISC VI= 35V, TA =+25°C - 250 - mA

Note:
Output Voltage VO
TJ =+25 °C 23.5 24 24.5
VI = 27.3V to 38V
23 24 25
Regline
VI= 27V to 38V
IO = 500mA
- 18 240
mVVI= 21V to 33V - 6 240
TJ =+25 °C
VI= 26.7V to 38V - 18 240
VI= 30V to 36V - 6 120
Regload
TJ =+25 °C
IO = 5mA to 1.5A
- 15 100
mV
IO = 5mA to 1.0A - 15 100
IO = 250mA to 750mA - 7 50
VI = 27.3V to 38V, TJ =+25 °C - - 0.8
mAVI = 27.3V to 38V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5
f = 10Hz to 100KHz
TA = 25 °C
- 10 - µV/Vo
Ripple Rejection RR
f = 120Hz, IO = 500mA
VI = 28V to 38V
- 54 - dB

Typical Perfomance Characteristics
I
Figure 1. Quiescent Current Figure 2. Peak Output Current
Figure 3. Output Voltage Figure 4. Quiescent Current

Typical Applications
Input Output
Figure 5. DC Parameters
Input Output
Figure 6. Load Regulation
Input Output
Figure 7. Ripple Rejection
Input Output
Figure 8. Fixed Output Regulator

COMPARATIVE ANALYSIS OF SWITCHING STRATEGIES FOR HARMONIC MINIMIZATION

COMPARATIVE ANALYSIS OF SWITCHING STRATEGIES FOR HARMONIC MINIMIZATION

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