thesis presentation

1. REDUCTION OF GROUND BOUNCE
NOISE IN HIGH PERFORMANCE
STACKING POWERGATING CIRCUITS
Presenting by
R.Bhanuprakash
M.Tech VLSI - 09
Thesis Guides
Dr. Manisha Pattanaik Dr. S.S.Rajput

2. INTRODUCTION
• With the recent trend toward high performance portable system-on-a
chip for communication and computing, power dissipation has
become a critical design constraint .
• supply voltage scaling is the most effective way to reduce power
dissipation however this technique increases circuit delay which
leads to decreasing threshold voltage in order to maintain
performance.
• leakage current dramatically increases due to the exponential nature
of leakage current in the sub threshold regime of the transistor.
• Based on ITRS report[1], sub threshold leakage power dissipation in
standby mode of a chip may exceed dynamic power dissipation as
the feature size reduces..

3. POWER GATING TECHNIQUE
 Power gating technique is well
known technique for leakage
reduction in sleep mode.
 In Sleep mode virtual ground node
charge up close to VDD.
 While turning on in active mode
sleep transistor turns on in
saturation.
 Due to this technique causes for
ground bounce noise in mode
transition.

4. PREVIOUS TECHNIQUES

5. MOTIVATION
 As new trend toward NANO scale
regime need of improved power gating
techniques to reduce the leakage current
than conventional power gating structure .
 In sleep to active Mode transition causes
ground bounce noise which enormously
switch the wrong logic.

6. Stacking Power Gating
Technique
Stacking power Gating
structure Works on two
Strategies
1. Reduction of leakage
current by stacking
effect.
2. Reducing ground
bounce by controlling
the intermediate node
voltage

7. Reduction of leakage
1. By stacking effect
In sleep mode turning both M1 and M2 sleep transistors
OFF .This raises the intermediate node voltage VGN to
positive value. Positive potential at the intermediate
node has three effects:
Gate to source voltage of M1 (Vgs1) becomes negative;
Negative body-to–source potential (Vbs1) of M1 causes
more body effect;
Drain-to-source potential (Vds1) of M1 decreases,
resulting in less drain induced barrier lowering

8. Reducing ground bounce
Isolating the Ground for small duration during mode
transition.
Turning ON the M2 transistor in linear region instead of
saturation region to decrease current surge.
In two ways we can control the intermediate node VGN
By inserting proper amount of delay, that is less than the
discharging time of the M1 transistor.
By proper selection of capacitor C2 we can control there by
controlling intermediate node voltage .
By using the above mentioned ground bounce noise has
been reduced.

9. ANALYSIS OF STACKING
POWERGATE TECHNIQUE
Fig: Equivalent circuit at t=0+ Fig: Equivalent circuit at ∆T > t > 0

10. Minimum Wakeup Latency Condition
The delay which we are provided is directly
proportional to the wakeup latency .
The minimum wake up condition at the time
the M1 Transistor enter enters into linear
region from saturation

11. Minimum Ground Bounce
Condition
In staking power gate technique we are turning On the sleep transistors twice.
So we will get Ground bounce noise twice whenM1 is turned ON and M2 is
turned ON.
The peak of the ground bounce noise is depend on the voltage
that the individual capacitors C1 and C2 discharges in that short span of
duration when M1 and M2 transistors are ON.
By making the Both C1 and C2 discharging voltages equal we will get
minimum ground bounce noise.
i.e.
VC1(0) – VC1(∆T ) =VC2(∆T)

12. Simulation
1. Stacking power gate
technique has been simulated
NAND gate and its leakage
power and ground bounce
noise has been measured.
2. Simulation has been done in
Tanner Spice Version 13.0
Simulator using transistor
model of 90nm Technology
(Berkeley Predictive
Technology Model).
3. Stacking power gate
technique has been
compared with the
conventional power gating
structure.
Fig : Nand gate with Stacking power gate technique

13. Supply
Voltage(V)
Without
Power Gating
With
conventional
Power Gating
With stacking
Power Gating
0.5 0.611nA 0.097nA 0.0311nA
0.7 1.16nA 0.145nA 0.0343nA
0.9 2.29nA 0.197nA 0.0367nA
1.2 6.86nA 0.305nA 0.0392nA
1.5 22.5nA 0.763nA 0.0404nA
Leakage current
Comparisons

14. Ground bounce noise
• In stacking power
gate ground bounce
noise has been
reduced by 90.39%
over conventional
power gating
structure.
• The comparison
of two techniques
has done for
different supply
voltages ranging
from (0.5-1.5)V

15. Leakage power
Comparison
 By using the
stacking power
gating technique,
the leakage
power has been
reduced by
81.71% over
conventional
power gating
structure.

16. TRADE OFF BETWEEN WAKEUP
LATENCY AND GROUND BOUNCE NOISE

17. Future Work
 In stacking power gating technique
ground bounce reduction has been
achieved at the cost of wakeup latency
and future works will be directed towards
minimizing it.
 In sleep mode the problem of data
being not retained has to be resolved.

18. References
1. “International Technology Roadmap for Semiconductors,” Semiconductor
Industry Association, 2005. [Online]. Available: http://public.itrs.net
2. Suhwan Kim, Chang Jun Choi, Deog-Kyoon Jeong,Stephen V. Kosonocky, and
Sung Bae Park” Reducing Ground-Bounce Noise and Stabilizing the Data-
Retention Voltage of Power-Gating Structures” IEEE TRANSACTIONS ON
ELECTRON DEVICES, VOL. 55, NO. 1, JANUARY 2008
3. Suhwan Kim; Kosonocky, S.V.; Knebel, D.R.; Stawiasz, K., "Experimental
measurement of a novel power gating structure with intermediate power saving
mode," Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of
the 2004 International Symposium on, vol., no.pp. 20- 25, 9-11 Aug. 2004
4 Y. Chang, S. K. Gupta, and M. A. Breuer, “Analysis of ground bounce in deep
sub- micron circuits,” in Proceedings of 15th IEEE VLSI Test Symposium, pp.
110-116, 1997
5. Suhwan Kim; et. el. "Minimizing inductive noise in system-on-a chip with multiple
power gating structures," Solid-State Circuits Conference, 2003. ESSCIRC '03.
Proceedings of the 29th European, vol., no.pp. 635- 638, 16-18 Sept. 2003