A CAD Framework for FPGA-Based Systems
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This document presents a CAD framework for FPGA-based systems called CAOS. CAOS provides a web UI and flow manager backend for optimizing applications onto FPGAs. It uses architectural templates to map applications described as systems onto computational models. The document demonstrates CAOS with a demo application for convolutional filters in retinal vessel segmentation.
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A CAD Framework for FPGA-Based Systems
- 1. 1 A CAD FRAMEWORK FOR FPGA-BASED SYSTEMS luca.stornaiuolo@mail.polimi.it Microsoft 06/07/2017 Alberto Scolari, Anna Maria Nestorov, Emanuele Del Sozzo, Enrico Reggiani, Gianluca Durelli, Giuseppe Natale, Lorenzo Di Tucci, Luca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio NGCVIII 2017@SF
- 3. 3 Heterogeneous Complex Systems F1 Project Catapult
- 6. 6 CAOSWebUI CAOSFlowManager Backend Functions Optimization Frontend <system > … </system > System description Profiling datasets ______ __________ ___ ________ Application code (C, C++, OPENCL) ______ __________ ___ ________ ______ __________ ___ ________ 1110010110 1010101111 1111010101 0101010101 0101010101 0111111 FPGAs bitstreams ______ __________ ___ ________ System runtime ArchitecturalTemplates
- 7. 7 CAOSWebUI CAOSFlowManager Backend Functions Optimization Frontend <system > … </system > System description Profiling datasets ______ __________ ___ ________ Application code (C, C++, OPENCL) ______ __________ ___ ________ ______ __________ ___ ________ 1110010110 1010101111 1111010101 0101010101 0101010101 0111111 FPGAs bitstreams ______ __________ ___ ________ System runtime ArchitecturalTemplates Architectural Templates ( ) OpenCL Streaming … ( ) … Computation Model Technology SST
- 8. 8 CAOSWebUI CAOSFlowManager Backend Functions Optimization Frontend <system > … </system > System description Profiling datasets ______ __________ ___ ________ Application code (C, C++, OPENCL) ______ __________ ___ ________ ______ __________ ___ ________ 1110010110 1010101111 1111010101 0101010101 0101010101 0111111 FPGAs bitstreams ______ __________ ___ ________ System runtime ArchitecturalTemplates
- 9. 9 CAOSWebUI CAOSFlowManager Backend Functions Optimization Frontend <system > … </system > System description Profiling datasets ______ __________ ___ ________ Application code (C, C++, OPENCL) ______ __________ ___ ________ ______ __________ ___ ________ 1110010110 1010101111 1111010101 0101010101 0101010101 0111111 FPGAs bitstreams ______ __________ ___ ________ System runtime ArchitecturalTemplates
- 10. 10 CAOSWebUI CAOSFlowManager Backend Functions Optimization Frontend <system > … </system > System description Profiling datasets ______ __________ ___ ________ Application code (C, C++, OPENCL) ______ __________ ___ ________ ______ __________ ___ ________ 1110010110 1010101111 1111010101 0101010101 0101010101 0111111 FPGAs bitstreams ______ __________ ___ ________ System runtime ArchitecturalTemplates
- 11. 11 CAOSWebUI CAOSFlowManager Backend Functions Optimization Frontend <system > … </system > System description Profiling datasets ______ __________ ___ ________ Application code (C, C++, OPENCL) ______ __________ ___ ________ ______ __________ ___ ________ 1110010110 1010101111 1111010101 0101010101 0101010101 0111111 FPGAs bitstreams ______ __________ ___ ________ System runtime ArchitecturalTemplates SST MaxCompiler Output Generation
- 12. 12
- 13. 13 Demo Application Convolution filters for retinal vessels segmentation • The goals are: – to speed up the “hot” portion of Vessel – to show how CAOS can really help and ease porting
- 14. 14 Vessels Segmentation • Retinal vessels segmentation recognizes blood vessels from retinal images. • Vessel segmentation is essentially a convolution that slides a 2D matrix onto the matrix representing the image to process.
- 15. 15
Editor's Notes
- Nowadays, High performance processing systems are considering FPGA-based accelerators as a promising solution for several application fields, due to the high relative performance with respect to a low power consumption, however, the employment of such devices poses challenges due to the high level of complexity required to program them.
- Nowadays, High performance processing systems are considering FPGA-based accelerators as a promising solution for several application fields, due to the high relative performance with respect to a low power consumption, however, the employment of such devices poses challenges due to the high level of complexity required to program them.
- Nowadays, High performance processing systems are considering FPGA-based accelerators as a promising solution for several application fields, due to the high relative performance with respect to a low power consumption, however, the employment of such devices poses challenges due to the high level of complexity required to program them. Pendenza …
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.