© 2016 IBM Corporation
Welcome to the waitless world
1
Prepared by Nengkuan Tu1
POWER Processor Roadmap
POWER9P1, P2, PPC P3, RS64
Fma
RISC
Cache
Numerous
• Processors,
• Cache architecture
• Boxes
• OS
64 bit
MP
Office automation
(DB)
High speed
computing as low
cost of super
computer
Exploration
New Micro-
Architecture
New
Technology
POWER10
New
Features and
Functions
Future
Other than performance and scale up, additional focus can vary in different time.
Power4
Growth Consolidation Virtualization/Cloud
Power5, PPC970
1990 1997 2001 2004 2010 2014
64 bit to deal with the
growth of data size
beyond 4G.
MP to improve the
performance with
parallel computing.
Simplified
processors offering.
One for business,
one for engineering.
One processor
for all boxes
NUMA
to support
large systems
Hypervisor
Open/Accelerator
2020
Power6
MicroPartition
SMT2
Large Page
(64K and 16G page)
2007
DFP
VMX
HEA
Clock
speed
First NUMA
capable
processor to
support server
with up to 32
cores.
Hypervisor to
support LPAR.
SMT to better
utilize processor
resources.
Micropartition to
get smaller and
more LPARs.
Large page to
improve memory
performance
PPC970 for blade
server
Decimal
floating
point
support.
Vector
operation
HEA to
virtualize IO
devices.
Power7 Power8
2017
SMT4
AME
8core
Per chip
SMT8
12core
per chip
CAPI
NVLINK
(2016)
2018
AME to
solve the
most
common
problem in
virtualized
environmen
t: memory
shortage.
New applications like big data, IOT, neural
network, AI, etc. are usually distributed with
various HW and SW. No single company can
do it all.
Special purpose accelerator like GPU and
FPGA can significantly improve the
performance.
NVLINK and PCIe G4 can help the high
communication bandwidth needed among
GPU, FPGA, and CPU.
CAPI is a special kind of FPGA which was
originally implemented for Power8. Open
CAPI is supported for Power9 and any
processor that follows the protocols.

Evolution and roadmap ibm power_system_onepage

  • 1.
    © 2016 IBMCorporation Welcome to the waitless world 1 Prepared by Nengkuan Tu1 POWER Processor Roadmap POWER9P1, P2, PPC P3, RS64 Fma RISC Cache Numerous • Processors, • Cache architecture • Boxes • OS 64 bit MP Office automation (DB) High speed computing as low cost of super computer Exploration New Micro- Architecture New Technology POWER10 New Features and Functions Future Other than performance and scale up, additional focus can vary in different time. Power4 Growth Consolidation Virtualization/Cloud Power5, PPC970 1990 1997 2001 2004 2010 2014 64 bit to deal with the growth of data size beyond 4G. MP to improve the performance with parallel computing. Simplified processors offering. One for business, one for engineering. One processor for all boxes NUMA to support large systems Hypervisor Open/Accelerator 2020 Power6 MicroPartition SMT2 Large Page (64K and 16G page) 2007 DFP VMX HEA Clock speed First NUMA capable processor to support server with up to 32 cores. Hypervisor to support LPAR. SMT to better utilize processor resources. Micropartition to get smaller and more LPARs. Large page to improve memory performance PPC970 for blade server Decimal floating point support. Vector operation HEA to virtualize IO devices. Power7 Power8 2017 SMT4 AME 8core Per chip SMT8 12core per chip CAPI NVLINK (2016) 2018 AME to solve the most common problem in virtualized environmen t: memory shortage. New applications like big data, IOT, neural network, AI, etc. are usually distributed with various HW and SW. No single company can do it all. Special purpose accelerator like GPU and FPGA can significantly improve the performance. NVLINK and PCIe G4 can help the high communication bandwidth needed among GPU, FPGA, and CPU. CAPI is a special kind of FPGA which was originally implemented for Power8. Open CAPI is supported for Power9 and any processor that follows the protocols.