The document appears to be a lab manual describing various adder designs to be implemented and tested in Verilog, including ripple carry adders, carry lookahead adders, carry select adders, and carry skip adders. It provides Verilog code examples and test benches for 32-bit implementations of each adder type, as well as expected results for propagation delay, resource utilization, and output waveforms. The manual is meant to guide students through designing and analyzing the performance of different adder architectures.
This resume summarizes Cheah Yaw Wah's qualifications and work experience. He received a Bachelor's degree in Electrical and Electronics Engineering from the University of Lincoln in the UK and has over 15 years of experience in product testing and engineering roles. His most recent role is as a Senior Product and Test Engineer at Lumileds Malaysia, where he is responsible for supporting automotive product testing and reliability testing. Previously he worked as a Staff Engineer at Renesas Semiconductor, where he improved testing efficiency and yield.
The document discusses various topics related to software testing including:
1. It introduces different levels of testing in the software development lifecycle like component testing, integration testing, system testing and acceptance testing.
2. It discusses the importance of early test design and planning and its benefits like reducing costs and improving quality.
3. It provides examples of how not planning tests properly can increase costs due to bugs found late in the process, and outlines the typical costs involved in fixing bugs at different stages.
Alfred Chikuniciwa is seeking a position in industrial automation and process measurement. He has over 20 years of experience as an instrumentation and control technician. He holds qualifications including a National Diploma in Electronic Engineering and a National Certificate in Electrical Engineering. His most recent role was as a Senior Control and Instrumentation Technician at Colgate Palmolive where he implemented automation disaster recovery plans and ensured quality audit compliance. He has extensive skills in PLC programming, instrumentation calibration, and process control systems maintenance.
This document discusses various types of software testing performed at different stages of the software development lifecycle. It describes component testing, integration testing, system testing, and acceptance testing. Component testing involves testing individual program units in isolation. Integration testing combines components and tests their interactions, starting small and building up. System testing evaluates the integrated system against functional and non-functional requirements. Acceptance testing confirms the system meets stakeholder needs.
Ramachandra PC is seeking a dynamic job where he can gain and share knowledge. He has 1.6 years of experience in avionics testing and development using C/C++ and assembly languages. His skills include embedded software development, testing, requirements documentation, and working well in a team. He completed projects at DRDO involving digital flight control computers and air data computers. He has a BE in electronics and communication and is proficient in various programming languages, communication protocols, and IDE tools.
The Maestro framework implemented by the validation group at Cirrus Logic provides GUI-based test automation and management for mixed signal validation. It leads to a 66% reduction in testing time through a modular structure with configuration files, a MATLAB GUI, and reusable validation scripts. Key benefits include abstracted test development and execution, standardized methodologies, and a system for monitoring and logging test results.
Atif Farooq Bhatti has over 15 years of experience as a test engineer developing automated testing solutions for RF products. He has a Master's degree in Electronics and is proficient in languages like C/C++, LabVIEW, and Visual Basic. He has worked on testing projects for water meters, network devices, and UPS systems. His skills include requirements documentation, test automation, data analysis, and reducing production costs.
The document appears to be a lab manual describing various adder designs to be implemented and tested in Verilog, including ripple carry adders, carry lookahead adders, carry select adders, and carry skip adders. It provides Verilog code examples and test benches for 32-bit implementations of each adder type, as well as expected results for propagation delay, resource utilization, and output waveforms. The manual is meant to guide students through designing and analyzing the performance of different adder architectures.
This resume summarizes Cheah Yaw Wah's qualifications and work experience. He received a Bachelor's degree in Electrical and Electronics Engineering from the University of Lincoln in the UK and has over 15 years of experience in product testing and engineering roles. His most recent role is as a Senior Product and Test Engineer at Lumileds Malaysia, where he is responsible for supporting automotive product testing and reliability testing. Previously he worked as a Staff Engineer at Renesas Semiconductor, where he improved testing efficiency and yield.
The document discusses various topics related to software testing including:
1. It introduces different levels of testing in the software development lifecycle like component testing, integration testing, system testing and acceptance testing.
2. It discusses the importance of early test design and planning and its benefits like reducing costs and improving quality.
3. It provides examples of how not planning tests properly can increase costs due to bugs found late in the process, and outlines the typical costs involved in fixing bugs at different stages.
Alfred Chikuniciwa is seeking a position in industrial automation and process measurement. He has over 20 years of experience as an instrumentation and control technician. He holds qualifications including a National Diploma in Electronic Engineering and a National Certificate in Electrical Engineering. His most recent role was as a Senior Control and Instrumentation Technician at Colgate Palmolive where he implemented automation disaster recovery plans and ensured quality audit compliance. He has extensive skills in PLC programming, instrumentation calibration, and process control systems maintenance.
This document discusses various types of software testing performed at different stages of the software development lifecycle. It describes component testing, integration testing, system testing, and acceptance testing. Component testing involves testing individual program units in isolation. Integration testing combines components and tests their interactions, starting small and building up. System testing evaluates the integrated system against functional and non-functional requirements. Acceptance testing confirms the system meets stakeholder needs.
Ramachandra PC is seeking a dynamic job where he can gain and share knowledge. He has 1.6 years of experience in avionics testing and development using C/C++ and assembly languages. His skills include embedded software development, testing, requirements documentation, and working well in a team. He completed projects at DRDO involving digital flight control computers and air data computers. He has a BE in electronics and communication and is proficient in various programming languages, communication protocols, and IDE tools.
The Maestro framework implemented by the validation group at Cirrus Logic provides GUI-based test automation and management for mixed signal validation. It leads to a 66% reduction in testing time through a modular structure with configuration files, a MATLAB GUI, and reusable validation scripts. Key benefits include abstracted test development and execution, standardized methodologies, and a system for monitoring and logging test results.
Atif Farooq Bhatti has over 15 years of experience as a test engineer developing automated testing solutions for RF products. He has a Master's degree in Electronics and is proficient in languages like C/C++, LabVIEW, and Visual Basic. He has worked on testing projects for water meters, network devices, and UPS systems. His skills include requirements documentation, test automation, data analysis, and reducing production costs.
IRJET- A Testbed for Real Time Water Level Control SystemIRJET Journal
The document describes the design and development of a testbed for real-time water level control system. The testbed is intended to provide engineering students a platform to test process control algorithms before implementation. It uses an algorithmic state machine approach where the state transition table is converted to a ROM structure. The hardware components include a microcontroller, ADC, timer and driver circuits. The design calculations and subsystem design are also outlined. The conclusions state that the low-cost testbed will enable practical learning of process control and help improve engineering education.
This document discusses various techniques for estimating software project costs, schedules, and sizes. It covers function point analysis, lines of code estimation, productivity models like COCOMO, and probabilistic techniques like PERT estimation. Key approaches mentioned include analogies, decomposition, mathematical models, mean schedule dates, and probability distributions.
The document presents a comparative analysis of different fault injection methods using on-chip debug (OCD) infrastructures. It describes experiments conducted using a Freescale MPC-565 microprocessor with enhanced OCD capabilities. The experiments compare basic, extended, and OCD-enhanced fault injection configurations across offline and real-time scenarios. Results show that the OCD-enhanced method enables higher fault detection rates with lower performance overhead compared to other approaches.
The document discusses building human-based software estimation models that are accurate, intuitive, and easy to understand. It presents an approach using correlation and scale factors between estimated and actual effort. Experiments on a dataset of 178 samples show that combining correlation and scale factors into a decision tree achieves up to 93.3% accuracy. The resulting model bridges expert and algorithmic estimation methods.
ATreVEE IN: Using Natural Interaction in Procedure Simulator for Training in ...Tatiana Tavares
The document discusses adding natural interaction to ATreVEE3D, a procedure simulator for training in the electricity sector. It integrated the Leap Motion device to allow natural hand gestures. An evaluation compared the user experience of ATreVEE3D using a mouse to ATreVEE IN using Leap Motion. Users found ATreVEE IN improved realism, engagement and the simulation tool, though navigation was easier with a mouse. The integration of Leap Motion in critical sector simulators and comparisons between devices were concluded to provide insights.
The document describes the assembly and programming of an autonomous line following robot to avoid obstacles. It includes:
1. Objectives to assemble the robotic kit using a Texas Instruments MSP430G2553 microcontroller and program it for line following and obstacle avoidance. Components used include sensors, motors, and the IAR compiler.
2. Project execution was divided into hardware development, software development, and testing of line following, obstacle avoidance, and integrated functions. The schedule planned was impacted by changes to critical assumptions.
3. Hardware was developed by modifying the SAM board to integrate with the MSP430G2553 and using tools and materials like the Launchpad board.
4. Software was programmed using
Vyshnavi CV has over 3 years of experience in embedded systems testing using C, ADA, and UNIX. She has a Bachelor's Degree in Electronics and Communication Engineering from Channabasaveshwara Institute of Technology with 83.5%. Currently she works as a Software Engineer for DRDO at Aeronautical Development Establishment, where her responsibilities include coding, testing, and debugging software for flight control systems. In her spare time she enjoys mehendi, drawing, listening to music and watching movies.
This document provides a resume for Ruchi Mishra, an experienced QA professional with over 8 years of experience in software testing. Key skills include testing using manual, database, ETL, automation and performance testing tools. She has experience in various domains including airline, travel, insurance, retail and life sciences. Strengths include ISTQB certification, proficiency with tools like QTP, Quality Center and databases like Oracle and SQL Server. Recent projects include testing data integration and analytics dashboards for retail and transportation clients.
This document contains instructions for a final examination in an introduction to software engineering course. It provides the date, time, location of the exam, as well as instructions that students are to write their name, student ID, and signature on the cover and top of the exam. It also states that the exam is closed book and notes, calculators are permitted, and to circle one answer for multiple choice questions. The exam contains two sections - a multiple choice section and an essay question section where students should write their answers in a separate booklet.
The document is a Test & Evaluation Master Plan (TEMP) for the Expeditionary Fighting Vehicle (EFV) that outlines the integrated test program and resources needed to test and evaluate the EFV system. Key points include:
- The EFV is an amphibious assault vehicle being developed for the US Marine Corps to deploy troops from ships to shore under hostile conditions.
- The test program includes developmental testing to verify requirements are met and operational testing to validate performance. Multiple live fire, terrain, and maritime tests are planned over several years.
- Resources needed for testing include prototype vehicles, test sites with various terrain types, live fire ranges, Navy assets, and trained Marine Corps personnel. Facilities from H
The document discusses principles of software testing including why testing is necessary, common testing terminology, and the testing process. It describes the testing process as having six key steps: 1) planning, 2) specification, 3) execution, 4) recording, 5) checking completion, and 6) planning at a more detailed level. It emphasizes prioritizing tests to address highest risks and outlines factors that influence how much testing is needed such as contractual requirements, industry standards, and risk levels.
Software Outsourcing and New Model of Test Estimation for Agile Development Masud Parvez
- Over 40-60% of IT development projects are outsourced, and this percentage is increasing each year.
- 50-70% of companies experience projects that exceed time and budget estimates by over 80% and deliver less than 70% of required functionality when outsourcing projects.
- A new model was developed that incorporates efficiency and risk factors to more accurately estimate test effort for outsourced software projects compared to traditional use case point methods. The model was demonstrated on a sample project.
Stil test pattern generation enhancement in mixed signal designConference Papers
This document describes a process for generating STIL test patterns from mixed signal design simulations in order to test digital blocks on an SoC. It involves simulating the mixed signal design, sampling the waveforms to generate test vectors, and converting those vectors into an ATPG-compliant STIL format using an automation program. This was implemented successfully at MIMOS Berhad, generating STIL test patterns that passed 100% of stuck-at tests.
Nowadays, CPU microarchitecture is concealed from developers by compilers, VMs, etc.
Do Java developers need to know microarchitecture details of modern processors?
Or, does it like to learn quantum mechanics for cooking?
Are Java developers safe from leaking low-level microarchitecture details into high level application performance behaviour?
We will try to answer these questions by analyzing several Java examples.
Cyclomatic complexity is a software metric used to measure the complexity of a program based on the number of linearly independent paths. It is calculated as the number of edges - nodes + 2 in the program's control flow graph. Higher cyclomatic complexity indicates a more complex program that is likely more error-prone. Testing seeks to determine the required quality standard and strategy before planning specific unit, integration, and system tests. Factors considered in test planning include prioritizing what to test based on damage severity and risk levels, determining test sources, who will perform the tests, where to conduct them, and when to terminate testing. The results are documented in a software test plan.
This document is a preface to a laboratory manual for a Digital Communication Systems course. It discusses the importance of practical, hands-on learning to develop industry-relevant skills. Each practical exercise is designed to help students achieve predetermined outcomes through developing procedures and safety precautions. The course aims to enable students to apply concepts of digital communication to troubleshoot and maintain real-world systems. While efforts were made to eliminate errors, feedback is welcome to improve the manual.
Crude-Oil Scheduling Technology: moving from simulation to optimizationBrenno Menezes
Scheduling technology either commercial or homegrown in today’s crude-oil refining industries relies on a complex simulation of scenarios where the user is solely responsible for making many different decisions manually in the search for feasible solutions over some limited time-horizon i.e., trial-and-error heuristics. As a normal outcome, schedulers abandon these solutions and then return to their simpler spreadsheet simulators due to: (i) time-consuming efforts to configure and manage numerous scheduling scenarios, and (ii) requirements of updating premises and situations that are constantly changing. Moving to solutions based in optimization rather than simulation, the lecture describes the future steps in the refactoring of the scheduling technology in PETROBRAS considering in separate the graphic user interface (GUI) and data communication developments (non-modeling related), and the modeling and process engineering related in an automated decision-making with built-in problem representation facilities and integrated data handling features among other techniques in a smart scheduling frontline.
Rohith Kumar C has over 5 years of experience in testing electrical and electronic equipment for safety and reliability. He currently works as a Test Engineer at Electronics Test and Development Centre testing equipment according to Indian and international standards. His expertise includes safety testing, environmental simulation testing, and laboratory management. Rohith holds an M.Tech in Computer Application in Industrial Drives and a B.E. in Electronics and Communication Engineering.
This document provides information about a lab manual for a Microcontrollers course. It includes:
1) An index listing 12 experiments covering assembly programming of 8051 microcontrollers and interfacing programs, along with MSP430 programming.
2) Syllabus details for the course outlining topics like data transfer, arithmetic, logic instructions, counters and interfacing modules.
3) Instructions for students on lab protocols and expectations.
4) Table of contents organizing the experiments and programs by topic and page numbers.
5) An introduction section describing 8051 architecture features and Keil μVision tools for programming.
FPGA BASED IMPLEMENTATION OF DELAY OPTIMISED DOUBLE PRECISION IEEE FLOATING-P...Somsubhra Ghosh
This document summarizes an algorithm for implementing a double precision floating point adder according to the IEEE 754 standard. The algorithm uses several optimization techniques to reduce latency, including separating the computation into two parallel paths based on the operands and operation, reducing the number of IEEE rounding modes, using a sign-magnitude representation for subtraction, and performing prefix addition of the significands. Analysis using the logical effort model estimates the delay of this optimized design is 30.6 FO4 delays, an improvement over prior designs.
This slide is special for master students (MIBS & MIFB) in UUM. Also useful for readers who are interested in the topic of contemporary Islamic banking.
More Related Content
Similar to DSP Spring 2023 Lab Manual for spring 2023
IRJET- A Testbed for Real Time Water Level Control SystemIRJET Journal
The document describes the design and development of a testbed for real-time water level control system. The testbed is intended to provide engineering students a platform to test process control algorithms before implementation. It uses an algorithmic state machine approach where the state transition table is converted to a ROM structure. The hardware components include a microcontroller, ADC, timer and driver circuits. The design calculations and subsystem design are also outlined. The conclusions state that the low-cost testbed will enable practical learning of process control and help improve engineering education.
This document discusses various techniques for estimating software project costs, schedules, and sizes. It covers function point analysis, lines of code estimation, productivity models like COCOMO, and probabilistic techniques like PERT estimation. Key approaches mentioned include analogies, decomposition, mathematical models, mean schedule dates, and probability distributions.
The document presents a comparative analysis of different fault injection methods using on-chip debug (OCD) infrastructures. It describes experiments conducted using a Freescale MPC-565 microprocessor with enhanced OCD capabilities. The experiments compare basic, extended, and OCD-enhanced fault injection configurations across offline and real-time scenarios. Results show that the OCD-enhanced method enables higher fault detection rates with lower performance overhead compared to other approaches.
The document discusses building human-based software estimation models that are accurate, intuitive, and easy to understand. It presents an approach using correlation and scale factors between estimated and actual effort. Experiments on a dataset of 178 samples show that combining correlation and scale factors into a decision tree achieves up to 93.3% accuracy. The resulting model bridges expert and algorithmic estimation methods.
ATreVEE IN: Using Natural Interaction in Procedure Simulator for Training in ...Tatiana Tavares
The document discusses adding natural interaction to ATreVEE3D, a procedure simulator for training in the electricity sector. It integrated the Leap Motion device to allow natural hand gestures. An evaluation compared the user experience of ATreVEE3D using a mouse to ATreVEE IN using Leap Motion. Users found ATreVEE IN improved realism, engagement and the simulation tool, though navigation was easier with a mouse. The integration of Leap Motion in critical sector simulators and comparisons between devices were concluded to provide insights.
The document describes the assembly and programming of an autonomous line following robot to avoid obstacles. It includes:
1. Objectives to assemble the robotic kit using a Texas Instruments MSP430G2553 microcontroller and program it for line following and obstacle avoidance. Components used include sensors, motors, and the IAR compiler.
2. Project execution was divided into hardware development, software development, and testing of line following, obstacle avoidance, and integrated functions. The schedule planned was impacted by changes to critical assumptions.
3. Hardware was developed by modifying the SAM board to integrate with the MSP430G2553 and using tools and materials like the Launchpad board.
4. Software was programmed using
Vyshnavi CV has over 3 years of experience in embedded systems testing using C, ADA, and UNIX. She has a Bachelor's Degree in Electronics and Communication Engineering from Channabasaveshwara Institute of Technology with 83.5%. Currently she works as a Software Engineer for DRDO at Aeronautical Development Establishment, where her responsibilities include coding, testing, and debugging software for flight control systems. In her spare time she enjoys mehendi, drawing, listening to music and watching movies.
This document provides a resume for Ruchi Mishra, an experienced QA professional with over 8 years of experience in software testing. Key skills include testing using manual, database, ETL, automation and performance testing tools. She has experience in various domains including airline, travel, insurance, retail and life sciences. Strengths include ISTQB certification, proficiency with tools like QTP, Quality Center and databases like Oracle and SQL Server. Recent projects include testing data integration and analytics dashboards for retail and transportation clients.
This document contains instructions for a final examination in an introduction to software engineering course. It provides the date, time, location of the exam, as well as instructions that students are to write their name, student ID, and signature on the cover and top of the exam. It also states that the exam is closed book and notes, calculators are permitted, and to circle one answer for multiple choice questions. The exam contains two sections - a multiple choice section and an essay question section where students should write their answers in a separate booklet.
The document is a Test & Evaluation Master Plan (TEMP) for the Expeditionary Fighting Vehicle (EFV) that outlines the integrated test program and resources needed to test and evaluate the EFV system. Key points include:
- The EFV is an amphibious assault vehicle being developed for the US Marine Corps to deploy troops from ships to shore under hostile conditions.
- The test program includes developmental testing to verify requirements are met and operational testing to validate performance. Multiple live fire, terrain, and maritime tests are planned over several years.
- Resources needed for testing include prototype vehicles, test sites with various terrain types, live fire ranges, Navy assets, and trained Marine Corps personnel. Facilities from H
The document discusses principles of software testing including why testing is necessary, common testing terminology, and the testing process. It describes the testing process as having six key steps: 1) planning, 2) specification, 3) execution, 4) recording, 5) checking completion, and 6) planning at a more detailed level. It emphasizes prioritizing tests to address highest risks and outlines factors that influence how much testing is needed such as contractual requirements, industry standards, and risk levels.
Software Outsourcing and New Model of Test Estimation for Agile Development Masud Parvez
- Over 40-60% of IT development projects are outsourced, and this percentage is increasing each year.
- 50-70% of companies experience projects that exceed time and budget estimates by over 80% and deliver less than 70% of required functionality when outsourcing projects.
- A new model was developed that incorporates efficiency and risk factors to more accurately estimate test effort for outsourced software projects compared to traditional use case point methods. The model was demonstrated on a sample project.
Stil test pattern generation enhancement in mixed signal designConference Papers
This document describes a process for generating STIL test patterns from mixed signal design simulations in order to test digital blocks on an SoC. It involves simulating the mixed signal design, sampling the waveforms to generate test vectors, and converting those vectors into an ATPG-compliant STIL format using an automation program. This was implemented successfully at MIMOS Berhad, generating STIL test patterns that passed 100% of stuck-at tests.
Nowadays, CPU microarchitecture is concealed from developers by compilers, VMs, etc.
Do Java developers need to know microarchitecture details of modern processors?
Or, does it like to learn quantum mechanics for cooking?
Are Java developers safe from leaking low-level microarchitecture details into high level application performance behaviour?
We will try to answer these questions by analyzing several Java examples.
Cyclomatic complexity is a software metric used to measure the complexity of a program based on the number of linearly independent paths. It is calculated as the number of edges - nodes + 2 in the program's control flow graph. Higher cyclomatic complexity indicates a more complex program that is likely more error-prone. Testing seeks to determine the required quality standard and strategy before planning specific unit, integration, and system tests. Factors considered in test planning include prioritizing what to test based on damage severity and risk levels, determining test sources, who will perform the tests, where to conduct them, and when to terminate testing. The results are documented in a software test plan.
This document is a preface to a laboratory manual for a Digital Communication Systems course. It discusses the importance of practical, hands-on learning to develop industry-relevant skills. Each practical exercise is designed to help students achieve predetermined outcomes through developing procedures and safety precautions. The course aims to enable students to apply concepts of digital communication to troubleshoot and maintain real-world systems. While efforts were made to eliminate errors, feedback is welcome to improve the manual.
Crude-Oil Scheduling Technology: moving from simulation to optimizationBrenno Menezes
Scheduling technology either commercial or homegrown in today’s crude-oil refining industries relies on a complex simulation of scenarios where the user is solely responsible for making many different decisions manually in the search for feasible solutions over some limited time-horizon i.e., trial-and-error heuristics. As a normal outcome, schedulers abandon these solutions and then return to their simpler spreadsheet simulators due to: (i) time-consuming efforts to configure and manage numerous scheduling scenarios, and (ii) requirements of updating premises and situations that are constantly changing. Moving to solutions based in optimization rather than simulation, the lecture describes the future steps in the refactoring of the scheduling technology in PETROBRAS considering in separate the graphic user interface (GUI) and data communication developments (non-modeling related), and the modeling and process engineering related in an automated decision-making with built-in problem representation facilities and integrated data handling features among other techniques in a smart scheduling frontline.
Rohith Kumar C has over 5 years of experience in testing electrical and electronic equipment for safety and reliability. He currently works as a Test Engineer at Electronics Test and Development Centre testing equipment according to Indian and international standards. His expertise includes safety testing, environmental simulation testing, and laboratory management. Rohith holds an M.Tech in Computer Application in Industrial Drives and a B.E. in Electronics and Communication Engineering.
This document provides information about a lab manual for a Microcontrollers course. It includes:
1) An index listing 12 experiments covering assembly programming of 8051 microcontrollers and interfacing programs, along with MSP430 programming.
2) Syllabus details for the course outlining topics like data transfer, arithmetic, logic instructions, counters and interfacing modules.
3) Instructions for students on lab protocols and expectations.
4) Table of contents organizing the experiments and programs by topic and page numbers.
5) An introduction section describing 8051 architecture features and Keil μVision tools for programming.
FPGA BASED IMPLEMENTATION OF DELAY OPTIMISED DOUBLE PRECISION IEEE FLOATING-P...Somsubhra Ghosh
This document summarizes an algorithm for implementing a double precision floating point adder according to the IEEE 754 standard. The algorithm uses several optimization techniques to reduce latency, including separating the computation into two parallel paths based on the operands and operation, reducing the number of IEEE rounding modes, using a sign-magnitude representation for subtraction, and performing prefix addition of the significands. Analysis using the logical effort model estimates the delay of this optimized design is 30.6 FO4 delays, an improvement over prior designs.
Similar to DSP Spring 2023 Lab Manual for spring 2023 (20)
This slide is special for master students (MIBS & MIFB) in UUM. Also useful for readers who are interested in the topic of contemporary Islamic banking.
Walmart Business+ and Spark Good for Nonprofits.pdfTechSoup
"Learn about all the ways Walmart supports nonprofit organizations.
You will hear from Liz Willett, the Head of Nonprofits, and hear about what Walmart is doing to help nonprofits, including Walmart Business and Spark Good. Walmart Business+ is a new offer for nonprofits that offers discounts and also streamlines nonprofits order and expense tracking, saving time and money.
The webinar may also give some examples on how nonprofits can best leverage Walmart Business+.
The event will cover the following::
Walmart Business + (https://business.walmart.com/plus) is a new shopping experience for nonprofits, schools, and local business customers that connects an exclusive online shopping experience to stores. Benefits include free delivery and shipping, a 'Spend Analytics” feature, special discounts, deals and tax-exempt shopping.
Special TechSoup offer for a free 180 days membership, and up to $150 in discounts on eligible orders.
Spark Good (walmart.com/sparkgood) is a charitable platform that enables nonprofits to receive donations directly from customers and associates.
Answers about how you can do more with Walmart!"
Strategies for Effective Upskilling is a presentation by Chinwendu Peace in a Your Skill Boost Masterclass organisation by the Excellence Foundation for South Sudan on 08th and 09th June 2024 from 1 PM to 3 PM on each day.
This presentation includes basic of PCOS their pathology and treatment and also Ayurveda correlation of PCOS and Ayurvedic line of treatment mentioned in classics.
Leveraging Generative AI to Drive Nonprofit InnovationTechSoup
In this webinar, participants learned how to utilize Generative AI to streamline operations and elevate member engagement. Amazon Web Service experts provided a customer specific use cases and dived into low/no-code tools that are quick and easy to deploy through Amazon Web Service (AWS.)
Chapter wise All Notes of First year Basic Civil Engineering.pptxDenish Jangid
Chapter wise All Notes of First year Basic Civil Engineering
Syllabus
Chapter-1
Introduction to objective, scope and outcome the subject
Chapter 2
Introduction: Scope and Specialization of Civil Engineering, Role of civil Engineer in Society, Impact of infrastructural development on economy of country.
Chapter 3
Surveying: Object Principles & Types of Surveying; Site Plans, Plans & Maps; Scales & Unit of different Measurements.
Linear Measurements: Instruments used. Linear Measurement by Tape, Ranging out Survey Lines and overcoming Obstructions; Measurements on sloping ground; Tape corrections, conventional symbols. Angular Measurements: Instruments used; Introduction to Compass Surveying, Bearings and Longitude & Latitude of a Line, Introduction to total station.
Levelling: Instrument used Object of levelling, Methods of levelling in brief, and Contour maps.
Chapter 4
Buildings: Selection of site for Buildings, Layout of Building Plan, Types of buildings, Plinth area, carpet area, floor space index, Introduction to building byelaws, concept of sun light & ventilation. Components of Buildings & their functions, Basic concept of R.C.C., Introduction to types of foundation
Chapter 5
Transportation: Introduction to Transportation Engineering; Traffic and Road Safety: Types and Characteristics of Various Modes of Transportation; Various Road Traffic Signs, Causes of Accidents and Road Safety Measures.
Chapter 6
Environmental Engineering: Environmental Pollution, Environmental Acts and Regulations, Functional Concepts of Ecology, Basics of Species, Biodiversity, Ecosystem, Hydrological Cycle; Chemical Cycles: Carbon, Nitrogen & Phosphorus; Energy Flow in Ecosystems.
Water Pollution: Water Quality standards, Introduction to Treatment & Disposal of Waste Water. Reuse and Saving of Water, Rain Water Harvesting. Solid Waste Management: Classification of Solid Waste, Collection, Transportation and Disposal of Solid. Recycling of Solid Waste: Energy Recovery, Sanitary Landfill, On-Site Sanitation. Air & Noise Pollution: Primary and Secondary air pollutants, Harmful effects of Air Pollution, Control of Air Pollution. . Noise Pollution Harmful Effects of noise pollution, control of noise pollution, Global warming & Climate Change, Ozone depletion, Greenhouse effect
Text Books:
1. Palancharmy, Basic Civil Engineering, McGraw Hill publishers.
2. Satheesh Gopi, Basic Civil Engineering, Pearson Publishers.
3. Ketki Rangwala Dalal, Essentials of Civil Engineering, Charotar Publishing House.
4. BCP, Surveying volume 1
What is Digital Literacy? A guest blog from Andy McLaughlin, University of Ab...
DSP Spring 2023 Lab Manual for spring 2023
1. SSUET/QR/113
Digital Signal Processing (EE-322L) Lab Manual
Electronic Laboratory Manual
Digital Signal Processing (EE-322L)
6th Semester Electronic Engineering
Electronic Engineering Department
Sir Syed University of Engineering and Technology
University Road Karachi - 75300
http://www.ssuet.edu.pk
2. Digital Signal Processing (EE-322L) Lab Manual
Sir Syed University of Engineering & Technology, Karachi
Electronic Engineering Department
Rubric Guideline for Software Based Lab
Digital Signal Processing (EE-322L), 6th
Semester, Batch 2020
SSUET/QR/118
(Form IIa)
Name of Student: Roll No.
Criteria Exceeds Expectations
(>=90%)
Meets Expectations
(70%-89%)
Developing
(50%-69%)
Unsatisfactory
(<50%)
Software
Handling
Able to use software
with its standard and
advanced features
without assistance
Able to use software
with its standard and
advanced features with
minimal assistance
Able to use
software with its
standard features
with assistance
Unable to use the
software
Programming/
Simulation
Able to program/
simulate the lab tasks
with simplification
Able to program/
simulate the lab tasks
without errors
Able to program/
simulate lab tasks
with errors
Unable to
program/simulate
Results
Able to achieve all the
desired results with
alternate ways
Able to achieve all the
desired results
Able to achieve
most of the
desired results
with errors
Unable to
achieve the
desired results
Laboratory
Manual
Laboratory manual has
no grammatical and/ or
spelling errors.
All sections of the
report are very well
written and technically
accurate.
Laboratory manual has
very few grammatical/
spelling errors.
All sections of the
report are technically
accurate.
Laboratory manual
has multiple
grammatical/
spelling errors.
Few sections of the
report contains
technical errors.
Laboratory
manual has
several
grammatical/
spelling errors
and sentence
construction is
poor.
3. Digital Signal Processing (EE-322L) Lab Manual
Sir Syed University of Engineering & Technology, Karachi
Electronic Engineering Department
Rubric-Laboratory Manual
Digital Signal Processing (EE-322L), 6th
Semester, Batch 2020
Name of Student: Roll No.________
Lab Description & Score
1.
Review of MATLAB fundamentals and display the output of basic commands.
Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
2.
To construct & observe the effects of sampling on continuous time signals display the output.
Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
3.
Construct the aliasing effect of two signals. Measure the effects of Quantization
Lab Report
( )/1
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
4.
Record, observe and display the output of waves by using Audio processing technique and perform various tasks.
Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
5.
Assemble the equation of DFT and IDFT and measure different parameters.
Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
6.
Implement and organize the DFT butterfly method on Simulink and verify the results by solving equations
Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
7.
OPEN ENDED
Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
8.
Perform Z transforms and measure poles, zeros to check the stability of a system.
Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
9.
Implement z- transform on a continuous signal
Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
10.
Get familiar with basic commands of video processing and measure parameters.
Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
11. Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
12. Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
13. Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
14. Software Handling
( )/2
Programming/ Simulations
( )/5
Results
( )/2
Lab Report
( )/1
Score
( )/10
TOTAL SCORE
Overall Score: out of ___ Examined by:
(Obtained Score / Total Score) x scale (Name and Signature of concerned lab instructor)
4. Digital Signal Processing (EE-322L) Lab Manual
SSUET/QR/118
(Form Ia)
Sir Syed University of Engineering & Technology, Karachi
Electronic Engineering Department
Rubric Guideline for Hardware Based Lab
Digital Signal Processing (EE-322L), 6th
Semester, Batch 2020
Name of Student______________________________________ Roll No. _____________
Criteria Exceeds Expectations
(>=90%)
Meets Expectations
(70%-89%)
Developing
(50%-69%)
Unsatisfactory
(<50%)
Experimental
Setup
Able to setup experiment
independently with
complete understanding
of each step
Able to setup
experiment
independently with
adequate
understanding of
each step
Can setup major part
of the experiment
with assistance
Can’t set up the
experiment even
with assistance
Procedure
Able to follow the
procedure completely
with simplification or
develop alternate
procedure
Able to follow the
procedure
completely
Able to follow major
part of the procedure
with errors or
omissions
Unable to follow
the procedure
Experimental
Results
Able to achieve all the
desired results with
alternate ways to
improve measurements
Able to achieve all
the desired results
Able to achieve
most of the desired
results with errors
Unable to achieve
the desired results
Safety
Extremely alert to
practice safety measures
in laboratory procedures
Fairly alert to practice
safety measures in
laboratory
procedures
Rarely alert to
practice safety
measures in
laboratory
procedures
Poorly alert about
safety measures in
laboratory
procedures
Laboratory
Manual
Laboratory manual has
no grammatical and/ or
spelling errors.
All sections of the
report are very well
written and technically
accurate.
Laboratory manual
has very few
grammatical/
spelling errors.
All sections of the
report are technically
accurate.
Laboratory manual
has multiple
grammatical/
spelling errors.
Few sections of the
report contain
technical errors.
Laboratory manual
has several
grammatical/
spelling errors and
sentence
construction is
poor. All sections
of the report
contains multiple
technical errors.
6. Digital Signal Processing (EE-322L) Lab Manual
SSUET/QR/118
(Form IIIa)
Sir Syed University of Engineering & Technology, Karachi
Electronic Engineering Department
Rubric for Subject Project
Digital Signal Processing (EE-322L), 6th
Semester, Batch 2020
Name of Student: Roll No.
Criteria Exceeds
Expectations
(>=90%)
Meets Expectations
(70%-89%)
Developing (50%-
69%)
Unsatisfactory
(<50%)
Score
Obtained
Project
Demonstration
06 Marks
Able to demonstrate
the project with
achievement of
required objectives
having clear
understanding of
project limitations
and future
enhancements.
Hardware and/or
Software modules
are fully
functional, if
applicable.
Able to demonstrate
the project with
achievement of
required objectives
but understanding of
project limitations
and future
enhancements is
insufficient.
Hardware and/or
Software modules
are functional, if
applicable.
Able to demonstrate
the project with
achievement of a*t
least 50% required
objectives and
insufficient
understanding of
project limitations
and future
enhancements.
Hardware and/or
Software modules
are partially
functional, if
applicable.
Able to
demonstrate the
project with
achievement of
less than 50%
required
objectives and
lacks in
understanding of
project limitations
and future
enhancements.
Hardware and/or
Software modules
are not functional,
if applicable.
Project results
04 Marks
Able to achieve all
the desired results
with alternate ways
to improve
measurements
Able to achieve all
the desired results
Able to achieve most
of the desired results
with errors
Unable to achieve
the desired results
Project Report
03 Marks
Project report has
no grammatical
and/ or spelling
errors. All sections
of the report are
very well- written
and technically
accurate.
Project report
has very few
grammatical/
spelling errors.
All sections of the
report are
technically accurate.
Project report has
multiple
grammatical/
spelling errors.
Few sections of the
report contain
technical errors.
Project report has
several
grammatical/
spelling errors and
sentence
construction is
poor.
Viva
02 Marks
Able to answer
the questions
easily and
correctly across
the project.
Able to answer the
questions related
to the project
Able to answer the
questions but with
mistakes
Unable to answer
the questions
Total Marks (Out of 15)
7. Digital Signal Processing (EE-322L) Lab Manual
SSUET/QR/118
(Form IIIb)
Sir Syed University of Engineering & Technology, Karachi
Electronic Engineering Department
Rubric for Lab Exam
Digital Signal Processing (EE-322L), 6th
Semester, Batch 2020
Name of Student: Roll No.
Criteria Exceeds
Expectations
(>=90%)
Meets Expectations
(70%-89%)
Developing
(50%-69%)
Unsatisfactory
(<50%)
Score
Obtained
Performance
15 Marks Able to present full
knowledge of both
problem and solution.
Able to present
adequate knowledge of
both problem and
solution
Able to present sufficient
knowledge of both
problem and solution
No or very less
knowledge of
both problem
and solution
Viva
05 Marks Able to answer the
questions easily and
correctly
Able to answer the
questions
Able to answer the
questions but with
mistakes
Unable to
answer the
questions
Total Marks (Out of 20)
Final Lab Assessment
Assessment Tool CLO-1 (Marks) CLO-2 (Marks) CLO-3 (10)
Lab Manual ______/ 10 ______/05 xxx
Subject Project / Viva xxx ______/10 ______/05
Lab Exam / Viva ______/ 10 ______/05 ______/05
Score Obtained ______/ 20 ______/ 20 ______/ 10
Total Score: ________ out of 50
Examined by:
(Name and Signature of concerned lab instructor)
8. Digital Signal Processing (EE-322L) Lab Manual
Digital Signal Processing
Table of Contents
Lab No. List of Experiments CLO # PLO # Page
No.
1 Review of MATLAB fundamentals and display the output
of basic commands.
CLO - 1 PLO-3 01
2
To construct & observe the effects of sampling on
continuous time signals display the output.
CLO - 1 PLO-3 06
3(a)
Construct the aliasing effect of two signals.
CLO – 1 PLO-3 11
3(b) Measure the effects Of Quantization On Discrete
Time Continuous Signals
CLO – 1 PLO-3 15
4 Record, observe and display the output of waves by
using Audio processing technique and perform various
tasks.
CLO - 1 PLO-3 19
5 Assemble the equation of DFT and IDFT and measure
different parameters.
CLO – 1 PLO-3 23
6. Implement and organize the DFT butterfly method on
Simulink and verify the results by solving equations
CLO – 1 PLO-3 26
7 OPEN ENDED CLO – 1 PLO-3 29
8
Perform Z transforms and measure poles, zeros to check
the stability of a system. CLO – 1 PLO-3 30
9
Implement z- transform on a continuous signal and display
the transfer function in a discrete time sampled signal.
Compute partial fraction into rational z transform.
CLO - 1 PLO-3 34
10 Get familiar with basic commands of video processing and
measure parameters. Import any video from library and
apply basic commands on it and display
CLO – 1 PLO-3 39
11 Perform Various Tasks using DSK C6416t Processor and
related CCS Software tool
CLO – 2 PLO-3 46
9. Digital Signal Processing (EE-322L) Lab Manual
12 Produce Sine Wave Using Eight Points with DIP Switch
Control of TSMC DSP Kit
CLO – 2 PLO-3 56
13 Design FIR and IIR Filter using interference of Code
Composer Studio (CCS) software tool with TSMC DSP Kit
CLO – 2 PLO-3 68
14
OPEN ENDED LAB
CLO –1
and 2
PLO-3 70
10. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 1
Laboratory Exercise 1
REVIEW OF MATLAB FUNDAMENTALS
OBJECTIVE: Display the results of following tasks:
1. Review of basic commands in MATLAB.
2. Investigate the difference between different mathematical operations.
3. Generate complex-valued matrix
4. Implementation of function.
5. Review of Simulink.
THEORY:
In this course we will use software MATLAB to implement and simulate digital signal processing
algorithms.
The name MATLAB stands for MATrix LABoratory. Originally MATLAB was developed to deal with
only one single but universal data type: the matrix.
A matrix is defined by
● Its associated name
● The number of rows
● The number of columns
● The value of all matrix elements
The matrix data type includes vectors, for the case when either of the number of rows or the number of
column equals to 1; and it includes scalars when both the number of rows and columns equal 1.
Furthermore, matrices can be either real‐valued or complex valued, which is the most general case.
There is a small tutorial in this exercise for newcomer to become familiar with the MATLAB fundamentals.
It is recommended to try out introduced methods while solving the described tasks.
How to get Help?
There are several methods in MATLAB to access texts, which explain the usage and behavior of
givenfunctions:
● The HELP command is the basic help feature to get help of a function. For example, to get help
on the SUM function, type at the command prompt:
help sum
● HELPWIN is used in the same manner as help, but it opens a separate window withadvance search
facilities and links to related topics.
● HELPDESK uses a window of an installed web browser to display the help texts.
● If the name of a command is not exactly known, the LOOKFOR function helps by seeking through
the first comment line of all available functions and listing all functions where a desired expression
is found.
11. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 2
Statement, Expressions and Variables:
MATLAB is an expression language. The expressions you type are interpreted and evaluated. MATLAB
statements are usually of the form
variable = expression, or simply
expression
Expressions are usually composed from operators, functions and variable names. Evaluation of the
expression produces a matrix, which is then displayed on the screen and assigned to the variable for future
use.
A statement is normally terminated with the carriage return. However, a statement can be continued to the
next line with three or more periods followed by a carriage return. On the other hand, several statements
can be placed on a single line if separated by commas or semicolon.
The variable ANS:
If the variable name and = sign are omitted, a variable ANS (for answer) is automatically created to which
the result is assigned.
Suppressing Screen Output:
If the last character of a statement is a semicolon, the printing is suppressed, but the assignment is carried
out. This is essential in suppressing unwanted printing of intermediate results.
Colon Notation:
Colon notation is used to generate vectors, and reference submatrices, known as subscripting. Creative
use of this feature makes MATLAB programming code simple, readable and minimizes the use of loop,
which slows MATLAB.
● An index vector is created by using the colon notation
first : last
For example, [1:5] creates the vector [12345]
● An spacing can be introduced between two elements of a vector by using the colon notation
first : spacing : last
For example, [1: 2 : 5] creates the vector [1 3 5].
Workspace:
The contents of all the variables are stored in the MATLAB workspace. This is the memory region allocated
for variable.
● The command WHO lists all variable which currently exist in the workspace.
● WHOS additionally lists the size and amount of allocated memory.
● The entire workspace or single variable can be cleared by using the CLEAR command.
Elementary Operations:
Algebraic expressions can be formed by the following basic operations:
● Transpose of a vector/matrix can be produced by .*
12. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 3
e.g. B.*
● + is used to add two vectors/matrices of identical size, or a vector/matrix and a scalar, e.g.
[3 2; 4 5] + [7 4; 9 6]
● ‐ subtracts two vectors/matrices of identical size, or a vector/matrix and a scalar, e.g.
2-B
● .* performs element‐wise multiplication of two vectors/matrices of identical size, or a vector/matrix
and a scalar. For example, to square all elements of B, we may write
B.*B
● ./ performs element‐wise division of two vectors/matrices of identical size, or a vector/matrix
and a scalar. For example, the reciprocal of all elements in B is computed through
1./B
● * performs vector/matrix multiplication. The number of columns in the first vector/matrix
must equal to the number of rows in the second. Example:
B * B
Real and Complex Matrices:
In general, any matrix within the MATLAB can be complex‐valued. However, for efficient storage,
MATLAB distinguishes between real‐valued and complex‐valued matrices. Real valued matrices are
matrices where the imaginary parts of all matrix elements are zero. The following essentials must be known
to deal with complex‐valued matrices:
● The variables i and j are assigned, by default, the value i= √ −1. This is used to definethe complex
values. For example,
5 + j * 10
generates a complex‐valued variable.
● The real part of a complex‐valued matrix can be extracted by using the function REAL and
imaginary part can be extracted by using the function IMAG. Both functions deliver the real‐valued
matrices as outputs.
● The function CONJ is used to produce the complex conjugate of a matrix.
● The special character ’ generates the complex conjugate transpose of a matrix, the hermitian matrix.
This character is written after an expression or variable.
For example, the hermitian of a matrix A can be obtained through: A'
M-Files:
MATLAB can execute a sequence of statements stored in a file. Such files are called M‐files because they
have “.m” extension as the last part of their file name.There are two types of M‐types:
● Script files
● Function files
Script File:
In a script file, script is a sequence of commands as they could be entered at the prompt. The script allows
to execute the entire sequence multiple times in a comfortable way, or to test modified versions.
13. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 4
Function File:
In a function file, function has the additional feature of passing parameters. On calling a function, it may
read input arguments and after execution it may return output values. The “FUNCTION” command
specifies the input and output parameters of a function. It must be veryfirst command in a function file.
Only comment may be written before the FUNCTION command. Any text after a % sign inside an m‐file
is comment.
Flow Control:
In MATLAB flow control means that a program may not only be executed straight down from top to bottom
but with branches and repetitions.
● The FOR function allows to create a loop which is controlled by a counter.
● More general exit conditions can be implemented in a WHILE loop.
● The IF command allows for conditional programming, together with ELSE.
● All these commands come along with an END command which acts as a closing brace, together
with the opening brace, i.e. the introducing FOR, WHILE or IF command.
14. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 5
EXERCISE:
Task # 1: Try all help methods to get help of any function.
Task # 2: (a) Assign 10 samples, from 0 to 9, of time to the vector t.
(b) Assign a vector of samples without assigning it to a variable.
(c)Assign 10 samples, from 0 to 9, of time to any vector without printing it to screen.
Task # 3: Investigate the difference between multiplication*and element‐wise multiplication.* of
vectors/matrices.
Task # 4: Assemble a complex‐valued matrix
a = ones (1,10)+i* (1 : 10)
and calculate the absolute square of all elements of this matrix.
Task # 5: Implement a function
[x]=sinewave(t)
Which produces a sine wave of 1001 samples with spacing of ∆t= 1ms and construct the output.
Task # 6: Use MATLAB help to get familiar with the syntax of FOR, WHILE and IF‐ELSE statement.
Task#7:
(a): Using Simulink, plot a sine wave between t=0s and t=10s.
(b): Using Simulink, plot a sine wave between t=0s and t=100s
Task#8: Using Simulink, construct a Unit step Signal between t=0s and t=10s.
Task#9: Implement the following continuous‐time system with a Simulink model:
y(t) = 0.2x(t) +0.8x(t ‐2)‐0.4x(t ‐5)
Simulate the system between t=0s and t=10s with the following inputs:
a) x(t) = u(t) (Unit step)
b) x(t) = 2.5 sin(2*pi*f*t)
15. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 6
Laboratory Exercise 2
EFFECTS OF SAMPLING ON ANALOG SIGNALS
OBJECTIVE:
1. To construct & observe the effects of sampling on continuous time signals.
2. Conversion of continuous time signal to discrete time signal and display the output.
3. Observe the effects of sampling theorem on discrete time signals by changing their sampling
frequencies.
THEORY:
Most signals of practical interest, such as speech, biological signals, seismic signals, radar signals, sonar
signals, and various communications signals such as audio and video signals, are analog. To process analog
signals by digital means, it is first necessary to convert them into digital form, that is, to convert them to a
sequence of numbers having finite precision. This procedure is called analog‐to‐digital (A/D) conversion,
and the corresponding devices are called A/Dconverters (ADCs)
Conceptually, we view A/D conversion as a three step process. This process is illustrated in figure 2.1.
Sampling:
This is the conversion of a continuous time signal to a discrete time signal obtained by taking “samples” of
continuous time signal at discrete time instants. Thus, if xa(t) is the input to the sampler, the output is
xa(nT)≡x(n), where T is called the sampling interval.
Quantization:
This is the conversion of discrete time continuous valued signal into a discrete time discrete valued (digital)
signal. The value of each signal sample is represented by a value selected from a finite set of possible
values. The difference between the unquantized sample x(n) and the quantized output xq(n) is called the
quantized error.
Coding:
In the coding process, each discrete value xq(n) is represented by a b‐bit binary sequence.
16. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 7
Figure 2.1: Basic parts of an analog‐to‐digital (A/D) converter.
There are many ways to sample an analog signal. We limit our discussion to periodic or uniform sampling,
which is the type of sampling used most often in practice. This is described by the relation
x( n)=xa(n), −∞ <n< ∞
Where x(n) is the discrete time signal obtained by “taking samples” of the analog signal xa
seconds. This procedure is illustrated in figure 2.2. The time interval T between successive samples is
called the sampling period or sample interval and its reciprocal 1/T=Fsis called the sampling rate (samples
per second) or the sampling frequency (hertz).
Figure 2.2: Periodic sampling of an analog signal
Periodic sampling establishes a relationship between the time variables t and n of continuous time and
discrete time signals respectively. Indeed, these variables are linearly related through the sampling period
T or, equivalently, through the sampling rate Fs= 1/T, as
t = nT =
𝑛
𝐹𝑠
There exists a relationship between the variables F (or Ω) for analog signals and the frequency variable ƒ
(or ω) for discrete time signals. To establish this relationship, consider an analog sinusoidal signal of the
form
17. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 8
xa (t) = A cos(2πFt +θ )
Which, when sampled periodically at a rate Fs =1/T samples per second, yields
xa (nT)≡ x(n) = A cos(2πFnT +θ )
The frequency variables F and ƒ are linearly related as
(2.1)
Or, equivalently, as
ω = Ω T (2.2)
The relation in (2.1) justifies the name relative or normalized frequency, which is sometimes used to
describe the frequency variable f. As (2.1) implies, we can use f to determine the frequency F in hertz only
if the sampling frequency Fs is known.
The range of frequency variable F or Ω for continuous time sinusoids is
−∞ < 𝐹 < ∞
−∞ < 𝛺 < ∞ (2.3)
However, the situation is different for discrete time sinusoids.
−1
2
< 𝑓 <
1
2
−𝜋 < 𝜔 < 𝜋 (2.4)
By substituting from (2.1) and (2.2) into (2.4), we find that the frequency of the continuous time sinusoid
when sampled at a rate Fs=1/T must fall in the range
−
1
2𝑇
= −
𝐹𝑠
2
≤ 𝐹 ≤
𝐹𝑠
2
=
1
2𝑇
(2.5)
Or, equivalently,
18. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 9
−
𝜋
𝑇
= −𝜋𝐹𝑠 ≤ 𝛺 ≤ 𝜋𝐹𝑠 =
𝜋
𝑇
(2.6)
From these relations we observe that the fundamental difference between the continuous time and discrete
time signals is in their range of values of the frequency variables F and f, or Ω and 𝜔. Periodic sampling
of a continuous time signal implies a mapping of the infinite frequency range for the variable F (or Ω) into
a finite frequency range for the variable f (or 𝜔). Since the highest frequency in a discrete time signal is
𝜔= π or f = 1/2, it follows that, with a sampling rate Fs, the corresponding highest value of F and Ω
are
19. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 10
EXERCISE:
Task#1: Write a script to construct a continuous time sinusoid signal with amplitude=2 for a time t and
take the frequency as a user input by using input command.
Task#2: Write a script to construct continuous time signalof task #1 to a discrete time signal and take the
analog frequency as input. Sampling frequency should be less than twice of analog signal
frequency in Hertz.
Task#3: Write a script to construct continuous time signal of task#1 to a discrete time signal and take the
analog frequency as input. Sampling frequency should be equal to twice of analog signal frequency
in Hertz.
Task#4: Write a script to constructcontinuous time signal of task#1 to a discrete time signal and take the
analog frequency as input. Sampling frequency should be greater than twice of analog signal
frequency in Hertz.
Task#5: Write a script using subplot command to construct task #1, task#2, task#3 and task#4plots.
Analyze the four plots, what happens by increasing the sampling frequency?
Task#6: Consider the analog signal
xa(t)= 3 cos(100πt )
(i) Measure the minimum sampling rate required to avoid aliasing.
(ii) Suppose that the signal is sampled at the rate Fs=200 Hz. What is the discrete time signal
obtained after sampling? Plot the discrete‐time signal.
(iii) Suppose that the signal is sampled at the rate Fs=75 Hz. What is the discrete time signal
obtained after sampling? Plot the discrete‐time signal.
20. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 11
Laboratory Exercise 3(a)
ALIASING EFFECT IN ANALOG SIGNALS
OBJECTIVE: To measure the values of following tasks:
1. Plot two continuous-time signals of 10 Hz and 110 Hz.
2. Sample at Fs = 100 Hz.
3. Analyze the effect of aliasing by plotting both signals in discrete form.
4. Plot discrete-time signal with different frequencies and analyze the similarities and differences.
THEORY:
We only sample the signal at intervals. We don't know what happened between the samples. A crude
example is to consider a 'glitch' that happened to fall between adjacent samples. Since we don't measure it,
we have no way of knowing the glitch was there at all.
Figure 4.1: Basic view of sampling theorem
In a less obvious case, we might have signal components that are varying rapidly in between samples.
Again, we could not track these rapid inter‐sample variations. We must sample fast enough to see the most
rapid changes in the signal. Sometimes we may have some a priori knowledge of the signal, or be able to
make some assumptions about how the signal behaves in between samples. If we do not sample fast enough,
we cannot track completely the most rapid changes in the signal. Some higher frequencies can be incorrectly
interpreted as lower ones as shown in figure 4.2 below:
21. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 12
Figure 4.2: Overlapping of High frequency signal into Low frequency signal (fs ≤ 2 fm)
In the fig 4.2, the high frequency signal is sampled just under twice every cycle. The result is that each
sample is taken at a slightly later part of the cycle. If we draw a smooth connecting line between the
samples, the resulting curve looks like a lower frequency. This is called 'aliasing' because one frequency
looks like another.
Note that the problem of aliasing is that we cannot tell which frequency we have ‐ a high frequency looks
like a low one so we cannot tell the two apart. But sometimes we may have some a priori knowledge of the
signal, or be able to make some assumptions about how the signal behaves in between samples, that will
allow us to tell unambiguously what we have.
Nyquist showed that to distinguish unambiguously between the signal frequencies we must sample faster
than twice the frequency of the highest frequency component.
Figure 4.3: Reconstruction of signal with (fs = 2fm)
22. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 13
In the diagram, the high frequency signal is sampled twice every cycle. If we draw a smooth connecting
line between the samples, the resulting curve looks like the original signal. But if the samples happened to
fall at the zero crossings, we would see no signal at all ‐this is why the sampling theorem demands we
sample faster than twice the highest signal frequency as it will avoids aliasing.
The highest signal frequency allowed for a given sample rate is called the Nyquist frequency. Actually,
Nyquist says that we have to sample faster than the signal bandwidth, not the highest frequency. But this
leads us into multirate signal processing which is a more advanced subject. Nyquist showed that to
distinguish unambiguously between all signal frequencies we must sample at least twice the frequency of
the highest frequency component.
23. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 14
EXERCISE:
ALIASING EFFECT IN ANALOG SIGNALS
Task #1: Construct two CT signals of 10 Hz and 110 Hz for 0 < t < 0.2 secs. Sample at Fs = 100 Hz and
display them in discrete form.
Task #2 For a C.T signal x=sin(2πft)
a) Plot the signal x(n) for n=0 to 99 for f=[500 2000 3000 4500] sampled at fs=5000hz.
b) Suppose that f=2khz& fs=50khz.
(i) Plot the signal x(n).
(ii) Plot the signal x(n) created by even number samples of x(n)
24. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 15
Laboratory Exercise 3(b)
EFFECTS OF QUANTIZATION ON DISCRETE TIME CONTINUOUS
SIGNALS
OBJECTIVE:
● Simulate a discrete-time continuous sinusoid signal with length of the signal be 500.
● Choose the significant digits for round-off and apply to the signal above.
● Display error signals and SQNR.
● Now choose significant digits for truncation for the same signal given above.
● Measure the difference between round-off and truncation.
THEORY:
Digital signal is a sequence of numbers (samples) in which each number denotes a finite number having
finite precision.
The process of converting a discrete time continuous valued (DTCV) signal into a discrete time discrete
valued (DTDV) signal is known as Quantization. In this process each sample expresses a value as finite
(rather than infinite) number. The error introduced in representing the continuous valued signal by a finite
set of discrete value levels is called Quantization error or Quantization noise.
We express the quantizer operation on the sampled signal x(n) as Q[x(n)] and the quantized signal can be
expressed as xq(n) which denotes the sequence of quantized samples at the quantizer output. Hence
xq (n) = Q [x (n)]
The quantization error is a sequence eq(n) defined as the difference between the quantized value and the
actual sample value. Thus
eq (n) = xq (n) – x (n)
It is obvious that the signal cannot be processed by using calculator or digital computer since only the first
few samples can be stored and manipulated. For example, most calculators process number with only eight
significant digits.
We assume that we want to use only one significant digit. To eliminate the excess digit we either simply
discard them (truncation) or discard them by rounding the resulting number (rounding). The resulting
quantized signals xq(n) are shown by the numerical illustrations in the Table 5.1 as below:
25. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 16
Table 5.1: Error Computation and Analysis
The values allowed in the digital signal are called the quantization levels whereas the distance ∆
between two successive quantization levels is called quantization step size or resolution. The
rounding quantizer assigns each sample of x (n) to the nearest quantization level. In contrast, a
quantizer that performs truncation would have assigned each sample of x(n) to the quantization level
below it.
The quantization error eq (n) in rounding is limited to the range of -∆/2 to ∆/2, that is;
-∆/2 ≤ eq(n) ≤ ∆/2
The instantaneous quantization error cannot exceed half of the quantization step.
If xmin and xmax represent the minimum and maximum values of x (n) and L is the number of quantization
levels, then
The dynamic range of the signal is Xmax‐Xmin. In our example we have Xmax = 1, Xmin = 0, and L = 11,
which leads to ∆ = 0.1. Note that if the dynamic range is fixed, increasing the number of quantization levels
L results in a decrease of the quantization step size, thus the quantization error decreases and the accuracy
of the quantizer increases. In practice, we can reduce the quantization error to an insignificant amount by
choosing a sufficient number of quantization levels.
SQNR (Signal to Quantization Ratio)
26. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 17
The ‘quality’ of the quantized signal is measured by the signal‐to‐quantization noise ratio (SQNR) which
is mathematically written as:
Where, Px and Pq are the average powers of the DTCV and quantized signals respectively, and may be
written as:
And,
27. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 18
EFFECTS OF QUANTIZATION ON DISCRETE TIME CONTINUOUS
SIGNALS
EXERCISE:
Task #1:Differentiate between round off and truncation and also use MATLAB help to get familiar with
the syntax of both methods.
Task #2: Simulate a discrete time continuous valued (DTCV) sinusoid of 1/50 cycles/sample with length
of the signal to be 500& choose the no. of significant digits for round‐off and apply to the signal
generated above. Compute the error signals and SQNR.
Task #3: For F = 1/50 and length of the signal to be 200, write a program to quantize the signal x (n), using
Truncation. Also increase number of levels by increasing amplitude of the signal. Plot the signals x (n), xq
(n) and eq (n) and also compute the corresponding SQNR.
Task #4: Use round off method by using for loop and take significant digits as input i.e. 1, 2 &3.
In each case plot the signals x (n), xq (n) and eq (n) and also compute the corresponding SQNR.
28. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 19
Laboratory Exercise 4
AUDIO PROCESSING USING MATLAB
OBJECTIVE: Record, observe and display the output of waves and perform following:
● To record the audio clip and apply different operations on it.
● Analyze the effect on audio by changing the sampling frequency.
● Read different wav files and analyze their spectrums.
● Make Simulink models for recording or reading wav files.
THEORY:
To execute audio files using MATLAB commands and to observe a human generated audio signal on time
scope through Simulink
Audio signals, much like images, can under o filtering. It is somewhat easier to understand the impact of
signal processing on audio, since audio needs not be translated from a spatial to a frequency domain. To
load a wave (PCM) audio file, Matlab provides the function wavread.
funky = wavread('funky.wav');
It's important to capture the sampling frequency at which the sound was recorded; otherwise the speed of
playback and result s of further processing is not guaranteed to be correct:
[funky, f] = wavread( 'funky.wav');
To play a wave file at sampling frequency f:
wavplay( funky, f);
To view the waveform, plot the wave. Since audio is represented with many thousand samples per second,
it may be required to plot small portions of the waveform at a time.
11.1 SPECTROGRAM
Two‐dimensional plots of audio waves can be used to easily identify magnitude; however, combined
frequency distributions and magnitudes are more easily viewed in a spectrogram:
specgram (funky, 512 , f);
where 512 is the number of samples that are used for the discrete Fourier Transform, and thus a grouping
factor of samples per column in the spectrogram image
29. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 20
Figure 11.1: Spectrogram
HUMAN GENERATED AUDIO SIGNAL
The blocks used to generate a human voice in Simulink are;
Unbuffer (DSP Block set):
Convert a frame to scalar samples output at a higher sample rate.
From Wave device ( DSPBlockset):
Reads audio data samples from a standard Windows audio device in real time.Previously, only for
Win95/98/NT. Now MATLAB versions support up till Windows 7 (64 bit editions included)
To Wave file (DSP Blockset):
Writes audio data samples to a standard Windows PCM format ".WAV" audio file.Previously, only for
Win95/98/NT. Now MATLAB versions support up till Windows 7 (64 bit editions included).
Time Scope (DSP Blockset):
Provides real time monitoring of the output signal.
30. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 21
Figure 11.2: Simulink blockset for human generated audio signal
Figure 11.3: Time-
scope view of
human generated
audio signal
31. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 22
EXERCISE
Task #1: Write a MATLAB script to accomplish the following tasks:
a. Record your utterance of "we" and play it.
b. Record your utterance of "you" and play it.
Task #2: Write a MATLAB script that can read the wav file and display the following information:
a. Number of sample points.
b. Sampling rate.
c. Bit resolution
d. Time duration of the recording (in terms of seconds)
Task #3: Write a MATLAB script to read any file. Try to explain the playback effect you observe after you
try the following operations on the audio signals.
a. Multiply the audio signals by -1.
b. Reverse the audio signal
c. Multiply the audio signals by 10.
d. Take the square root of the signal.
Task #4:
i) Write a MATLAB script to record your utterance with a sample rate of 32 KHz and 8-bit
resolution. Try to resample the audio signals at decreasing sample rates of 16 KHz, 8 KHz, 4
KHz, 2 KHz, 1 KHz, and so on. At which sample rate you start to have difficulty in
understanding the contents of the utterance?
ii) Write a MATLAB script to record your utterance with a sample rate of 32 KHz and 8-bit
resolution. Try to resample the audio signals at increasing sample rates. At which sample rate
you start to have difficulty in understanding the contents of the utterance?
Task #5: Write a MATLAB code to read any wav file and generate its spectrum.
Task #6: Record 5 sec of 16 bit audio sampled at 11025 & play it.
32. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 23
Laboratory Exercise 5
DISCRETE FOURIER TRANSFORM
OBJECTIVE: Assemble equations of DFT and measure the following:
● Different data sequences given in this lab to compute the DFT.
● Plot magnitude and phase graphs and analyze the results.
● Computation of IDFT.
● Design DFT algorithm on MATLAB.
THEORY:
The discrete Fourier transform (DFT) is one of the specific forms of Fourier analysis. It transforms one
function into another, which is called the frequency domain representation, or simply the DFT, of the
original function (which is often a function in the time domain). But the DFT requires an input function
that is discrete and whose non-zero values have a limited (finite) duration. Such inputs are often created by
sampling a continuous function, like a person's voice. And unlike the discrete-time Fourier transform
(DTFT), it only evaluates enough frequency components to reconstruct the finite segment that was
analyzed. Its inverse transform cannot reproduce the entire time domain, unless the input happens to be
periodic (forever). Therefore it is often said that the DFT is a transform for Fourier analysis of finite-domain
discrete-time functions. The sinusoidal basis functions of the decomposition have the same properties.
Since the input function is a finite sequence of real or complex numbers, the DFT is ideal for processing
information stored in computers. In particular, the DFT is widely employed in signal processing and related
fields to analyze the frequencies contained in a sampled signal, to solve partial differential equations, and
to perform other operations such as convolutions. The DFT can be computed efficiently in practice using a
fast Fourier transform (FFT) algorithm.
The sequence of N complex numbers x0, ..., xN−1 is transformed into the sequence of N complex numbers
X0, ..., XN−1 by the DFT according to the formula:
Where is a primitive Nth root of unity.
The transform is sometimes denoted by the symbol, as in
33. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 24
Inverse Discrete Fourier Transform
The inverse discrete Fourier transform (IDFT) is given by
A simple description of these equations is that the complex numbers Xk represent the amplitude and phase
of the different sinusoidal components of the input "signal" Xn. The DFT computes the Xk from the Xn,
while the IDFT shows how to compute the Xn as a sum of sinusoidal components
with frequency k/N cycles per sample.
In Matlab we can find DFT by using following commands
FFT Discrete Fourier transform.
FFT(X) is the discrete Fourier transform (DFT) of vector X. For matrices, the FFT operation is
applied toeach column. For N-D arrays, the FFT operation operates on the first non-singleton
dimension.
FFT(X,N) is the N-point FFT, padded with zeros if X has less than N points and truncated if it has
more. FFT(X,[],DIM) or FFT(X,N,DIM) applies the FFT operation across the dimension DIM.
For length N input vector x, the DFT is a length N vector X, with elements
N
X(k) =sum x(n)*exp(-j*2*pi*(k-1)*(n-1)/N), 1 ≤ k ≤ N.
n=1
The inverse DFT (computed by IFFT) is given by
N
x(n) = (1/N) sum X(k)*exp( j*2*pi*(k-1)*(n-1)/N), 1 ≤ n ≤ N.
k=1
EXERCISE:
34. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 25
Task #1: Data sequence is given as follows:
xn = {1 0 0 1}
Compute by hand the DFT function Xk.
Task #2: Use FFT command to compute the DFT function for the given data sequence in Task #1.
Task #3: Construct the magnitude and phase graphs of DFT function of Task #2 in separate window.
Task #4: Plot an
sequence. Where a=0.8 and define at n=0 to 35. Find its DFT, plot its magnitude and
phase graphs also.
Task #5: Take IDFT of the results of Task #2 and verify that it gives you the same sequence as mention
in Task #1.
Task #6: Given three sinusoids.
x1(t)=5Cos(1000*pi*t),
x2(t)=5Cos(2400*pi*t+0.25*pi),
x3(t)=5Cos(3600*pi*t+0.5*pi)
a) Create a matlab program to sample each sinusoid & generate a sum of three sinusoids using
fs=8000Hz.Plot the sum x(n) over n=0:0.01:1
b) Compute DFT coefficients & plot phase and magnitude.
Task #7: Prove parseval’s theorem for given data sequence
x(n)=[5 0 -3 4].
Task #8: Prove linearity property when
a1=0.8, a2=0.1, x1(n)=(1/4)n
, x2(n)=Cos((3*pi*n)/8), -1<n<16.
35. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 26
Laboratory Exercise 6
DFT BUTTERFLY METHOD ON SIMULINK
OBJECT: Implement and organize the following:
● Implement 4-point butterfly diagram by Decimation in time method
● Implement Inverse Fourier Transform
● Implement 8-point Butterfly diagram by decimation in time and decimation in frequency method.
● Verify the results by implementing coding on M-file.
THEORY:
In the context of fast Fourier transform algorithms, a butterfly is a portion of the computation that combines the
results of smaller discrete Fourier transforms (DFTs) into a larger DFT, or vice versa (breaking a larger DFT up
into subtransforms). The name "butterfly" comes from the shape of the data-flow diagram in the radix-2 case, as
described in the diagram. The same structure can also be found in the Viterbi algorithm, used for finding the
most likely sequence of hidden states.
Most commonly, the term "butterfly" appears in the context of the Cooley–Tukey FFT algorithm,
which recursively breaks down a DFT of composite size n = rm into r smaller transforms of size m where r is
the "radix" of the transform. These smaller DFTs are then combined via size-r butterflies, which themselves are
DFTs of size r (performed m times on corresponding outputs of the sub-transforms) pre-multiplied by roots of
unity (known as twiddle factors). (This is the "decimation in time" case; one can also perform the steps in reverse,
known as "decimation in frequency", where the butterflies come first and are post-multiplied by twiddle factors)
Signal-flow graph connecting the inputs x (left) to the outputs y that depend on them (right) for a "butterfly"
step of a radix-2 Cooley–Tukey FFT. This diagram resembles a butterfly (as in the morpho butterfly shown
for comparison), hence the name, although in some countries it is also called the hourglass diagram.
36. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 27
RADIX-2 BUTTERFLY DIAGRAM:
In the case of the radix-2 Cooley–Tukey algorithm, the butterfly is simply a DFT of size-2 that takes two
inputs (x0, x1) (corresponding outputs of the two sub-transforms) and gives two outputs (y0, y1) by the
formula (not including twiddle factors):
If one draws the data-flow diagram for this pair of operations, the (x0, x1) to (y0, y1) lines cross and resemble the
wings of a butterfly,
More specifically, a radix-2 decimation-in-time FFT algorithm on n = 2 p
inputs with respect to a
primitive n-th root of unity relies on O(n log n) butterflies of the form:
where k is an integer depending on the part of the transform being computed. Whereas the corresponding
inverse transform can mathematically be performed by replacing ω with ω−1
(and possibly multiplying by
an overall scale factor, depending on the normalization convention), one may also directly invert the
butterflies:
corresponding to a decimation-in-frequency FFT algorithm.
A decimation-in-time radix-2 FFT breaks a length-N DFT into two length-N/2 DFTs followed by a
combining stage consisting of many butterfly operations.
37. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 28
EXERCISE:
TASK 1:
Given a Sequence x(n),compute DFT of the sequence by DIT butterfly method on Simulink.
a) X(n)={4,-3,2,0,-1,-2,3,1}
b) X(n)={1,1,1,1,1,1,1,1}
c) X(n)={3,0,2,9}
d) X(n)={9,12,6,2}
TASK 2:
Prove above task on script file. Also perform these tasks via DIF method.
TASK 3:
Given a sequence X[k] , Compute IDFT by using DIT butterfly method.
i) X[k]={20 -4+6i -4 -4-6i}
ii) X[k]={61 -2+5i -9 -2+5i}
iii) X[k]={40 -6+I -10-2i 8-i -8+i -10+2i -6-i 60}
TASK 4:
Prove above task on script File. Also perform these tasks via DIF method.
38. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 29
Laboratory Exercise 7
OPEN ENDED
● Objective:
● Hardware/Software required:
● Diagram:
● Methodology:
● Observation:
● Results and Discussions:
● Conclusion:
39. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 30
Laboratory Exercise 8
ANALYSIS OF Z TRANSFORM
Analysis of Z transforms and measure poles, zeros to check the stability of a
system.
OBJECTIVE:
● To generate a transfer function, this makes the system stable, marginally stable and unstable.
● Generate pole-zero map in z-plane for each system.
● Construct impulse response of each system.
● Compare the results of pole-zero map and impulse responses for each system individually.
THEORY:
Z-transform is discrete in nature or we can say that Z-transform operates in discrete time domain. With the
help of Z-transform we can check the stability of the systems such as filters, speech processing systems,
etc.
The Z-transform, like many integral transforms, can be defined as either a one-sided or two-sided transform.
The bilateral or two-sided Z-transform of a discrete time signal x[n] is the function X(z) defined as
X (z) = Z {x(n)} = ∑𝑛=∞
𝑛=−∞ 𝑥[𝑛]𝑧-n
Where, n is an integer and z is, in general, a complex number
z = Aejφ
= A (cosφ + jsinφ)
Where, A is the magnitude of z, and φis the complex argument (also referred to as angle or phase) in
radians. Alternativelyin cases where x[n] is defined only for n≥ 0, the single-sided or unilateral Z-transform
is defined as
X (z) = Z {x(n)} = ∑𝑛=∞
𝑛=0 𝑥[𝑛]𝑧-n
In digital signal processing, this definition can be used to evaluate the Z-transform, of the unit impulse
response of a discrete time causal system. From the above equation we can evaluate
X(z) = Z {x(n) r-n}
Once the poles and zeros have been found for given Z-transform, they can be plotted on to the Z-plane. The
40. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 31
Z-plane is a complex plane with an imaginary and real axis referring to the complex-valued variable z. the
position on the complex plane is given by re jθ and the angle from the positive, real axis around the plane
is denoted by θ. When mapping poles and zeros on to the plane, poles are denoted by an “x” and zeros by
an “o”.
Figure 10.1: Z-plane
As in this topic we are going to check the relationship between Z-transform and frequency response. If the
poles lie inside the unit circle the system said to be stable. If the poles lie on the unit circle the system is
said to be marginally stable and if the poles lies outside the unit circle the system will be unstable. The
placement of poles and zeros in the unit circle provides us the frequency response as well as the stability of
the system.
Impulse Response
In digital signal processing, the impulse response or impulse response function (IRF) is the output when
presented with a brief input signal, called an impulse. More generally, the impulse response refers to the
reaction of any system I response to some external change. In both cases, the impulse response describes
the reaction of the system as a function of time for possibly as a function of some other independent variable
that parameterizes the dynamic behavior of the system.
In general we have two types of impulse responses; Finite Impulse Response (FIR) and Infinite Impulse
Response (IIR). FIR depends upon previous value of input, if the system has FIR response then the value
of denominator in H(z) will be 1, i.e. poles are not present. On the other hand, IIR depends upon the previous
value of output. If the system has IIR response then the value of denominator in H(z) is other than 1, i.e.
poles are present.
FIR as mentioned above, is Finite Impulse Response filter, this means that such filter gives finite number
of pulses on output of filter and filter function can be described as
41. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 32
y [n] = x [n]*c0 + x [n-1]*c1 + ………….. + x [n-N]*cN
where y[n] is output signal at instant n, x[n] input signal al instant n, ck is the impulse response from 0 to
N instants and N is the number of samples in the pulse response.
Similarly, the IIR response can be seen as
y[n] = a1*y[n-1] + a2*y[n-2] + ….. + ak*y[n-k] + b0*x[n] + b1*x[n-1] + ….. + bk*x[n-k]
The equation of IIR filter has a feedback element which means that output signal y[n] is fed back to the
input. IIR filter response can be created with few coefficients comparing to FIR. So IIR requires less
computing power than FIR. But on other hand FIR filter is easier to design, but gives flat phase response.
FIR filters are also unconditionally stable while IIR can be unstable if designed poorly.
42. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 33
EXERCISE:
Task 1: Use matlab help to get familiar with following commands
i) Pzmap
ii) Roots
iii) Tf
iv) Zplane
Task 2:
a) Find out the zeros and poles of the following transfer functions with the help of roots
commandandalso plot them by using ‘zplane’.
b) Perform above tasks with pzmap command.
Task 3:Given a function H(z) =
1+2𝑧−1+𝑧−2
1−0.5𝑧−1+0.25𝑧−2
.Plot its magnitude & phase response.
Task 4: Generate a Transfer function and plot its response in z-plane so that the system is:
1
. Stable
(Pole(s) inside
unit circle)
2
. Marginally stable
(Pole(s) on the
unit circle)
3
. Unstable
(Pole(s) outside
unit circle)
Generate the plots for above conditions by using subplot of 3x1. Give proper label
and title to the subplots.
Task 5:Write a script file to find the transfer function from pole-zero values & plot its diagram.
Also plot frequency response of the system
a) Zeros are at (0,-1.5), poles are at (-0.3536±0.3536i) & gain constant is 1.
43. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 34
Laboratory Exercise 9
COMPUTATION OF Z-TRANSFORM
OBJECTIVE:
● Implement z- transform on a continuous signal
● Observe and display the transfer function in a discrete time sampled signal
● Convert partial fraction in to rational z transform and dismantle it
● Calculation of z transform through poles and zeros
THEORY:
The z-transform is useful for the manipulation of discrete data sequences and has acquired a new
significance in the formulation and analysis of discrete-time systems. It is used extensively today in the
areas of applied mathematics, digital signal processing, control theory, population science,
economics. These discrete models are solved with difference equations in a manner that is analogous to
solving continuous models with differential equations. The role played by the z-transform in the solution
of difference equations corresponds to that played by the Laplace transforms in the solution of differential
equations.
The function notation for sequences is used in the study and application of z-transforms. Consider a
function defined for that is sampled at times , where is the
sampling period (or rate). We can write the sample as a sequence using the notation
. Without loss of generality we will set and consider real sequences such as, . The
definition of the z-transform involves an infinite series of the reciprocals .
Given the sequence the z-transform is defined as follows
,
which is a series involving powers of .
Bilateral Z-transform Pair
Although Z transforms are rarely solved in practice using integration (tables and computers (e.g. Matlab)
are much more common), we will provide the bilateral Z transform pair here for purposes of discussion and
derivation. These define the forward and inverse Z transformations. Notice the similarities between the
forward and inverse transforms. This will give rise to many of the same symmetries found in Fourier
analysis.
44. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 35
Z Transform
X(z)=∑n=−∞∞x[n]z−n
Inverse Z Transform
x[n]=12πi∮rX(z)zn−1dz
Relation between Z-transform and DTFT
Taking a look at the equations describing the Z-Transform and the Discrete-Time Fourier Transform:
Discrete-Time Fourier Transform
X(eiω)=∑n=−∞∞x(n)e−(iωn)
Z-Transform
X(z)=∑n=−∞∞x[n]z−n
We can see many similarities; first, that :
X(eiω)=X(z)
for all z=eiω
Visualizing the Z-transform
With the DTFT, we have a complex-valued function of a real-valued variable ω (and 2 π periodic). The Z-
transform is a complex-valued function of a complex valued variable z.
Plots
Figure 1
45. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 36
With the Fourier transform, we had a complex-valued function of a purely imaginary variable, F(iω).
This was something we could envision with two 2-dimensional plots (real and imaginary parts or magnitude
and phase). However, with Z, we have a complex-valued function of a complex variable. In order to
examine the magnitude and phase or real and imaginary parts of this function, we must examine 3-
dimensional surface plots of each component.
46. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 37
EXERCISE:
TASK 1: Use matlab help to get familiar with following commands
v) c2d
vi) ztrans
vii) residuez
viii) impulse
ix) filtic
x) filter
TASK 2: Write a script file to convert the following continuous system in to discrete time using
Ts = 0.1sec. Also construct graph of step response.
a) A(s)=
3𝑆
𝑆+1
b) A(s)=
(𝑆+2)
(𝑆2+3𝑆+2)
TASK 3: Write a script file to reconstruct the continuous system from the discrete system obtained
in task 1.
TASK 4: Write a script file to find the z-transform of the following discrete time signals
(a)x(n)=(
1
2
)
𝑛
u(n)
(b)y(n)=(
1
2
)
𝑛
𝑢(𝑛) + (−
1
3
)
𝑛
𝑢(𝑛)
TASK 5: Plot the poles & zeroes in z-plane. State whether the system is FIR or IIR. Plot the
frequency response.
a) H(z) =
𝑧
𝑧−0.5
b) H(z)=
𝑧−0.5
𝑧
c) H(z) =
0.5𝑧2−0.32
𝑧2−0.5𝑧+0.25
TASK 6: Given the difference equations
a) y(n) = x(n-1) -0.75y(n-1) – 0.125y(n-2). Take n=0 to 10 &i/p x(n) = 0.5𝑛
u(n)
b) y(n) = 2x(n) – 25x(n-2) -28y(n-2) take n = 0 to 20 &i/p x(n) = 0.75𝑛
u(n)
Use filtic& filter command to calculate system response with initial conditions:
x(-1) = -1 ,y(-1) = 1,y(-2) = 2
47. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 38
TASK 7: Compute the partial fraction expansion of following transfer function
H (z) =
1+2𝑧−1
1−𝑧−1+2𝑧−2
and from obtained answer, convert back to transfer function
48. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 39
Laboratory Exercise 10
VIDEO PROCESSING USING MATLAB
Objective:
● Get familiar with basic commands of video processing and measure parameters.
● Import any video from library and apply basic commands on it and display
Theory:
The MATLAB functions associated with reading video files:
• aviread: to read an AVI video file & store the frames into a MATLAB video structure, which may me
actually 3D or 4D matrices, containing information about the monochrome or colored frames.
• aviinfo: returns a structure who contains information such as, frame width, frame height, total number of
frames, frame rate, file size, etc
• mmreader: constructs a multimedia [here mm stands for multimedia] object that can read video data from
a variety of multimedia file formats.
Playing Video Files In MATLAB
• movie: a built-in video player of MATLAB
• implay: a fully functional built in image & video player with many options.
Writing Video Files in MATLAB
• avifile: creates a new AVI file that can then be populated with video frames
in a variety of ways.
• movie2avi: creates an AVI file, from MATLAB Frame Sequence.
Common Applications
Video applications present common but difficult challenges that require flexible analysis and processing
functionality. Using MATLAB®
and Simulink®
products, you can develop solutions to common video
processing challenges such as video stabilization, video mosaicking, target detection, and tracking.
Object Tracking
Object tracking is an essential part of many applications including pedestrian avoidance, security and
surveillance, and augmented reality. This examples shows motion-based tracking of moving people in a
video from a stationary camera.
49. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 40
Example: Motion-based multiple object tracking
Object Detection and Counting
Video processing can be used to detect and count objects that move in video sequences. In this case study,
scientists in Australia are using video footage to estimate the wildlife population of waterbirds.
Video Processing in MATLAB
MATLAB®
provides tools and algorithms that let you view, analyze, read, and write videos. Video
processing can be useful in applications like:
50. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 41
● Object recognition with deep learning
● Motion estimation such as optical flow
● Face detection and tracking
Video Processing in 4 Easy Steps
Video processing in MATLAB involves the following steps:
1. Reading the video
2. Displaying the video
3. Processing the video
4. Writing the video
Step 1. Reading the Video
You can read video from files or directly from cameras.
A single MATLAB command lets you read in videos from a file:
>>vid = VideoReader('filename.avi')
MATLAB supports webcams for video processing, while Image Acquisition Toolbox™ enables live
acquisition from many industrial and scientific cameras.
MATLAB lets you read video files using a variety of codecs including OS-specific codecs for
Microsoft®
Windows®
, Mac, and Linux®
.
Step 2. Displaying the Video
There are two methods for displaying video in MATLAB:
● deployableVideoPlayer: Efficiently view a series of video frames
● implay: Launch the Video Viewer app for viewing videos
51. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 42
The Video Viewer app, which plays MATLAB movies, videos, or image sequences. The app lets you
start, stop, and play video at different speeds, and jump to a section of the video.
Step 3. Processing the Video
A video is a sequence of individual video frames, or images. This means an algorithm designed to
perform edge detection on an image can be quickly converted to perform edge detection on a video.
Read single image Read image frame from video
current_image = imread('flowers.png');
edge(current_image);
current_image = readFrame(vid);
edge(current_image);
Video processing can be very simple, as in the example using edge detection, or significantly more
complex, such as tracking algorithms that must account for an object’s location in previous frames.
For more information on advanced video processing, see examples for:
52. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 43
● KLT tracking algorithm
● Foreground detection using Gaussian mixture models
● Multi-object tracking
Step 4. Writing the Video
After processing, you can write each frame of a video back to a file. You can create a video file with the
function:
>>vid_w = VideoWriter('newfile.avi');
>>open(vid_w)
The variable vid_w can accumulate new frames to create a video.
A Complete MATLAB Example
Putting all the components together, let’s run through a complete example to show the steps of reading,
displaying, processing, and writing video:
%% Read and process a video into MATLAB
% Setup: create Video Reader and Writer
videoFileReader = VideoReader('tilted_face.avi');
myVideo = VideoWriter('myFile.avi');
% Setup: create deployable video player and face detector
depVideoPlayer = vision.DeployableVideoPlayer;
faceDetector = vision.CascadeObjectDetector();
open(myVideo);
53. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 44
%% Detect faces in each frame
whilehasFrame(videoFileReader)
% read video frame
videoFrame = readFrame(videoFileReader);
% process frame
bbox = faceDetector(videoFrame);
videoFrame = insertShape(videoFrame, 'Rectangle', bbox);
% Display video frame to screen
depVideoPlayer(videoFrame);
% Write frame to final video file
writeVideo(myVideo, videoFrame);
pause(1/videoFileReader.FrameRate);
end
close(myVideo)
54. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 45
Exercise:
Task 1: Use matlab help to investigate the following commands
⮚ vision.VideoPlayer
⮚ vision.VideoFileReader
⮚ hasFrame
⮚ implay
⮚ vision.DeployableVideoPlayer
⮚ vision.CascadeObjectDetector
Task 2:Write a code to read any video file and display its information.
Task 3:Write a code to read any video file and play it using videoplayer.
Task 4(a): Write a code to detect faces in any image file by using cascade detector
Task 4(b): Write a code to detect faces in any video file by using cascade detector
55. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 46
Laboratory Exercise 11
PERFORM VARIOUS TASKS USING DSK C6416T PROCESSOR AND
RELATED CCS SOFTWARE TOOL
OBJECTIVE:
Perform and understand DSK (DSP Starter Kit) in which we include:
● System requirements for installing DSK contents.
● Installation procedures.
● Connectivity procedures.
● Testing connections.
● Debug hints and troubleshooting.
● DSP board components.
● Configuration parameters settings.
● DSP board features.
● CCS Software.
THEORY:
C6416T Overview:
The purpose of this lab is to familiarize you with DSP Kit TMS320C6416T Simulink, Real Time Workshop
and Link for CCS and how they interact with Code Composer Studio (CCS). This lab involves building
relatively simple systems using Simulink rather than CCS.
DSP Board: Texas Instruments TMS320C6416T (DSP Starter Kit) DSK
The 6416 DSP Starter Kit (DSK) is an all-in-one evaluation platform for the TMS320C6416T Digital Signal
Processor from Texas Instruments. It includes a target board that can be used as a reference design for
interfacing the DSP to common devices such as SDRAM, Flash and a codec as well as a Code Composer
Studio development tools. An on-board JTAG emulator allows debug from Code Composer Studio through
your PC's USB port.
56. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 47
Figure 3.1: Block Diagram of TMS320C6416T Board
The TMS320C6416T DSK comes with a full complement of on-board devices that suit a wide variety of
application environments. Key features include:
• A Texas Instruments TMS320C6416T DSP operating at 1 Gigahertz.
• An AIC23 stereo codec
• 16 Mbytes of synchronous DRAM
• 512 Kbytes of non-volatile Flash memory
• 4 user accessible LEDs and DIP switches
• Software board configuration through registers implemented in CPLD
• Configured boot options and clock input selection
• Standard expansion connectors for daughter card use
• JTAG emulation through on-board JTAG emulator with USB host interface or external emulator
• Single voltage power supply (+5V)
⮚ System Requirements for installing DSK contents
● 500MB of free hard disk space
● Microsoft Windows™ 2000/XP
● 128MB of RAM
● 16-bit color display
● CD-ROM Drive
57. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 48
⮚ Install DSK Content from the CD-ROM
Before you install the DSK software, please make sure you are using Administrator privileges and any
virus checking software is turned off. The DSK board should not be plugged in at this point.
1. Insert the Code Composer Studio installation CD into the CD-ROM Drive. An install menu (see below)
should appear. If it does not, manually run Launch.exe from the CD-ROM. Select the Install Products
option from the menu.
2. Install any components you need. To debug with the DSK you must have 1) a copy of Code Composer
Studio, 2) the target content package for your board and 3) a copy of the FlashBurnplug-in. Users of
the full Code Composer Studio package can skip the DSK Code Composer installation and simply
install the target content packages.
3. The installation procedure will create two icons on your desktop:
● 6416 DSK CCStudio v3.1
● 6416 DSK Diagnostics Utility v3.1
⮚ Connect the DSK to Your PC
1. Connect the supplied USB cable to your PC or laptop. We recommend that anyone making hardware
modifications connect through a USB hub for safety.
2. If you plan to connect a microphone, speaker, or expansion card these must be plugged in properly
before you connect power to the DSK board.
3. Connect the included 5V power adapter brick to your AC power source using the AC power cord.
4. Apply power to the DSK by connecting the power brick to the 5V input on the DSK.
5. When power is applied to the board the Power OnSelf Test (POST) will run. LEDs 0-3 will flash.
When the POST is complete all LEDs blink on and off then stay on. At this point your DSK is functional
and you can now finish the USB driver install.
6. Make sure your DSK CD-ROM is installed in your CD-ROM drive. Now connect the DSK to your PC
using the included USB. After few seconds Windows will launch its "Add New Hardware Wizard" and
prompt for the location of the DSK drivers.
7. Follow the instructions on the screens and let Windows find the USB driver files “dsk6416.inf” and
“sdusb2em.sys” on the DSK CD-ROM. On XP systems Windows will find the drivers automatically.
⮚ Testing Your Connection
If you want to test your DSK and USB connection you can launch the C6416 DSK Diagnostic Utility
from the icon on your desktop.
58. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 49
Figure 3.2: 6416 DSK Diagnostics icon
From the diagnostic utility, press the start button to run the diagnostics. In approximately 30 seconds
all the on-screen test indicators should turn green.
Figure 3.3: 6416 DSK Diagnostics window
⮚ Starting Code Composer
To start Code Composer Studio, double click the 6416 DSK CCStudio icon on your desktop.
59. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 50
Figure 3.4: 6416 DSK CCStudio v3.1 icon
⮚ Debug Hints and Trouble Shooting
1. If installing on Windows XP and your PC is connected to the internet through a firewall the USB install
may take up to 15 minutes if you let it complete normally. The work-around for this issue is to simply
disconnect your network cable during the USB hardware install.
2. Make sure all of the Configuration Switches (SW3) are set in the off position. This configures the DSK
for the factory default settings of little endian processor mode booting out of the on-board Flash
memory.
3. If you want to verify a successful USB driver install, open your device manager by right clicking on
the My Computer icon on your desktop and selecting Properties --> HW --> Device Manager. You
should see a new class “SD USB Based Debug Tools” and one Spectrum Digital TMS320C6416 DSK
installed.
4. The BUSY LED above the USB connector comes on when power is applied to the DSK. Do not launch
Code Composer until the LED is off.
DSP Board Components
DSP board components and their specifications are given in table below:
Components Details
TMS320C6416T DSP 1GHz MHz, fixed point, 1Mbyte internal RAM
CPLD Programmable "glue" logic
External SDRAM 16Mbytes, 64-bit interface
External Flash 512Kbytes, 8-bit interface
AIC23 Codec Stereo, 8KHz –96KHz sample rate, 16 to 32 bit samples, Mic, line-in,
line-out and speaker jacks
4 User LEDs Writable through CPLD
4 User DIP Switches Readable through CPLD
60. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 51
8 Configuration Switches Selects power-on configuration and boot modes
Daughter card Expansion Interface Allows user to enhance functionality with add-on daughter cards
HPI Expansion Interface Allows high speed communication with another DSP
Embedded JTAG Emulator Provides high speed JTAG debug through widely accepted USB host
interface
6416T DSK Specifications
⮚ Configuration Switches
The 6416T DSK has 8 configuration switches that allow users to control the operational state of the DSP
when it is released from reset. The configuration switch block is labeled SW3 on the DSK board, next to
the reset switch. Configuration switch 1 controls the endianness of the DSP while switches 2 and 3 configure
the boot mode that will be used when the DSP starts executing. Configuration switches 5-8 used to configure
the EMIF and DSP frequencies.
The default configuration settings are to have all switches off. This configures the DSK to boot from the
on-board Flash in little endian mode.
Configuration switch settings
The following table shows the switch position settings for desired CPU and EMIFA frequencies.
61. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 52
CPU and EMIFA frequency configuration switch settings
⮚ AIC23 Stereo Codec
The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for input and output of
audio signals. The codec samples analog signals on the microphone or line inputs and converts them into
digital data that can be processed by the DSP. When the DSP is finished with the data it uses the codec to
convert the samples back into analog signals on the line and headphone outputs so the user can hear the
output.
Four industry-standard 3.5mm stereo jack connectors are used in the audio interface:
● One jack is for connecting audio input from a microphone.
● One jack for connecting stereo audio line input.
● One jack for outputting stereo audio line output (un-amplified).
● One jack for connecting stereo audio output to a speaker (amplified).
⮚ User LEDs
The four user controllable LEDs allow for user feedback and display of simple status information. They are
controlled by writing to the CPLD USER_REG register. They can also be set or cleared through the LED
Module of the Board Support Library.
⮚ Status Indicators
62. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 53
The status indicators monitor the following functions. The PWR LED is hardwired on the +5V supply and
will illuminate whenever the power is connected. The RESET LED illuminates when the RESET event
occurs. The USB_IN_USE LED is on when USB emulation is used and goes off when an external emulator
is applied. The USB BUSY LED indicates that a USB emulator transaction is in progress.
⮚ DIP Switches
The four DIP switches allow simple feedback from the user. The DIP switches can be read through the
CPLD USER_REG register. They can also be read using the DIP Switch module of the Board Support
Library.
⮚ Power Supply
An included 5V external power supply is used to power the board. On-board voltage regulators provide the
1.4V DSP core voltage, 3.3V digital and 3.3V analog voltages. A voltage supervisor monitors the internally
generated voltage, and will hold the board in reset until the supplies is within operating specifications and
the reset button is released. If desired, JP1, JP2 and JP4 can be used as power test points for the core, I/O
and system power supplies.
DSP Board Features
The DSK supports a TMS320C6416T DSP which can operate at a clock frequency of up to 1 GHz. The
DSP core is designed for extremely high performance. Beyond the DSP core, the ‘6416 integrates a number
of on-chip resources that improve functionality and minimize hardware development complexity. Features
of the processor include:
⮚ EMIFA – External Memory Interface A
A 64-bit bus on which external memories and other devices can be connected. It included features like
internal wait state generation and SDRAM control. The EMIF can interface to both synchronous and
asynchronous memories.
⮚ EMIFB – External Memory Interface B
A 16-bit bus on which external memories and other devices can be connected.Similar to EMIFA but with
narrower bus width. Used for devices those are not as performance critical or do not require maximum
bandwidth.
⮚ McBSPs– Multichannel buffered serial ports
Each McBSP can be used for high speed serial data transmission with external devices or reprogrammed
as general purpose I/Os. McBSP2 is used to transmit and receive audio data from the AIC23 stereo codec.
McBSP1 is used to control the codec through its serial control port. McBSP0 is always brought out to the
peripheral expansion connector. The MISC register in the CPLD is used to select whether McBSP1 and
McBSP2 are routed to the AIC23 or the expansion connectors.
⮚ 1Mbyte Internal Memory
High speed internal memory for maximum performance.
⮚ On-chip PLL
63. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 54
Generate processor clock rate from slower external clock reference.
⮚ 3 Timers
Generate periodic timer events as a function of the processor clock. Used by DSP/BIOS to create time slices
for multitasking.
⮚ EDMA Controller
Enhanced DMA controller allows high speed data transfers without intervention from the DSP.
⮚ Endianness
Endianness is a term that refers to the byte ordering of multi-byte data types. Specifically, a system is called
big endian if byte 0 contains the most significant byte of the data or little endian if byte 0 contains the least
significant byte. The 6416 supports both modes and the processor endianness can be controlled at boot time
through one of the configuration switches. The DSK default is little endian mode and all of the DSK specific
code examples are distributed in little endian format.
64. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 55
EXERCISE:
TASK 1: Write a brief report (1 to 2 pages) about your learning, observation and understanding of this lab.
TASK 2: Write a code to blink all leds and observe the output using this kit.
TASK 3: Write a code to toggle led 0 and 2 and increase the time delay gradually.
TASK 4: Write a code to toggle led 1 and 3 and decrease the time delay gradually.
TASK 5: Generate tone using AIC23
65. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 56
Laboratory Exercise 12
PRODUCE SINE WAVE USING EIGHT POINTS WITH DIP
SWITCH CONTROL OF TSMC DSP KIT
Objective: Produce Sine Wave Using Eight Points with Dip Switch Control of TSMC
DSK (DSP Starter Kit). This lab generates the beep of sinusoid using a table lookup
method. More important, it illustrates some features of CCS for editing, building a project,
accessing the code generation tools, and running a program on the C6416 processor. In the
end the beep sound will not only be heard but also be observed as visual effect by LED dip
switches of C6416 DSK.
Program Explanation
Although the purpose is to illustrate some of the tools, it is useful to understand the program
sine8_LED.c. A table or buffer sine_table is created and filled with eight points
representing sin(t), where t = 0, 45, 90, 135, 180, 225, 270, and 315 degrees (scaled by
1000). Within the function main, another function, comm_poll, is called that is located in
the communication and initialization support file c6416dskinit.c. It initializes the DSK,
along with C64163 processor. Within c6416dskinit.c, the function DSK6416_init
initializes the BSL file, which must be called before the two subsequent BSL functions,
DSK6416_LED_init and DSK6416_DIP_init, are invoked that initialize the four LEDs and
the four dip switches.
The statement while (1) within the function main creates an infinite loop. When dip switch
#0 is pressed, LED #0 turns on and the sinusoid is generated. Otherwise,
DSK6416_DIP_get(0) will be false (true if the switch is pressed) and LED #0 will be off.
//Sine8_LED.c Sine generation with DIP switch control
#include "dsk6416_aic23.h" //support file for
codec,DSK
Uint32 fs = DSK6416_AIC23_FREQ_8KHZ; //set sampling rate
short loop = 0; //table index
short gain = 10; //gain factor
66. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 57
short sine_table[8]={0,707,1000,707,0,-707,-1000,-707}; //sine values
void main()
{
comm_poll(); //init DSK, codec, McBSP
DSK6416_LED_init(); //init LED from BSL
DSK6416_DIP_init(); //init DIP from BSL
while(1) //infinite loop
{
if(DSK6416_DIP_get(0)==0) //=0 if switch #0 pressed
{
DSK6416_LED_on(0); //turn LED #0 ON
output_sample(sine_table[loop]*gain); //output every Ts (SW0 on)
if (++loop > 7) loop = 0; //check for end of table
}else DSK6416_LED_off(0); //LED #0 off
} //end of while (1)
} //end of main
The function output_sample, located in the communication support file C6416dskinit.c, is
called to output the first data value in the buffer or table sine_table[0] = 0. The loop index
is incremented until the end of the table is reached, after which it is reinitialized to zero.
Every sample period T = 1/Fs = 1/8000 = 0.125ms, the value of dip switch #0 is tested, and
a subsequent data value in sine_table (scaled by gain = 10) is sent for output.Within one
period, eight data values (0.125 ms apart) are output to generate a sinusoidal signal. The
period of the output signal is T = 8(0.125 ms) = 1ms, corresponding to a frequency of f =
1/T = 1kHz.
Create Project
In this section we illustrate how to create a project, adding the necessary files for building
the project sine8_LED. Back up the folder sine8_LED (change its name) or delete its
content, keeping only the C source file sine8_LED.c and the file gain.gel in order to
recreate the content of that folder. Access CCS (from the desktop).
1. To create the project file sine8_LED.pjt. Select Project > New. Type sine8_LED for
the project name. This project file is saved in the folder sine8_LED (within
67. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 58
c:c6416myprojects). The .pjt file stores project information on build options,
source filenames, and dependencies.
2. To add files to the project. Select Project Add Files to Project. Look in the folder
support, Files of type C Source Files. Double-click on the C source file
C6416dskinit.c to add it to the project. Click on the “+” symbol to the left of the
Project Files window within CCS to expand and verify that this C source file has
been added to the project.
3. Repeat step 2, use the pull-down menu for Files of type, and select ASM Source
Files. Double-click on the assembly source vector file vectors_poll.asm to add it to
the project. Repeat again and select Files of type: Linker Command File, and add
C6416dsk.cmd to the project.
4. To add the library support files to the project. Repeat the previous step, but select
files of type: Object and Library Files. Look in c:c6416c6000cgtoolslib and select
the run-time support library file rts6700.lib (which supports the C6416 architecture
as well) to add to the project. Continue this process to add the BSL file
dsk6416bsl.lib located in c:c6416c6000dsk6416lib, and the chip support library
(CSL) file csl6416.lib located in c:c6416c6000bioslib.
5. Verify from the Files window that the project (.pjt) file, the linker command (.cmd)
file, the three library (.lib) files, the two C source (.c) files, and the assembly (.asm)
file have been added to the project.
6. Note that there are no “include” files yet. Select Project > Scan All File
Dependencies. This adds/includes the header files c6416dskinit.h, along with
several board and chip support header files included with CCS. Any of the files
(except the library files) from CCS’s Files window can be displayed by clicking on
it. You should not add header or include files to the project. They are added to the
project automatically when you select: Scan All File Dependencies. (They are also
added when you build the project.) It is also possible to add files to a project simply
by “dragging” the file (from a different window) and dropping it into the CCS
Project window.
Code Generation and Options
Various options are associated with the code generation tools: C compiler and linker to
build a project.
68. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 59
Compiler Option
Select Project > Build Options. Select the Preprocessor Category and type for Define
Symbols{d}: CHIP_6416, and from the Feedback Category, select for Interlisting: OPT/C
and ASM{-s}. The resulting compiler option is:
-g -s
The -g option is used to enable symbolic debugging information, useful during the
debugging process, and is used in conjunction with the option -s to interlist the C source
file with the assembly source file sine8_LED.asm generated (an additional option, -k, can
be used to retain the assembly source file). The -g option disables many code optimizations
to facilitate the debugging process. Press OK.
Selecting C621x or C64xx for Target Version invokes a fixed-point implementation. The
C6416-based DSK can use either fixed- or floating-point processing. Most examples
69. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 60
implemented in this book can run using fixed-point processing. Selecting C641x as Target
Version invokes a floating-point implementation.
If No Debug is selected (for Generate Debug Info) and -o3: File is selected (for Opt Level),
the Compiler option is automatically changed to
-s -o3
The -o3 option invokes the highest level of optimization for performance or execution
speed. For now, speed is not critical (neither is debugging). Use the compiler options -gs
(which you can also type directly in the compiler command window). Initially, one would
not optimize for speed but to facilitate debugging.
Linker Option
Click on Linker (from CCS Build Options).The output filename sine8_LED.out defaults to
the name of the .pjt filename, and Run-time Autoinitialization defaults for Autoinit Model.
70. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 61
The map file can provide useful information for debugging (memory locations of functions,
etc.).The -c option is used to initialize variables at run time, and the -o option is used to
name the linked executable output file sine8_LED.out. Press OK.
Note that you can/should choose to store the executable file in the subfolder “Debug,”
within the folder sine8_LED, especially during the debugging stage of a project.
Again, these various compiler and linker options can be typed directly within the
appropriate command windows. In lieu of adding the three library files to the project by
retrieving them from their specific locations, it is more convenient to add them within the
linker option window Include Libraries{-l}, typing them directly, separated by a comma.
However, they will not be shown in the Files window.
71. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 62
Building and Running the Project
The project sine8_LED can now be built and run.
1. Build this project as sine8_LED. Select Project > Rebuild All or press the toolbar
with the three down arrows. This compiles and assembles all the C files using cl6x
and assembles the assembly file vectors_poll.asm using asm6x. The resulting object
files are then linked with the library files using lnk6x. This creates an executable
file sine8_LED.out that can be loaded into the C6416 processor and run. Note that
the commands for compiling, assembling, and linking are performed with the Build
option. A log file cc_build_Debug.log is created that shows the files that are
compiled and assembled, along with the compiler options selected. It also lists the
support functions that are used. The building process causes all the dependent files
to be included (in case one forgets to scan for all the file dependencies).
2. Select File > Load Program in order to load sine_LED.out by clicking on it (CCS
includes an option to load the program automatically after a build). It should be in
the folder sine8_LEDDebug. Select Debug > Run or use the toolbar with the
“running man.” Connect a speaker to the LINE OUT connector on the DSK. Press
the dip switch #0. You should hear a tone. You can also use the headphone output
at the same time.
The sampling rate Fs of the codec is set at 8kHz. The frequency generated is f = Fs/(number
of points) = 8 kHz / 8 = 1kHz. Connect the output of the DSK to an oscilloscope to verify
a 1-kHz sinusoidal signal with approximate amplitude of 0.8 V p-p (peak to peak).
72. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 63
Exercises
1. This lab demonstrates the whole procedure how to create and execute signal processing
on real time basis. We have simply heard the voice of sine wave by applying the same
method. How about controlling its voice using a volume slider, just like you see on your
desktop?
The General Extension Language (GEL) is an interpretive language similar to (a subset
of) C. It allows you to change a variable such as gain, sliding through different values
while the processor is running. All variables must first be defined in your source
program.
Select File >Load GEL and open the file gain.gel, which you retained from the “C6711
and C6416 support files.rar” on sites.google.com/site/ovaisakhter, sine8_LED (that
you backed up). Double-click on the file gain.gel to view it within CCS. It should be
displayed in the Files window. For your assistance, the coding of gain.gel is written
below. You can also verify it by double clicking on same file.
/*gain.gel Create slider and vary amplitude (gain) of sinewave*/ menuitem "Sine Gain"
slider Gain(10,35,5,1,gain_parameter) /*incr by 5,up to 35*/
{
gain = gain_parameter; /*vary gain of sine*/
}
Here, you can start with an initial value of 10 (first value) for the variable gain that is
set in the C program, up to a value of 35 (second value), incremented by 5 (third value).
Select GEL > Sine Gain > Gain. This should bring out the Slider window shown in
figure below, with the minimum value of 10 set for the gain. Here you go with a volume
slider that will ultimately change the volume of generated sine wave.
73. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 64
2. Change the sampling frequency from 8 to 16 kHz by setting fs in the C source program
to DSK6416_AIC23_FREQ_16KHz (line 3 of main program). Rebuild (use
incremental build) the project, load and run the new executable file, and verify that the
frequency of the generated sinusoid is 2kHz. The sampling frequencies supported by
the C6416 codec are 8, 16, 24, 32, 44.1, 48, and 96kHz. (Do not apply any other
frequencies except these; it’s useless)
3. Change the number of points in the lookup table to four points in lieu of eight points—
for example, {0, 1000, 0, -1000}. The size of the array sine_table and the loop index
also need to be changed. Verify that the generated frequency is f = Fs/(number of
points).
4. Still you have not seen the graph of sine wave. Amazing! Looks like you have done
nothing. This task will elaborate the procedure to draw the sine wave on which we have
learnt a lot. For your convenience, the coding of this program is given below. No need
to type it and instead, open file sine8_buf.c from “C6711 and C6416 support files.rar”
available on website.
//sine8_buf Sine generation. Output buffer plotted within CCS
#include "dsk6416_aic23.h" //codec-DSK support file
Uint32 fs=DSK6416_AIC23_FREQ_8KHZ; //set sampling rate
int loop = 0; //table index
74. Digital Signal Processing (EE-322L) Lab Manual
-Department of Electronic Engineering-
-Sir Syed University of Engineering & Technology-
Page | 65
short gain = 10; //gain factor
short sine_table[8]={0,707,1000,707,0,-707,-1000,-707};//sine values
short out_buffer[256]; //output buffer
const short BUFFERLENGTH = 256; //size of output buffer
int i = 0; //for buffer count
interrupt void c_int11() //interrupt service routine
{
output_sample(sine_table[loop]*gain); //output sine values
out_buffer[i] = sine_table[loop]*gain; //output to buffer
i++; //increment buffer count
if(i==BUFFERLENGTH) i=0; //if @ bottom reinit count
if (++loop > 7) loop = 0; //check for end of table
return; //return from interrupt
}
void main()
{
comm_intr(); //init DSK, codec, McBSP
while(1); //infinite loop
}
Create this project as sine8_buf.pjt, and add the necessary support files to the project,
(use the C source program sine8_buf.c in lieu of sine8_led.c). Repeat the whole
procedure and build the program in the same manner what you have learnt in this lab.
Only the following procedure will be added to previous in order to view the sinusoidal.
Select View > Graph >Time/Frequency. Change the Graph Property Dialog so that the
options in following figure (b) are selected for a time-domain plot (use the pull-down
menu when appropriate).The starting address of the output buffer is out_buffer. The
other options can be left as default. Figure (a) shows a time-domain plot of the
sinusoidal signal within CCS.