Digital system design

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SRI RAMAKRISHNA ENGINEERING COLLEGE
[Educational Service: SNR Sons Charitable Trust]
[Autonomous Institution, Accredited by NAAC with ‘A’ Grade]
[Approved by AICTE and Permanently Affiliated to Anna University, Chennai]
[ISO 9001:2015 Certified and all eligible programmes Accredited by NBA]
Vattamalaipalayam, N.G.G.O. Colony Post, Coimbatore – 641 022.
Course Instructors:
Mr.V.Gopu,AP(Sl.G)/EEE
Mrs.N.Divya, AP/EEE No. of Credits: 3
Department of Electrical and Electronics Engineering
20EC204 – DIGITAL SYSTEM DESIGN
EEE

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EEE
Syllabus
20EC204 DIGITAL SYSTEM DESIGN 3 0 0 3
Course Outcomes
On successful completion of the course, students will be able to
CO1: Interpret the principles of Boolean algebra to manipulate and minimize logic
expressions
CO2: Design the combinational logic circuits
CO3: Construct finite state machines using sequential circuits
CO4: Explain the concepts of logic families and memory devices
CO5: Describe the concepts of Verilog HDL
FUNDAMENTALS OF DIGITAL SYSTEMS 5
Digital Abstraction – Number System and Codes - Boolean algebra and logic gates – From
Logic to Gates - Simplification of Switching Functions - Karnaugh Map Method - Quine-
McCluskey Technique.
COMBINATIONAL LOGIC CIRCUITS 10
Analysis of combinational logic circuits - Arithmetic Circuits - Magnitude comparator -
Decoders / Encoders - Multiplexers / Demultiplexers – Code converters - Parity circuits –
Applications of combinational logic circuits.

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EEE
Syllabus
SEQUENTIAL LOGIC CIRCUITS 15
Models for Sequential logic circuits – Flip-flops - Analysis of clocked synchronous
sequential circuits – Mealy and Moore machines - Finite state machine – State
minimization/reduction, state assignment - Applications - Counters – Registers - Types
of Asynchronous logic circuits – Analysis and Synthesis of Fundamental mode
Asynchronous logic circuits – Introduction to pulse mode asynchronous sequential
circuits - Cycles – Races – Hazards.
LOGIC FAMILIES AND MEMORY DEVICES 6
Characteristics of Digital ICs, DTL, TTL, ECL, Calculation of noise margins and fan-
out. Memory: Basic Organization, ROM, RAM, PROM, EPROM, EEPROM - PLDs, -
FPGA – Design of combinational circuits using PLDs.
HARDWARE DESCRIPTION LANGUAGE 9
Introduction to VLSI design – Design flow - Hierarchical Modelling Concepts – Modules
& Ports – Modelling techniques – Tasks and Functions – User defined primitives -
Realization of combinational and sequential circuits using Verilog HDL.
CASE STUDY:
Systematic design approach for Leap Year Calculation, Digital Combination Lock
Total Hours: 45

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EEE
Syllabus
TEXT BOOKS
1. Morris Mano, "Digital Design", 6th Edition, Pearson Education Ltd., 2018.
2. Randy H. Katz, Gaetano Borriello, “Contemporary Logic Design”, 2nd Edition, Prentice
Hall, 2005.
3. Samir Palnitkar, "Verilog HDL", Prentice Hall, 2010.
REFERENCE BOOKS
1. Ronald J. Tocci, “Digital Systems: Principles and Applications”, 12th Edition,
Pearson Education, 2017.
2. Charles H.Roth, "Fundamentals of Logic design", 7th Edition, Thomson Learning,
2014.
3. Victor P. Nelson, H. Troy Nagle, J. David Irvin, Bill D. Carol, “Digital logic Analysis
and design”, 2nd edition, Pearson Education, 2019
4. S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, Tata
Mc-Graw Hill, 2008.
WEB REFERENCES
1. https://onlinecourses.nptel.ac.in/noc21_ee10

5. MODULE I
FUNDAMENTALS OF DIGITAL
SYSTEMS
5
EEE

6. CO 1 : Interpret the principles of Boolean algebra to
manipulate and minimize logic expressions
Contents
 Digital Abstraction
 Number System and Codes
 Boolean algebra and logic gates
 From Logic to Gates
 Simplification of Switching Functions
 Karnaugh Map Method
 Quine-McCluskey Technique.
6
EEE

7. Introduction

8. Electronics Milestones

9. Evolution of Electronic Devices

10. Digital Abstraction
Analog versus Digital Electronics

11. Signal Types

12. Analog and Digital Signals

13. Analog and Digital Signals

14. Analog and Digital Signals
Summary
• Analog signals suffer from noise, but don’t
need such complex equipment.
• Digital signals need fast, clever electronics,
but we can get rid of any noise.

15. Number System and Codes

16. Quantities

17. Quantities

18. Quantities

19. Conversion among Bases

20. Quick Example

21. Binary to Decimal

22. Binary to Decimal
Technique
– Multiply each bit by 2n, where n is the “weight” of the bit
– The weight is the position of the bit, starting from 0 on the
right
– Add the results

23. Binary to Decimal - Example

24. Octal to Decimal

25. Octal to Decimal
Technique
– Multiply each bit by 8n, where n is the “weight” of the bit
– The weight is the position of the bit, starting from 0 on the
right
– Add the results

26. Octal to Decimal - Example

27. Hexadecimal to Decimal

28. Hexadecimal to Decimal
Technique
– Multiply each bit by 16n, where n is the “weight” of the bit
– The weight is the position of the bit, starting from 0 on the
right
– Add the results

29. Hexadecimal to Decimal - Example

30. Decimal to Binary

31. Decimal to Binary
Technique
– Divide by two, keep track of the remainder
– First remainder is bit 0 (LSB, least-significant bit)
– Second remainder is bit 1

32. Decimal to Binary - Example

33. Decimal to Binary

34. Octal to Binary

35. Octal to Binary
Technique
– Convert each octal digit to a 3-bit equivalent binary
representation

36. Octal to Binary - Example

37. Octal to Binary - Example

38. Hexadecimal to Binary

39. Hexadecimal to Binary
Technique
– Convert each hexadecimal digit to a 4-bit equivalent binary
representation

40. Hexadecimal to Binary - Example

41. Decimal to Octal

42. Decimal to Octal
Technique
– Divide by 8
– Keep track of the remainder

43. Decimal to Octal - Example

44. Decimal to Hexadecimal

45. Decimal to Hexadecimal
Technique
– Divide by 16
– Keep track of the remainder

46. Decimal to Hexadecimal - Example

47. Binary to Octal

48. Binary to Octal
Technique
– Group bits in threes, starting on right
– Convert to octal digits

49. Binary to Octal - Example

50. Binary to Hexadecimal

51. Binary to Hexadecimal
Technique
– Group bits in fours, starting on right
– Convert to hexadecimal digits

52. Binary to Hexadecimal - Example

53. Octal to Hexadecimal

54. Octal to Hexadecimal
Technique
– Use binary as an intermediary

55. Octal to Hexadecimal - Example

56. Hexadecimal to Octal

57. Hexadecimal to Octal
Technique
– Use binary as an intermediary

58. Hexadecimal to Octal - Example

59. Fractions

60. Binary Codes
• In the coding, when numbers, letters or words are
represented by a specific group of symbols, it is
said that the number, letter or word is being
encoded. The group of symbols is called as a
code.
• The digital data is represented, stored and
transmitted as group of binary bits. This group is
also called as binary code.
• The binary code is represented by the number as
well as alphanumeric letter.

61. Classification of binary codes
The codes are broadly categorized into following
categories.
• Weighted Codes
• Non-Weighted Codes
• Binary Coded Decimal Code
• Alphanumeric Codes
• Error Codes
• Error Detecting Codes
• Error Correcting Codes

62. Weighted Codes
• Weighted binary codes are those binary codes
which obey the positional weight principle.
• Each position of the number represents a specific
weight.
• Several systems of the codes are used to express
the decimal digits 0 through 9.
• In these codes each decimal digit is represented
by a group of four bits.

63. Example : 8421 code

64. Non-Weighted Codes
• In this type of binary codes, the positional
weights are not assigned.
• The examples of non-weighted codes are Excess-
3 code and Gray code.

65. Excess-3 code
• The Excess-3 code is also called as XS-3 code. It is non-
weighted code used to express decimal numbers.
• The Excess-3 code words are derived from the 8421 BCD code
words adding (0011)2 or (3)10 to each code word in 8421.
• The excess-3 codes are obtained as follows −

66. Example

67. Gray Code
• It is the non-weighted code and it is not
arithmetic codes.
• That means there are no specific weights assigned
to the bit position.
• It has a very special feature that, only one bit will
change each time the decimal number is
incremented.
• As only one bit changes at a time, the gray code
is called as a unit distance code.
• The gray code is a cyclic code. Gray code cannot
be used for arithmetic operation.

68. Example

69. Binary Coded Decimal (BCD) code
• In this code each decimal digit is represented by a 4-bit binary
number.
• BCD is a way to express each of the decimal digits with a
binary code.
• In the BCD, with four bits we can represent sixteen numbers
(0000 to 1111).
• But in BCD code only first ten of these are used (0000 to
1001).
• The remaining six code combinations i.e. 1010 to 1111 are
invalid in BCD.

70. Alphanumeric codes
• A binary digit or bit can represent only two
symbols as it has only two states '0' or '1’.
• But this is not enough for communication
between two computers because there we need
many more symbols for communication.
• These symbols are required to represent 26
alphabets with capital and small letters, numbers
from 0 to 9, punctuation marks and other
symbols.

71. Alphanumeric codes
• The alphanumeric codes are the codes that
represent numbers and alphabetic characters.
• Mostly such codes also represent other characters
such as symbol and various instructions necessary
for conveying information.
• An alphanumeric code should at least represent
10 digits and 26 letters of alphabet i.e. total 36
items.

72. Alphanumeric codes
The following three alphanumeric codes are very
commonly used for the data representation.
• American Standard Code for Information Interchange
(ASCII).
• Extended Binary Coded Decimal Interchange Code
(EBCDIC).
• Five bit Baudot Code - International Teleprinter Code.
ASCII code is a 7-bit code whereas EBCDIC is an 8-bit
code. ASCII code is more commonly used worldwide
while EBCDIC is used primarily in large IBM computers.

73. Error codes
• Whenever a message is transmitted, it may get
scrambled by noise or data may get corrupted.
• To avoid this, we use error-detecting codes which
are additional data added to a given digital
message to help us detect if an error occurred
during transmission of the message.
• A simple example of error-detecting code is
parity check.

74. Binary Addition

75. Binary Addition

76. Binary Addition

77. Binary Addition - Example

78. Binary Subtraction

79. Binary Subtraction - Example

80. Binary Multiplication

81. Binary Multiplication

82. Binary Division

83. 1’s Complement
• The 1’s complement of a binary number is the number that
results when we change all 1’s to zeros and vice versa.

84. 1’s Complement

85. 2’s Complement

86. 2’s Complement

87. 9’s Complement

88. 10’s Complement

89. BOOLEAN ALGEBRA
EEE

90. Introduction

91. Application of Boolean algebra

92. AND operator

93. OR operator

94. NOT operator

95. Tautology & Fallacy

96. Logic Gates
• Boolean Algebra applied in computers electronic circuits. These
circuits perform Boolean operations and these are called logic
circuits or logic gates.
• A gate is an digital circuit which operates on one or more signals
and produce single output.
• Gates are digital circuits because the input and output signals are
denoted by either 1(high voltage) or 0(low voltage).
Three type of gates are as under:
1. AND gate
2. OR gate
3. NOT gate

97. AND gate

98. OR gate

99. NOT gate

100. Basic Theorems of Boolean Algebra

101. Basic Theorems of Boolean Algebra

102. Basic Theorems of Boolean Algebra

103. Basic Theorems of Boolean Algebra

104. Representation of Boolean expression
• Boolean expression can be represented by either
(i) Sum of Product( SOP) form
(ii) Product of Sum (POS form)
e.g. AB+AC - SOP
(A+B)(A+C) - POS
In above examples both are in SOP and POS respectively but
they are not in Standard SOP and POS.

105. Canonical form of Boolean Expression
(Standard form)
• In standard SOP and POS each term of Boolean expression must
contain all the literals (with and without bar) that has been used in
Boolean expression.
• If the above condition is satisfied by the Boolean expression, that
expression is called Canonical form of Boolean expression.
• In Boolean expression AB+AC the literal C is missing in the 1st
term AB and B is missing in 2nd term AC. That is why AB+AC is
not a Canonical SOP.

106. Canonical form of Boolean Expression
(Standard form)
• Convert AB+AC in Canonical SOP (Standard SOP)
AB + AC
=AB(C+C’) + AC(B+B’)
=ABC+ABC’+ABC+AB’C (Distributive law)
=ABC+ABC’+AB’C (Remove duplicates)

107. Canonical form of Boolean Expression
(Standard form)
• Convert (A+B)(A+C) in Canonical POS (Standard POS)
(A+B).(A+C)
=((A+B)+(C.C’)) .((A+C)+(B.B’))
=(A+B+C).(A+B+C’).(A+B+C)(A+B’+C)
(Distributive law)
=(A+B+C).(A+B+C’)(A+B’+C)
(Remove duplicates)

108. Minterm and Maxterm
• Individual term of Canonical Sum of Products (SOP) is called
Minterm. In other words minterm is a product of all the literals
(with or without bar) within the Boolean expression.
• Individual term of Canonical Products of Sum (POS) is called
Maxterm. In other words maxterm is a sum of all the literals (with
or without bar) within the Boolean expression.

110. From Logic to Gates
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111. Binary Quantities and Variables

112. Binary Quantities and Variables

113. Binary Quantities and Variables

114. Binary Quantities and Variables

115. Binary Quantities and Variables

116. Binary Quantities and Variables

117. Logic Gates

118. AND Gate
OR Gate

119. NOT Gate (an Inverter)
A logic buffer gate

120. NAND gate
NOR gate

121. Exclusive OR gate (XOR Gate)
Exclusive NOR gate (XNOR Gate)

122. Implementing a function from a Boolean
expression

123. Generating a Boolean expression from a logic
diagram

124. Example

125. Implementing a logic function from a truth table

127. NAND and NOR based
logic
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128. Universal Gates

129. Universal Gates

130. Simplification of Switching
Functions
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131. Minimization of Boolean Expression
• Canonical SOP (Sum of Minterms) and POS (Product of Maxterm)
is the derivation/expansion of Boolean Expression.
• Canonical forms are not usually minimal.
• Minimization of Boolean expression is needed to simplify the
Boolean expression and thus reduce the circuitry complexity as it
uses less number of gates to produce same output that can by taken
by long canonical expression.

132. Minimization of Boolean Expression
• Two method can by applied to reduce the Boolean expression –
i) Algebraic
ii) Using Karnaugh Map (K-Map).

133. Algebraic Method
• The different Boolean rules and theorems are used to simplify the
Boolean expression in this method.
• Minimize the following Boolean expression.
a’bc + ab’c’+ ab’c + abc’+ abc

134. Algebraic Method

135. Karnaugh Map (K-map)
• The Karnaugh map (K-map for short), Maurice Karnaugh's
1953 refinement of Edward Veitch's 1952 Veitch diagram, is a
method to simplify Boolean algebra expressions.
• K-Maps are a convenient way to simplify Boolean
Expressions.
• They can be used for up to 4 or 5 variables.
• They are a visual representation of a truth table.

136. Steps involved in
K-Map simplification
• Construction of K-map cells according to the
number of variables.
• Entering the min terms in the appropriate cell for
SOP form simplification.
• Grouping of minterms.
• Finding the final Expressions from each and
every group

137. Construction of K-map cells
• Total number of cell lies in the range of 2n
• “n” is the number of variables or literals
• For Example;
 If n=2, 2n = 22 = 4 cells
 If n=3, 2n = 23 = 8 cells
 If n=4, 2n = 24 = 16 cells

138. 2 Variables

139. 3 Variables

140. 4 Variables

141. Grouping in K-map
• Grouping of two adjacent cells (PAIR)
• Grouping of four adjacent cells (QUAD)
• Grouping of eight adjacent cells (OCTET)
NOTE:
• If all the minterms in a K-Map is grouped then
the value is “1”
• Maximum number of minterms in a single group
• Minimum number of Groups

142. 2 Variables

143. PROBLEMS
K – Map Simplification
• PROBLEM 1 - (2 variable)

144. PROBLEM 1 - (2 variable)

145. PROBLEM : 02 - (2 variable)
• ∑m (1, 2)

146. PROBLEM : 02 - (2 variable)
• ∑m (1, 2)

147. PROBLEM : 03 -(2 variable)
• Simplify the AND gate using K-map

148. 3 Variables

149. PROBLEM : 04 - (3 variable)
• Y = A’B’C + A’BC

150. PROBLEM : 05 - (3 variable)
• F(A,B,C) = ∑m(1,3,5,7)

151. PROBLEM : 06 - (3 variable)
• Y = AB’C’ + ABC’

152. PROBLEM : 07 - (3 variable)
• Y = A’B’C + A’BC + ABC

153. PROBLEM : 08- (3 variable)
• Y = A’B’C + A’BC + ABC + ABC’

154. PROBLEM : 09 - (3 variable)
• Y = ABC’ + ABC + AB’C’ + AB’C

155. PROBLEM : 10 - (3 variable)
• Simplify the logic function specified by the
truth table using K-map method. A,B,C are
inputs and Y is the output
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

156. PROBLEM : 10 - (3 variable)

157. PROBLEM : 11 - (3 variable)
• When all the min terms value is 1

158. 4 Variables

159. PROBLEM : 12 - (4 variables)
• Y = AB’CD + A’B’CD + ABCD + A’BCD

160. PROBLEM : 13 - (4 variable)
• f(A,B,C,D) = ∑m(0,2,4,5,6,7,8,10,12,13,14,15)

163. PROBLEM : 14 - (4 variable)
• f(A,B,C,D) = ∑m(0,2,8,10,12,14)

166. PROBLEM : 15 - (4 variable)
• f(A,B,C,D) = ∑m(9,10,11,12,13,14,15)

169. SOP with Don’t care condition
Simplify the Boolean Functions
F(A,B,C,D) = ∑m(1,3,7,11,15) + ∑d(0,2,5)

171. • Y = A’B’+CD

172. Simplify the Boolean Functions
F(A,B,C,D) = ∑m(5,7,8,10,13,15) + ∑d(0,1,2,3)

175. Y = BD + B’D’

176. • Implement the following truth table and find the
simplified expression.
INPUTS OUTPUT
A B C D O
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

180. Y = BC + CD’ + B’C’D

181. POS : Π M (0,6,7,8,12,13,14,15)

184. Y’ = AB + BC + B’C’D’

185. POS
Y’ = AB + BC + B’C’D’
Y = (A’+B’).(B’+C’).(B+C+D)

186. POS : Π M (0,6,7,8,12,13,14,15)

187. Y = (A’+B’).(B’+C’).(B+C+D)

188. References
NPTEL – DIGITAL CIRCUITS
PROF.SANTANU CHATTOPADHYAY
Department of Electrical Engineering
IIT Kharagpur
TEXT BOOK:
“Digital Design” by Morris Mano, 12th Edition,
Pearson Education Ltd (2012)