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DYNAMIC RANDOM
ACCESS MEMORY
TABLE OF
CONTENTS
What is a DRAM?
Organization of a DRAM chip
DRAM operations
• Asynchronous
• Synchronous
• Graphic
The different types of DRAMs:
DRAM scaling challenges
Advantages of DRAM over SRAM
WHAT IS IT?
WHERE ON MOTHERBOARD?
DRAM ORGANIZATION
Channel
DIMM
Rank
Chip
Bank
Row
Column
CHANNEL DIMM
R A N K 0
Side
View
DIMM
R A N K 1
RANKS, BANKS, ROWS AND COLUMNS
DRAM CHIP WITH 4 BANKS
DRAM SYSTEM ORGANIZATION
THE DIFFERENT
OPERATIONS
WRITING
Step1: word line = 1
Step 2: give a value to the bit
line (applying voltage)
Step 3: transfer of value to the
capacitor (charge or discharge)
READING
Step 1: word
line = 1
01
Step 2:
distribution of
the charge of
the capacitor to
thee bit line
02
Step 3: change
of the value at
the bit line
03
Step 4: charge
to the Vdd of
the bit line to be
interpreted at
thee output
04
DRAM REFRESH



DIFFERENT TYPES OF DRAMS
ASYNCHRONOUS SYNCHRONOUS GRAPHIC
ASYNCHRONOUS
SYNCHRONOUS



DOUBLE DATA RATE SDRAM
DDR5 RAM
WHY IS
ASYNCHRONOUS
PHASED OUT?

GRAPHIC


DRAM SCALING
CHALLENGES



DRAM PROCESS
SIZES SHRANK
SIGNIFICANTLY
IN RECENT
YEARS,
UNTIL 2016.
40nm
2008
30nm
2010
20nm
2011
10nm
Oct. 2016
CLOSER LOOK AT DRAM AND SRAM
















THANK YOU!

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DRAM