The document discusses the design and verification of several digital logic circuits using Verilog including full adders, finite state machines, encoders, decoders, arithmetic logic units (ALUs), barrel shifters, and stacks. It provides the results of testing and verifying 16-bit and 4-bit full adders, Moore and Mealy finite state machines, an 8-bit encoder, an 8-to-1 decoder, 12-bit two's complement ALUs, an 8-bit barrel shifter, a push-pop stack, and an ALU tester.

1. DIGITAL LOGIC AND
VERILOG

2. GRAPHIC INPUT
RTL
Diagram for
the circuit

3. GRAPHIC INPUT -RESULTS

4. FULL ADDERS – 16 BIT AND 4 BIT

5. FULL ADDERS – 16 BIT AND 4 BIT –
VERIFICATION RESULTS

6. FINITE STATE MACHINE- MOORE

7. FINITE STATE MACHINE- MOORE –
VERIFICATION RESULTS

8. FINITE STATE MACHINE- MEALY

9. FINITE STATE MACHINE- MEALY –
VERIFICATION RESULTS

10. ENCODER 3:8 BIT

11. DECODER 8:1 TEST RESULTS

12. 12 BIT TWO’S COMPLEMENT ALU
TEST RESULTS -1

13. 12 BIT TWO’S COMPLEMENT ALU
TEST RESULTS -2

14. 12 BIT TWO’S COMPLEMENT ALU
TEST RESULTS -3

15. 12 BIT TWO’S COMPLEMENT ALU
TEST RESULTS -4

16. 8 BIT BARREL SHIFT REGISTER

17. 8 BIT BARREL SHIFT REGISTER –
TEST RESULT

18. STACK – PUSH AND POP

19. ALU TESTER

20. ALU TESTER – VERIFICATION AND
TEST RESULT