1) The document describes a digital I/Q loop used for accelerating cavities. It uses frequency down conversion, baseband modulation, and an FPGA for correction. 2) Key components include an I/Q modulator for 362.202MHz single sideband generation, down conversion to 10MHz, and a Hittite modulator for 352.202MHz baseband modulation. 3) Software used includes MATLAB, Simulink, and Xilinx for the FPGA design. Signal theory concepts like complex baseband representation are discussed for the bandpass to complex baseband conversion.

1. Digital I/Q loop
1
Digital I/Q loop for accelerating cavities
Technical document

2. Digital I/Q loop
2
Contents
I I/Q loop description........................................................................................................................................................................4
I.1 I/Q loop.....................................................................................................................................................................................4
I.2 Low level Hardware description ...............................................................................................................................................5
II Synoptic..........................................................................................................................................................................................6
III Frequency down conversion .....................................................................................................................................................7
III.1 EMHISER TELE-TECH Inc I/Q modulator ........................................................................................................................7
III.2 362.202 MHz SSB Synoptic ................................................................................................................................................8
III.3 362.202MHz Band pass filter...............................................................................................................................................9
III.4 Down conversion 352.202MHz to 10MHz IF...................................................................................................................11
IV 352.202 MHz base band modulation.......................................................................................................................................13
IV.1 Hittite Modulator................................................................................................................................................................13
IV.1.1 Specifications ................................................................................................................................................................13
IV.2 Electronic Interface and modulator ....................................................................................................................................13
V Software and hardware used.........................................................................................................................................................15
V.1 Hardware:...........................................................................................................................................................................15
V.2 Software:............................................................................................................................................................................15
VI Signal Theory..........................................................................................................................................................................16
VI.1 Complex Base band representation of a band pass signal ..................................................................................................16
VII Band pass to complex Base band conversion..........................................................................................................................17
VIII Simulink Design......................................................................................................................................................................17
VIII.1 First method: Using a DDS ................................................................................................................................................17
VIII.2 Second method: I/Q sampling Method...............................................................................................................................18
VIII.3 Sign detection and down conversion around zero ..............................................................................................................19
IX Phase rotator ...........................................................................................................................................................................21
X Sum of the Two Cavities ..............................................................................................................................................................22
XI Controller Structure.................................................................................................................................................................22
Controller Transfer function:............................................................................................................................................................22
XI.1 W transform ......................................................................................................................................................................23
XI.2 Final Controller Structure...................................................................................................................................................25
XI.3 Translation to DAC............................................................................................................................................................26
XII Band Pass Signal.....................................................................................................................................................................27
XII.1 Definition ...........................................................................................................................................................................27
XII.2 Transmission through a linear time-invariant system ........................................................................................................28
XII.2.1 Band pass filter............................................................................................................................................................28
XII.2.2 Transmission through a band pass filter ...............................................................................................................28
XII.3 Band pass filter is a cavity..................................................................................................................................................29
XII.3.1 Find transfer function of hI(t) and hQ(t).......................................................................................................................30
XII.3.2 Using simulink control system toolbox.......................................................................................................................35
XII.4 Root locus of the close loop and open loop bode ...............................................................................................................36
XIII Conclusion ..............................................................................................................................................................................37

3. Digital I/Q loop
3
Bibliography
Haugen, F. (2005). Discrete-time signals and systems. discrete.pdf.
Complex Baseband Representation of Band pass Signals by Mike Fitz, UCLA
Complex Signal Processing is Not — Complex Ken Martin Dept. of Elect. and Comp. Engr., Univ. of Toronto
Garoby R. Low Level RF and Feedback CERN PS/RF
G.Gautier Wednesday, May 04, 2016

4. Digital I/Q loop
4
I I/Q loop description
I.1 I/Q loop
Error! Reference source not found.shows the I/Q modulation and I/Q demodulation synoptic. This I/Q loop is
made up of four parts. The first part is the 362.202MHz single side band generation. This part allows doing a down
conversion from 352.202 MHz to 10MHz. The second part is the down conversion, the third is the FPGA correction and
finally the fourth part is the I/Q modulation performs by Hittite HMC497LP4E. The RF plant is constituted of a solid
state amplifier and a warm radiofrequency cavity.
Figure 1 I/Q loop synoptic

5. Digital I/Q loop
5
Figure 2 loop synoptic, more details
I.2 Low level Hardware description
The synoptic next page shows the low level hardware (FPGA is not included in this drawing)
1. 362.202 MHz Single Sind band generation
2. Down conversion to 10MHz
3. Base band modulation

6. Digital I/Q loop
6
II Synoptic

7. Digital I/Q loop EMHISER TELE-TECH Inc I/Q modulator
ESRF Page 7
IIIFrequency down conversion
III.1 EMHISER TELE-TECH Inc I/Q modulator
Used to create the 362.202MHz sideband

8. Digital I/Q loop 362.202 MHz SSB Synoptic
ESRF Page 8
III.2 362.202 MHz SSB Synoptic
10MHz + DC signal
10MHz + DC signal
Input 352.202MHz
Output 362.202MHz
Bias Tee
DC signal
90 degree hybrids
Input 10MHz
I/Q modulator
50 Load
DC Offset

9. Digital I/Q loop //362.202MHz Band pass filter
ESRF Page 9
III.3 362.202MHz Band pass filter
It is used to suppress the spurious frequencies after modulation.
 Master source 352.202MHz local oscillator frequency spectrum.

10. Digital I/Q loop //362.202MHz Band pass filter
ESRF Page 10
 Output 362.202MHz spectrumbefore filtering
 362.202 MHz spectrum filtering

11. Digital I/Q loop Down conversion 352.202MHz to 10MHz IF
ESRF Page 11
III.4 Down conversion 352.202MHz to 10MHz IF

12. Digital I/Q loop Down conversion 352.202MHz to 10MHz IF
ESRF Page 12

13. Digital I/Q loop Hittite Modulator
ESRF Page 13
IV 352.202 MHz base band modulation
The base band correction signal modulate the 352.202MHz
IV.1 Hittite Modulator
IV.1.1 Specifications
hmc497lp4 Hittite modulator specifications
IV.2 Electronic Interface and modulator
Baseband signal
from DAC A
Baseband signal
from DAC B
352.202MHz input
Modulated 352.202MHz output

14. Digital I/Q loop Electronic Interface and modulator
ESRF Page 14
Designation
Brand or
distributor
reference
Amplificateur Mini-circuits ZX60-14012L+
Amplificateur Mini-circuits ZFL-1000H
Step attenuateur Mini-circuits ZX76-15R5-PP+
Mixer LO 17 dBm Mini-circuits TAK-1WH +
Bias Tee Mini-circuits ZFBT-4R2GW
I/Q modulator
EMHISER TELE-TECH
Inc
9211-44
Coupler hybrid 90 Pulsar (Elyte) 90 Q3-01-412
10MHz Filter Band pass Elythe B10-4/T-7C1FS
352.202 Mhz filter band
pass
Elythe
TB352-10-
4ACSJ
362.202 Mhz filter band
pass
Elythe BP21/362.202-9
Power Splitter Mini-circuits ZX10Q-2-12
I/Q modulator Hittite HMC 497 LP4E
Directional coupler Mini-circuits ZEDC-15-2B

15. Digital I/Q loop Hardware:
ESRF Page 15
V Software and hardware used
V.1 Hardware:
HERON Module with 200K/1M gate FPGA: Virtex 2V1000fg456-4
2 channels of 125Mhz 12 bit A/D
2 channels of 125Mhz 14 bit D/A
V.2 Software:
MATLAB Version 7.5.0.342 (R2007b)
MATLAB License Number: 143600
Operating System: Microsoft Windows XP Version 5.1 (Build 2600: Service Pack 3)
Java VM Version: Java 1.6.0 with Sun Microsystems Inc. Java HotSpot(TM) Client VM mixed mode
MATLAB Version 7.5 (R2007b)
Simulink Version 7.0 (R2007b)
Control System Toolbox Version 8.0.1 (R2007b)
Filter Design Toolbox Version 4.2 (R2007b)
Signal Processing Blockset Version 6.6 (R2007b)
Signal Processing Toolbox Version 6.8 (R2007b)
Simulink Control Design Version 2.2 (R2007b)
Symbolic Math Toolbox Version 3.2.2 (R2007b)
System Identification Toolbox Version 7.1 (R2007b)
Xilinx System Generator Version 10.1.3 build 1386
ISE 10.1.03

16. Digital I/Q loop Complex Base band representation of a band pass signal
ESRF Page 16
VI Signal Theory
VI.1 Complex Base band representation of a band pass signal1
A pure sine wave signal can be consider like a analytic signal (or a complex base band signal) modulated by a
carrier frequency. The signal can be write where is the carrier frequency. is name a
band pass signal.
The energy spectrum is always symmetric
around f =0.
with :
In phase signal: I
Quadrature signal:Q
Figure 3
Finally
Eq 1
If we want to demodulate we have to obtain the and components of the signal
1
Théorie et traitement des signaux (F. de Coulon) dunod
Théorie et Applications de la notion de signal analytique (J.Ville)
The Ohio State University (Michael P.Fitz) Complex Baseband Representation

17. Digital I/Q loop First method: Using a DDS
ESRF Page 17
VII Band pass to complex Base band conversion
Figure 4 shows the method to
obtain the two components I and Q
from a band pass signal. The signals
cosines and sinus must have the same
frequency than the band pass signal
in order to translate the band pass
frequency spectrum around f=0. Two
low pass filters are needed to
eliminate the harmonics due to the
multiplication.
Figure 4
There are several ways to perform this conversion. Here we will show two methods.
One is directly inspire by the
Figure 4 and the other is name I/Q sampling Method.
VIII Simulink Design
VIII.1 First method: Using a DDS2
Figure 5 Conversion using DDS
2
Direct Digital Synthesizer

18. Digital I/Q loop Second method: I/Q sampling Method
ESRF Page 18
In Figure 5 a DDS is use to generate the Sinus and Cosine signal to the right frequency. Two CIC3
filter are use to
low pass filtering.
The important restriction for this design is that the value of the carrier frequency must be o power of 2. If this condition
is not respected there will be a `battement` between the two frequencies.
This design has been cancelled for our application. The carrier frequency which comes from a down conversion has a
value of 10MHz
VIII.2 Second method: I/Q sampling Method
The I/Q sampling method is simple method. We only need two D registers.
The
Figure 6 details the method
used to obtain the I and Q signal
from a real signal.
V2 is the analogue input
signal (10 MHz) which fed the
ADC.
V1 is the ADC frequency
sampling.
In Green is the representation of an
ideal sampling.
V3 shows the effect of a real
sampling. The data is sampling
during the rising edge of the clock
and hold at the same value until the
next rising edge of the clock.
The frequency clock must be four
time higher than the input signal in
order to have four samples per
period. Each sample is separate
from the other by a pi/2 angle. So
S1 = -S3, S2 = -S4
Figure 6
Now the goal is to obtain two distinct signals. One signal witch com from S1,S3 and the other comes from S2, S4. In
orde to separate the signals we have to generate a 20MHz clock with its opposite. This clock derive from the 40MHz
clock.
3
CIC Filter Introduction Matthew P. Donadio

19. Digital I/Q loop Sign detection and down conversion around zero
ESRF Page 19
Figure 7 I/Q Sampling
VIII.3 Sign detection and down conversion around zero
Before to realize the down conversion (or
rectification), we have needed a time reference inside the
design. This reference will used to fix the right quadrant
(see Figure 8). So the first step is to test the sign of the
signal I and Q.
A clock at 10MHz samples the signal I and Q in order to
test the sign. The sign is tested by threshold 1 and
threshold 2 (see
Figure 9). The output of threshold 1 and 2 is equal to -1
when the input is negative. The result is used has a
multiplexer input control (see Figure 10).
Figure 8
To understand the rectification, it is essential to know
that phase is stable during many 10MHz clock periods
One clock cycle before the rectification, we test the I
and Q signal sign. This test is used to control the
rectification multiplexer
If sign is negative the signal sample will be multiplied
by -1 if the sample is positive and by 1 if the sample is
negative (see Figure 10 Rectification)
Figure 9 Sign detection

20. Digital I/Q loop Sign detection and down conversion around zero
ESRF Page 20
Figure 10 Rectification
The Figure 11 shows how the process runs in case of a phase step
Figure 11

21. Digital I/Q loop Sign detection and down conversion around zero
ESRF Page 21
IX Phase rotator
Phase rotator will be used to calibrate the loop
We used the Eq 2 to change the phase of the I/Q component
Figure 12 Shows the Simulink realization of the rotation matrix.
The Calibration function is to set the I and Q value before to close
the loop.
Eq 2
Figure 12

22. Digital I/Q loop Sign detection and down conversion around zero
ESRF Page 22
X Sum of the Two Cavities
XI Controller Structure
In first approach, we will used the simplest form of a Proportional and integral controller.
Eq 3
The integral is expressed by time Ti, which represents the time required for the change in the output (u) is equal to that
of the input (e)
Laplace transforme
Eq 4
Controller Transfer function:
Eq5
Z transform used for a integration is :
thus or
avec
Recursion equation:

23. Digital I/Q loop W transform
ESRF Page 23
XI.1 W transform 4
Fictive pulsation ν of the W transform:
4
Transformation conform
w(n)

24. Digital I/Q loop W transform
ESRF Page 24
We can see that the transfer function is an integrator and a zero

25. Digital I/Q loop Final Controller Structure
ESRF Page 25
XI.2 Final Controller Structure
1) one integration
2) A zero to cancel the cavity HI pole
fc = 9.1481e+003 Hz
3) A gain k
Kp = 1 ki =
10
2
10
3
10
4
10
5
10
6
10
7
-360
-315
-270
-225
-180
-135
-90
-45
0
P.M.: 79 deg
Freq: 4.54e+004 Hz
Frequency (Hz)
Phase(deg)
-40
-20
0
20
40
60
G.M.: 18.2 dB
Freq: 3.7e+005 Hz
Stable loop
Open-Loop Bode
Magnitude(dB)
Cavity pole and zero compensation

26. Digital I/Q loop Translation to DAC
ESRF Page 26
XI.3 Translation to DAC
The data inside the FPGA is fix point 14.13 (signed, 2’s comp). The fractional part is 13bits and the integer part is 1bits.
binary Decimal Integer . Xor with 8192
Unsigned
Hex
01111111111111 +0 .9998779296875Volt 8191 16383 3FFF
00000000000000 0 Volt 0 8192 2000
10000000000000 -1 Volt -8192 0 0000
The D/A’s analogue output level is related to the input digital value as shown in the table below. Each of the D/As are
connected to the FPGA directly, which must provide 14 bit data in offset binary format
Input Dec Input Hex Input binary Analog Output
0 0000 00000000000000 -1 Volt
8191 1FFF 01111111111111 0 Volt
16383 3FFF 11111111111111 +1 Volt
Figure 13 Translation to DAC

27. Digital I/Q loop Definition
ESRF Page 27
XII Band Pass Signal
XII.1 Definition
Band pass signal is:
is the base band signal
with :
In phase signal
Quadrature signal
Eq 7

28. Digital I/Q loop Transmission through a linear time-invariant system
ESRF Page 28
XII.2 Transmission through a linear time-invariant system 567
This is a detail of a calculus already performed by Gary R from CERN
XII.2.1 Band pass filter
with
Eq 8
Eq 9
XII.2.2 Transmission through a band pass filter
 Definition
In other words, the base band signal is modulated by the carrier signal
 Complex Base band signal
 Complex band pass signal
5
Garoby R. Low Level RF and Feedback CERN PS/RF
6
Complex Baseband Representation of Band pass Signals by Mike Fitz, UCLA
7
Complex Signal Processing is Not — Complex Ken Martin Dept. of Elect. and Comp. Engr., Univ. of Toronto

29. Digital I/Q loop Band pass filter is a cavity
ESRF Page 29
 Real band pass signal
Eq 10
XII.3 Band pass filter is a cavity

30. Digital I/Q loop Band pass filter is a cavity
ESRF Page 30
Resonator impedance:
We reorganize the transfer function in order to find the Laplace inverse transform:
Rs = 25.8MΩ
Q = 38500
F = 352.202MHz
Band width around
9kHz
Eq 11
XII.3.1 Find transfer function of hI(t) and hQ(t)

31. Digital I/Q loop Band pass filter is a cavity
ESRF Page 31
XII.3.1.1 hI(t)
Eq 12
XII.3.1.2 hQ(t)
XII.3.1.3 Laplace transform of hI(t) and hQ(t)
and
After filtering the terms
Eq 13

32. Digital I/Q loop Band pass filter is a cavity
ESRF Page 32
Eq 14
Parameters cavities 352202000
Rs 26.8MΩ
Q0 38500
σ 28739.68

33. Digital I/Q loop Band pass filter is a cavity
ESRF Page 33
XII.3.1.4 Z transform of HI(p) and HQ(p) (Haugen, 2005)
Figure 14 Hi(p) R
Figure 15 Hq(p) R
The effect of the Hq(p) can be neglected compare with the direct path Hi(p). For the simulation of the loop, I will
use Hi(p) or Hi(z).

34. Digital I/Q loop Band pass filter is a cavity
ESRF Page 34
XII.3.1.5 HI(p) Z transform for simulink simulation
Figure 16
8
In order to increase the bandwidth of the loop, we need to cancel the pole of the cavity and add a dominant pole
to the controller. This dominant pole sets the response of the loop.
Controller structure must have:
4) one or more integration
5) A zero to cancel the HI pole
6) A gain K
7) A pole in order to set le behaviour in close loop
So
Close loop characteristic equation
8

35. Digital I/Q loop Band pass filter is a cavity
ESRF Page 35
XII.3.2 Using simulink control system toolbox
Matalb simulink control system toolbox provides all the necessary tools to tune a loop.
% ---------- Hi(z ) -----------------------------------------------
% First method to convert Hi(p) to Hi(z)-------------------
display(' Cavity (c2d)');
sys_Hi_z = c2d(sys_Hi,Ts,'zoh')
% Second method to convert Hi(p) to Hi(z)-------------------
pole_Hi_z = exp(-sigma_*Ts);
num_Hi_z = [1-pole_Hi_z];
den_Hi_z = [1 -pole_Hi_z];
display(' Cavity (tf)');
sys_Hi_z = tf(num_Hi_z,den_Hi_z,Ts)
Figure 17 Hi(p) green and Hi(z) blue

36. Digital I/Q loop Root locus of the close loop and open loop bode
ESRF Page 36
XII.4 Root locus of the close loop and open loop bode
Figure 18 Simulink simulation: Controller and cavity
Rule for pole placement
1) Not too near of the unity circle because a small variation of the system should cause an instability
2) Not too near the point 1.
3) No negative poles
kc
1
k_Hi
k_Hi
Pulse
Generator1
Kout
1
Kf
1
Corrector
sys_C
Cavity
sys_Hi_z

37. Digital I/Q loop Root locus of the close loop and open loop bode
ESRF Page 37
XIII Conclusion
The loop has been installed and finally a single loop controlled two cavities.
After 3 years of run, we decided to change the regulation. Many reasons motivated this decision.
1. The system was complex and it was difficult for the person in standby apprehend the system. In others words,
it was difficult to find the solution in case of break down.
2. At this end of this 3 year, The manufacturer of the FPGA board stops his activities.
3. Xilinx has frozen the ISE to ISE 10.1 for the Virtex 2.
4. ISE 10.1 was frozen for XP
5. And XP is now gave up by Microsoft
6. The design chain is complex and requires specialist people. The major problems are generally not where you
expect them. To much upgrade of software for a insignificant profit.
Design reasons
1. It was not a good idea to stay in I/Q signal for the loop because the same controller was used for the signal I
and the signal Q. And in this case, we have the same parameters for the phase loop and the magnitude loop.
The two loops were not independent. In order to have two independent loops, we should have to transform the
signals I and Q in two signals phase and amplitude (Cordic algorithm).
2. The Hittite I/Q modulator was not perfect. An amplitude variation led a phase variation so it was not easy to
tuning the system.
In October 2015 we have changed the Digital loop by two analog loops which using the same features. We obtain the
same result with the analog loops.
We know that the fashion leads to use digital I/Q loops. But we think that the real benefice of the I/Q loop will be reach
when we will able to sampling directly the RF signal without use RF down conversion stage.
Flexibility is used as argument is use for the digital loops. But in the real life for systems which run continuously the
persons who program such systems become more and more reticent to change often the code.
The analog loops run perfectly since two years without break down.
Out1
1
p1plus_1
p1+1
p1
p1
k
k
alpha
alpha
Integer Delay4
-1
Z
Integer Delay3
-1
Z
Integer Delay2
-1
Z
Integer Delay1
-1
Z
In1
1