This document provides an overview and summary of key points from a lecture on massively parallel computing using CUDA. The lecture covers CUDA language and APIs, threading and execution models, memory and communication, tools, and libraries. It discusses the CUDA programming model including host and device code, threads and blocks, and memory allocation and transfers between the host and device. It also summarizes the CUDA runtime and driver APIs for launching kernels and managing devices at different levels of abstraction.

1. Massively Parallel Computing
CS 264 / CSCI E-292
Lecture #4: Intermediate-level CUDA | February 15th, 2011
Nicolas Pinto (MIT, Harvard)
pinto@mit.edu

2. Administrivia
• HW1: due Fri 2/18/11 (this week)
• Projects: think about it, consult the staff
• New guest lecturers!
• Max Lin (Google), Kurt Messersmith et al. (Amazon),
David Rich et al. (Microsoft)

3. During this course,
r CS264
adapted fo
we’ll try to
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and use existing material ;-)

4. Today
yey!!

5. Outline
• CUDA Language & APIs (overview)
• Threading/Execution (cont’d)
• Memory/Communication (cont’d)
• Tools
• Libraries

6. Outline
• CUDA Language & APIs (overview)
• Threading/Execution (cont’d)
• Memory/Communication (cont’d)
• Tools
• Libraries

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© NVIDIA Corporation 2010 5
4
Unit of Least Precision (ULP) is the gap between the floating-point
numbers nearest a given real number

12. A PI
CUDA APIs
API allows the host to manage the devices
Allocate memory & transfer data
Launch kernels
High level of abstraction - start here!
(aka “Device” API)
More control, more verbose
(OpenCL: Similar to CUDA C Driver API)
© NVIDIA Corporation 2010

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17. Runtime API
(high-level)

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21. “Device” Driver API
(low-level)

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32. Outline
• CUDA Language & APIs (overview)
• Threading/Execution (cont’d)
• Memory/Communication (cont’d)
• Tools
• Libraries

33. Threading Hierarchy
Execution Model
Software Hardware
Threads are executed by thread
Thread
processors
Processor
Thread
Thread blocks are executed on
multiprocessors
Thread blocks do not migrate
Several concurrent thread blocks can
Thread reside on one multiprocessor - limited
Block Multiprocessor by multiprocessor resources (shared
memory and register file)
A kernel is launched as a grid of
thread blocks
...
Only one kernel can execute on a
Grid device at one time
Device
© 2008 NVIDIA Corporation.

34. Thread Batching
Kernel launches a grid of thread blocks
Threads within a block cooperate via shared memory
Threads within a block can synchronize
Threads in different blocks cannot cooperate
Allows programs to transparently scale to
different GPUs
Grid
Thread Block 0 Thread Block 1 Thread Block N-1
…
Shared Memory Shared Memory Shared Memory
© 2008 NVIDIA Corporation.

35. Transparent Scalability
Hardware is free to schedule thread blocks on any
processor
A kernel scales across parallel multiprocessors
Kernel grid
Device Device
Block 0 Block 1
Block 2 Block 3
Block 4 Block 5
Block 0 Block 1 Block 0 Block 1 Block 2 Block 3
Block 6 Block 7
Block 2 Block 3 Block 4 Block 5 Block 6 Block 7
Block 4 Block 5
Block 6 Block 7
© 2008 NVIDIA Corporation.

36. Thread Arithmetic

37. Indexing Arrays: Example
In this example, the red entry would have an index of 21:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
M = 8 threads/block
blockIdx.x = 2
int index = threadIdx.x + blockIdx.x * M;
= 5 + 2 * 8;
= 21;

38. Indexing Arrays: Example
In this example, the red entry would have an index of 21:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
M = 8 threads/block
Addition with Threads and Blocks blockIdx.x = 2
int index = threadIdx.x + blockIdx.x * M;
The blockDim.x is a built-in variable for threads per block:
= 5 + 2 * 8;
int index= threadIdx.x + blockIdx.x * blockDim.x;
= 21;
A combined version of our vector addition kernel to use blocks and threads:
__global__ void add( int *a, int *b, int *c ) {
int index = threadIdx.x + blockIdx.x * blockDim.x;

39. Control Flow

40. Control Flow Divergence
What happens if you have the following code?
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/
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41. Control Flow Divergence
Branch
Path A
Path B

42. Control Flow Divergence
Nested branches are handled as well
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43. Control Flow Divergence
Branch
Branch
Path A
Path B
Path C

44. Control Flow Divergence
for correctness (*)
You might have to think about it for performance
Depends on your branch conditions

45. Control Flow Divergence
Performance drops off with the degree of divergence
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...
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...
7

46. Divergence
35
30
Performance
25
20
15
10
5
0
0 2 4 6 8 10 12 14 16 18
Divergence

47. Occupancy

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© NVIDIA Corporation 2010

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© NVIDIA Corporation 2010

50. Outline
• CUDA Language & APIs (overview)
• Threading/Execution (cont’d)
• Memory/Communication (cont’d)
• Tools
• Libraries

51. Kernel Memory Access
Kernel Memory Access
Per-thread
Registers On-chip
Thread
Local Memory Off-chip, uncached
Per-block
Shared • On-chip, small
Block • Fast
Memory
Per-device
Kernel 0 ... • Off-chip, large
• Uncached
Global • Persistent across
Time
Memory kernel launches
Kernel 1 ... • Kernel I/O

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55. Global Memory
Kernel Memory Access
• Different types of “global memory”
Per-thread
Registers On-chip
• Linear Memory Thread
Local Memory Off-chip, uncached
• Texture
Per-block Memory
• Constant Memory
Block
•
•
Shared
Memory
On-chip, small
Fast
Per-device
Kernel 0 ... • Off-chip, large
• Uncached
Global • Persistent across
Time
Memory kernel launches
Kernel 1 ... • Kernel I/O

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=3*<+,.4;(>(?@;;4:A(B3C,;43(/$$0

58. Constant Memory
Constants set by CPU, read by GPU
Each SM has 8kiB cache for constants
Optimized for broadcast
Accessing different elements forces serialisation
Can speed some calculations
Can relieve register pressure

59. Constant Memory
Declared at file scope
__constant__ float dc_myConst;
Set via cudaMemcpyToSymbol API call
cudaMemcpyToSymbol( “dc_myConst”, 3.14f, sizeof(float) )
Accessed by name in kernel
__global__ MyKernel( ... ) {
....
float myVal = dc_myConst+1;
....
}

60. Textures
Textures are essentially look up tables
Can only be written by the host
Cached on each multiprocessor (8kiB)
Optimised for 2D spatial locality
Hardware interpolation possible
Limited precision
Can clamp or wrap at boundaries

61. Textures
Declaration and setup rather involved
See programming guide
Accessed in kernels via texture fetches:
tex1D, tex2D, tex3D, etc.
Co-ordinates at texel centres
Have to take care when accessing elements

62. Textures
Can improve load coalescing from global memory
If whole texture fits in 8kiB cache, has grid lifetime
Clamping/wrapping can aid edge case handling
Have to test to determine benefits

63. General Principles
Memory access patterns are crucial
Even CPUs are typically memory bound
GPUs have 100x FP
Only 10x memory bandwidth
Have to keep the GPU busy

64. PC Architecture
8 GB/s
>?@
?>L9G=2%&66"K16
J%+8#"F7(&"K16
H%'2$7,6">'%("I"
A+%#$)%7(B& F+1#$)%7(B&
>@C!
E&.+%/"K16 ?>L"K16
3+ Gb/s
CD!E F!:! G#$&%8&# !
160+ GB/s
to
VRAM 25+ GB/s
modified from Matthew Bolitho

65. PCIe Transfers
(first thing to optimize?)

66. !"#$%&'()##*+&%,
-+#"(4&5&(6*+3(
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67. Processing Flow
PCI Bus
1. Copy input data from CPU memory to GPU
memory
© NVIDIA Corporation 2010

68. Processing Flow
PCI Bus
1. Copy input data from CPU memory to GPU
memory
2. Load GPU program and execute,
caching data on chip for performance
© NVIDIA Corporation 2010

69. Processing Flow
PCI Bus
1. Copy input data from CPU memory to GPU
memory
2. Load GPU program and execute,
caching data on chip for performance
3. Copy results from GPU memory to CPU
memory
© NVIDIA Corporation 2010

70. PCIe Transfers
PCIe 2.0 x16 bus has
Latency of 10 µs (observed)
Bandwidth of 8GB/s (theory), 5 GB/s (observed)
A lot of calculations can happen in these times

71. PCIe Transfers
PCIe transfers occur via DMA
GPU reads pages direct from CPU memory
Very bad if page gets moved mid-transfer
CUDA maintains internal pinned memory buffers
Used for cudaMemcpy calls
Data staged through these

72. !"#$%&'#'()*+(#$,-'#)
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81. Scheduling on GPU
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86. PCIe Transfers Optimization
PCIe bus is slow
Try to minimize transfers
Use pinned memory on host whenever possible
Try to perform copies asynchronously

87. Outline
• CUDA Language & APIs (overview)
• Threading/Execution (cont’d)
• Memory/Communication (cont’d)
• Tools
• Libraries

88. CUDA-GDB
Extended version of GDB with support for C for CUDA
Supported on Linux 32bit/64bit systems
Seamlessly debug both the host|CPU and device|GPU code
Set breakpoints on any source line or symbol name
Single step executes only one warp except on sync threads
Access and print all CUDA memory allocations, local, global,
constant and shared vars.
Walkthrough example with sourcecode : CUDA-GDB manual
© NVIDIA Corporation 2010

89. Linux GDB
Integration with
EMACS
© NVIDIA Corporation 2010

90. Linux GDB
Integration with
DDD
© NVIDIA Corporation 2010

91. CUDA-MemCheck
Detects/tracks memory errors
Out of bounds accesses
Misaligned accesses (types must be aligned on their size)
Integrated into CUDA-GDB
Linux and WinXP
Win7 and Vista support coming
© NVIDIA Corporation 2010
11
©NVIDIA 2010

92. CUDA Driver Low-level Profiling support
1. Set up environment variables
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!"#$%&'()*+,-./0123,2/94#%$<=@!?:AB
2. Set up configuration file
FILE "config.txt": FILE "profile.csv":
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3. Run application 55H<S!DD5I!TNLLIOE!E:#RU&$*OV?TLJO5L?III
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4. View profiler output HL
55H<S!DD5I<SSTDIOE!E:#R*&$UOV?VVWOTW?III
© NVIDIA Corporation 2010

93. CUDA Visual Profiler - Overview
Performance analysis tool to fine tune CUDA applications
Supported on Linux/Windows/Mac platforms
Functionality:
Execute a CUDA application and collect profiling data
Multiple application runs to collect data for all hardware performance counters
Profiling data for all kernels and memory transfers
Analyze profiling data
© NVIDIA Corporation 2010

94. CUDA Visual Profiler data for kernels
© NVIDIA Corporation 2010

95. CUDA Visual Profiler computed data for kernels
Instruction throughput: Ratio of achieved instruction rate to peak single issue instruction rate
Global memory read throughput (Gigabytes/second)
Global memory write throughput (Gigabytes/second)
Overall global memory access throughput (Gigabytes/second)
Global memory load efficiency
Global memory store efficiency
© NVIDIA Corporation 2010

96. CUDA Visual Profiler data for memory transfers
Memory transfer type and direction
(D=Device, H=Host, A=cuArray)
e.g. H to D: Host to Device
Synchronous / Asynchronous
Memory transfer size, in bytes
Stream ID
© NVIDIA Corporation 2010

97. CUDA Visual Profiler data analysis views
Views:
Summary table
Kernel table
Memcopy table
Summary plot
GPU Time Height plot
GPU Time Width plot
Profiler counter plot
Profiler table column plot
Multi-device plot
Multi-stream plot
Analyze profiler counters
Analyze kernel occupancy
© NVIDIA Corporation 2010

98. CUDA Visual Profiler Misc.
Multiple sessions
Compare views for different sessions
Comparison Summary plot
Profiler projects save & load
Import/Export profiler data
(.CSV format)
© NVIDIA Corporation 2010

99. Outline
• CUDA Language & APIs (overview)
• Threading/Execution (cont’d)
• Memory/Communication (cont’d)
• Tools
• Libraries

100. CUBLAS

101. CUBLAS
CUDA accelerated BLAS (Basic Linear Algebra
Subprograms)
Create matrix and vector objects in GPU memory space
Fill objects with data
Call sequence of CUBLAS functions
Retrieve data from GPU (optionally)
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© NVIDIA Corporation 2009

102. CUBLAS Features
Single precision data:
Level 1 (vector-vector O(N) )
Level 2 (matrix-vector O(N2) )
3
Level 3 (matrix-matrix O(N ) )
Complex single precision data:
Level 1
CGEMM
Double precision data:
Level 1: DASUM, DAXPY, DCOPY, DDOT, DNRM2,
DROT, DROTM, DSCAL, DSWAP, ISAMAX, IDAMIN
Level 2: DGEMV, DGER, DSYR, DTRSV
Level 3: ZGEMM, DGEMM, DTRSM, DTRMM, DSYMM,
DSYRK, DSYR2K
© NVIDIA Corporation 2009

103. CUBLAS Performance: CPU vs GPU
CUBLAS: CUDA 2.3, Tesla C1060
MKL 10.0.3: Intel Core2 Extreme, 3.00GHz
© NVIDIA Corporation 2009

104. !"#$%&'()*+,*-./0)
'#"
Up to 2x average speedup over CUBLAS 3.1
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105. CULA

106. CULA (LAPACK for heterogeneous systems)
GPU Accelerated
Linear Algebra
Partnership
! Dense linear algebra Developed in
! C/C++ & FORTRAN partnership with
! 150+ Routines NVIDIA
MATLAB Interface Supercomputer Speeds
! 15+ functions Performance 7x of
! Up to 10x speedup

107. CULA - Performance
Supercomputing Speeds
This graph shows the relative speed of many CULA functions when compared to
(Fermi) and an Intel Core i7 860. More at www.culatools.com

108. CUSPARSE

109. Sparse Matrix Performance: CPU vs. GPU
Multiplication of a sparse matrix by multiple vectors
35x
30x
25x
20x
15x
10x
"Non-transposed"
5x "Transposed"
0x MKL 10.2
Average speedup across S,D,C,Z
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110. CUFFT

111. CUFFT
CUFFT is the CUDA FFT library
Computes parallel FFT on an NVIDIA GPU
Plan contains information about optimal configuration for a
given transform.
Plans can be persisted to prevent recalculation.
Good fit for CUFFT because different kinds of FFTs require
different thread/block/grid configurations.
© NVIDIA Corporation 2009

112. CUFFT Features
1D, 2D and 3D transforms of complex and real-
valued data
Batched execution for doing multiple 1D transforms
in parallel
1D transform size up to 8M elements
2D and 3D transform sizes in the range [2,16384]
In-place and out-of-place transforms for real and
complex data.
© NVIDIA Corporation 2009

113. CUFFT Example
Complex 2D transform
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© NVIDIA Corporation 2009

114. CUFFT Performance: CPU vs GPU
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© NVIDIA Corporation 2009

115. CUFFT 3.2: Improved Radix-3, -5, -7
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116. CUDPP

117. !"#$$
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118. !"#$$%&'()*+,
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119. More?

120. Thrust

121. Objectives
! Programmer productivity
! Rapidly develop complex applications
! Leverage parallel primitives
! Encourage generic programming
! Don’t reinvent the wheel
! E.g. one reduction to rule them all
! High performance
! With minimal programmer effort
! Interoperability
! Integrates with CUDA C/C++ code
3
© 2008 NVIDIA Corporation

122. !"#$%&
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126. More?

127. PyCUDA

128. PyCUDA
3rd party open source, written by Andreas Klöckner
Exposes all of CUDA via Python bindings
Compiles CUDA on the fly
presents CUDA as an interpreted language
Integration with numpy
Handles memory management, resource allocation
CUDA programs are Python strings
Metaprogramming modify source code on-the-fly
Like a really complex pre-processor
http://mathema.tician.de/software/pycuda
© NVIDIA Corporation 2009

129. PyCUDA Example
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© NVIDIA Corporation 2009

130. More?

131. CURAND

132. RNG Performance: CPU vs. GPU
Generating 100K Sobol' Samples
25x
20x
15x
10x CURAND 3.2
MKL 10.2
5x
0x
SP DP SP DP
Uniform Normal
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133. OpenVIDIA

134. OpenVIDIA
Open source, supported by NVIDIA
Computer Vision Workbench (CVWB)
GPU imaging & computer vision
Demonstrates most commonly used image
processing primitives on CUDA
Demos, code & tutorials/information
http://openvidia.sourceforge.net

135. and many more...

136. References
• CUDA C Programming Guide
• CUDA C Best Practices Guide
• CUDA Reference Manual
• API Reference, PTX ISA 2.2
• CUDA-GDB User Manual
• Visual Profiler Manual
• User Guides: CUBLAS, CUFFT, CUSPARSE, CURAND
http://developer.nvidia.com/object/gpucomputing.html

137. one more thing
or two...

138. Life/Code Hacking #2.x
Speed {listen,read,writ}ing
accelerated e-learning (c) / massively parallel {learn,programm}ing (c)

139. Life/Code Hacking #2.1
Speed listening
accelerated e-learning (c) / massively parallel {learn,programm}ing (c)

140. Life/Code Hacking #2.1
Speed listening
• Step 1: Collect
• online videos, tutorials, podcasts, etc.
• audiobooks
• youtube-dl, get_flash_videos, jDownloader,
ffmpeg, mplayer, etc.
• etc.
accelerated e-learning (c) / massively parallel {learn,programm}ing (c)

141. Life/Code Hacking #2.1
Speed listening
• Step 2: Accelerate (time-stretch)
• VLC (Playback > Faster)
• sox $f{,.1.8X.mp3} tempo 1.8 50
• iPod ? mp3splt -t 5.00 -o small-@n large.mp3
accelerated e-learning (c) / massively parallel {learn,programm}ing (c)

142. Life/Code Hacking #2.1
Speed listening
• Step 3: chill or do more ;-)
accelerated e-learning (c) / massively parallel {learn,programm}ing (c)

143. Demo

144. CO ME