Cameron Swen is the Divisional Marketing Manager for AMD’s Embedded Solutions Division. He is responsible for outbound marketing and works with AMDs customers to develop and market board and system level solutions to serve the COTS market.
PEER 1 Offers NVIDIA GPU to Accelerate High Performance Applications
PEER 1 has teamed up with NVIDIA the creator of the GPU and a world leader in visual computing, to provide high performance GPU Cloud applications. NVIDIA’s GPUs are well known for making customer software run faster and PEER 1 is offering a number of services that run on NVIDA’s GPUs. PEER 1’s cloud service is built on NVIDIA Telsa GPU’s delivering supercomputing performance in the cloud to solve much tougher problems. Click here to find out how PEER 1 and NVIDIA can transform your business.
PEER 1 Offers NVIDIA GPU to Accelerate High Performance Applications
PEER 1 has teamed up with NVIDIA the creator of the GPU and a world leader in visual computing, to provide high performance GPU Cloud applications. NVIDIA’s GPUs are well known for making customer software run faster and PEER 1 is offering a number of services that run on NVIDA’s GPUs. PEER 1’s cloud service is built on NVIDIA Telsa GPU’s delivering supercomputing performance in the cloud to solve much tougher problems. Click here to find out how PEER 1 and NVIDIA can transform your business.
The new AMD Opteron™ processor: The core of the cloud
* Designed for the inflection point around the hyper-efficient, virtualized Cloud
* Strong OEM and end-customer support out of the gate
* Superior performance, ranging from 24% to 84% in key trending workloads
* Increased virtualization scalability
* As much as 56% lower power-per-core
* Perfectly matched architecture for today’s highly threaded workloads including cloud, web, virtualization, database and HPC
AFDS 2011 Phil Rogers Keynote: “The Programmer’s Guide to the APU Galaxy.”HSA Foundation
AFDS Keynote: “The Programmer’s Guide to the APU Galaxy.”
Phil Rogers, AMD Corporate Fellow
It’s a well-understood maxim in the technology industry that software and hardware must evolve in parallel, and be well matched, to achieve greatness. With the introduction of the world’s first APU in January 2011, AMD pointed the world toward a new way of computing. This was very much a first step in an architectural journey that is well underway at AMD. APUs combine different processing engines in single-chip combinations to strike a unique balance between the dimensions of performance, power consumption and price. Hear how AMD is working to ease the programmer’s access to this new level of compute horsepower and dramatically expand the processing resources available to modern applications
ARM Techcon Keynote 2012: Sensor Integration and Improved User Experiences at...HSA Foundation
HSA is a new computing platform architecture being standardized by the HSA Foundation which has as Founding members, AMD, ARM, Imagination, TI, Mediatek, Samsung and Qualcomm. HSA is intended to make the use of heterogeneous programming widespread by making purpose built architectures as easy to program as modern CPUs are. We start off by doing this with the GPU, the most widely deployed companion processor to the CPU and one which especially complements the CPU in low power and performance workloads. This requires some hardware architecture changes, that we have been working on for some time (in particular those that enable user mode scheduling, unified address space, unified shared memory, compute context switching, etc.) and which we have encapsulated into the spec currently under review by the HSA Foundation.
In short, HSA codifies the hardware architecture changes that are needed to enable mainstream programmers to develop heterogeneous application with the same facility that they do CPU only applications by seamlessly integrating the sequential programming capability of the CPU with the parallel compute capability of the GPU. We describe the software stacks that are needed for HSA, the benefits that accrue to both developers as well as end users, and describe our vision of the how HSA will help unify the ecosystems of the smartphone and tablet platforms as well as bring it closer to that of the traditional PC market. We will provide analysis of several examples which arise in applications and present data to validate the performance per watt benefit of HSA.
Performance and scalability of Informix ultimate warehouse edtion on Intel Xe...Keshav Murthy
Talk at Information on Demand Conference 2011. As part of the Informix Ultimate Warehouse Edition, Informix
Warehouse Accelerator (IWA) transparently provides up to several
orders of a magnitude speed up in query performance for
Informix Dynamic Server (IDS), as well as enormous administrative
cost savings. Combined with the Intel Xeon E7 processor series,
Informix and the Accelerator brings the performance and
scalability of IDS solutions to new levels. This presentation will
give best practices and benefits of IWA and the Intel Xeon E7
processors, and highlight the implications and performance
benefits of running IDS and IWA on these processors, compared
to previous releases of IDS and prior Intel server platforms.
The new AMD Opteron™ processor: The core of the cloud
* Designed for the inflection point around the hyper-efficient, virtualized Cloud
* Strong OEM and end-customer support out of the gate
* Superior performance, ranging from 24% to 84% in key trending workloads
* Increased virtualization scalability
* As much as 56% lower power-per-core
* Perfectly matched architecture for today’s highly threaded workloads including cloud, web, virtualization, database and HPC
AFDS 2011 Phil Rogers Keynote: “The Programmer’s Guide to the APU Galaxy.”HSA Foundation
AFDS Keynote: “The Programmer’s Guide to the APU Galaxy.”
Phil Rogers, AMD Corporate Fellow
It’s a well-understood maxim in the technology industry that software and hardware must evolve in parallel, and be well matched, to achieve greatness. With the introduction of the world’s first APU in January 2011, AMD pointed the world toward a new way of computing. This was very much a first step in an architectural journey that is well underway at AMD. APUs combine different processing engines in single-chip combinations to strike a unique balance between the dimensions of performance, power consumption and price. Hear how AMD is working to ease the programmer’s access to this new level of compute horsepower and dramatically expand the processing resources available to modern applications
ARM Techcon Keynote 2012: Sensor Integration and Improved User Experiences at...HSA Foundation
HSA is a new computing platform architecture being standardized by the HSA Foundation which has as Founding members, AMD, ARM, Imagination, TI, Mediatek, Samsung and Qualcomm. HSA is intended to make the use of heterogeneous programming widespread by making purpose built architectures as easy to program as modern CPUs are. We start off by doing this with the GPU, the most widely deployed companion processor to the CPU and one which especially complements the CPU in low power and performance workloads. This requires some hardware architecture changes, that we have been working on for some time (in particular those that enable user mode scheduling, unified address space, unified shared memory, compute context switching, etc.) and which we have encapsulated into the spec currently under review by the HSA Foundation.
In short, HSA codifies the hardware architecture changes that are needed to enable mainstream programmers to develop heterogeneous application with the same facility that they do CPU only applications by seamlessly integrating the sequential programming capability of the CPU with the parallel compute capability of the GPU. We describe the software stacks that are needed for HSA, the benefits that accrue to both developers as well as end users, and describe our vision of the how HSA will help unify the ecosystems of the smartphone and tablet platforms as well as bring it closer to that of the traditional PC market. We will provide analysis of several examples which arise in applications and present data to validate the performance per watt benefit of HSA.
Performance and scalability of Informix ultimate warehouse edtion on Intel Xe...Keshav Murthy
Talk at Information on Demand Conference 2011. As part of the Informix Ultimate Warehouse Edition, Informix
Warehouse Accelerator (IWA) transparently provides up to several
orders of a magnitude speed up in query performance for
Informix Dynamic Server (IDS), as well as enormous administrative
cost savings. Combined with the Intel Xeon E7 processor series,
Informix and the Accelerator brings the performance and
scalability of IDS solutions to new levels. This presentation will
give best practices and benefits of IWA and the Intel Xeon E7
processors, and highlight the implications and performance
benefits of running IDS and IWA on these processors, compared
to previous releases of IDS and prior Intel server platforms.
Fremtidens platform til koncernsystemer (IBM System z)IBM Danmark
Efter 22. juli 2010 vil verden se anderledes ud – i hvert fald hvis man er en koncern med mange sammensatte systemer. Lær mere om IBM’s teknologiske gennembrud inden for System z, der kan forenkle og optimere dine systemer yderligere og skabe større forretningsværdi. Præsentationen er relevant for såvel nye brugere, som for dem der har anvendt System z i flere år.
Læs mere her: bit.ly/softwaredagsystemz1
IBM System z - zEnterprise a future platform for enterprise systemsIBM Sverige
July 22. 2010 changed the world of enterprises with consolidated systems. Hear more about IBM's technological break through within System z, which can simplify and optimize your systems further and create greater business value. Talare: Jørgen R Andersen, Nordic Regional Manager System z, IBM DK och Ray Jones, VP WW SW System z, IBM US. Denna presentation hölls vid ett seminariepass för System Z på IBM Software Day 2010.
Enea OSE® is a robust, high-performance, real-time operating system optimized for multi-processor systems requiring true deterministic real-time behavior and high availability. It shortens development time, enhances reliability and reduces lifetime maintenance costs for a wide range of systems, from wireless devices and automobiles, to medical instruments and telecom infrastructure.
Heterogeneous Systems Architecture: The Next Area of Computing Innovation AMD
Dr. Lisa Su, Senior Vice President and GM, Global Business Units, AMD keynote from ISSCC on Heterogeneous Systems Architecture: The Next Area of Computing Innovation - Case Study, The Holodeck.
Simulation Directed Co-Design from Smartphones to SupercomputersEric Van Hensbergen
SystemExplorer is a system simulation framework based upon the open-source gem5 simulation infrastructure. It includes a rich collection of hardware components such as ARM cores, interconnect, memories and memory controllers, IO devices - ethernet, PCIe, and other peripherals. In addition it provides support for run fully featured operating systems such as Linux and Android combined with pre-packaged filesystem images that contain real workloads and benchmarks for Smartphone, Server and High Performance Computing. In this talk I'll give an overview of ARM R&D's use of the SystemExplorer tool for workload directed architectural co-design. I will focus on how we are using it in combination with the Department of Energy's co-design center proxy applications to help evaluate and enable the ARM architecture to address the power-efficiency, performance, and resilience requirements of Exascale computing.
(Presented during FastPass 2013 Workshop in Austin, TX)
Talk on Fundamentals of Parallel Computing ranging from basics and history of parallel computing to comparison of recent trends in the area of high performance computing delivered at Indo-German Winter Academy 2009.
2. TYPES OF MULTI-CORE PROCESSORS
Homogeneous Heterogeneous
Multi-core Processor Multi-core Processor
2 COTS Moves to Multi-core
3. MULTI-CORE PROCESSORS TUNED FOR TARGET MARKETS
“Bulldozer”
Performance &
Scalability
High Performance and Multi-processor Applications
Low Power Applications
“Bobcat”
Flexible, Low Power
& Small
3 COTS Moves to Multi-core
4. MULTI-CORE BENEFITS
Core 1 Core 2
Performance per Watt
Deterministic behavior
– Real-time software is not interrupted by GUI operations
Reliability
– Isolate critical system functions from non-critical functions
Security
– Isolate communications or user interface from sensitive data
4 COTS Moves to Multi-core
5. A NEW ERA OF MULTI-CORE PROCESSOR DESIGN
Heterogeneous
Single-Core Era Multi-Core Era
Systems Era
Constrained by: Constrained by: Enabled by:
Power Power Abundant data parallelism
Complexity Parallel SW availability Power efficient GPUs
Scalability
Constrained by:
Programming models
Targeted Application
Single-thread
Performance
Performance
Performance
Throughput
?
we are
here
we are
here
we are
here
Time Time Time
(# of processors) (Data-parallel exploitation)
5 COTS Moves to Multi-core
6. A NEW ERA OF PROCESSOR DESIGN & PERFORMANCE
Microprocessor Advancement
CPU
Single-Core Multi-Core Heterogeneous
Era Era Systems Era
Heterogeneous System-level
Computing programmable
Programmability
OpenCL/DX
Homogeneous driver-based
programs
Computing
Advancement
GPU
Graphics
driver-based
programs
Throughput Performance GPU
6 COTS Moves to Multi-core
7. TRADITIONAL X86 ARCHITECTURE
01010101010101 010101010101010
10101010101010 NORTH 101010101010101
01010101010101 BRIDGE 010101010101010
10101010101010 101010101010101
CPUs are designed for: A Northbridge is designed for: GPUs are designed for:
• General purpose tasks • Controlling communications • Graphics tasks
(e.g. primary PC usage, calculations) among the CPU, GPU, RAM, (e.g. video rendering, display
• Common applications (Windows®, BIOS and the Southbridge output)
Spreadsheets, Word processing,…) • Most visual applications (3D-
• Serial data processing rendering, HD Video playback)
• Parallel data processing
7 COTS Moves to Multi-core
8. INTRODUCING THE AMD ACCELERATED PROCESSING UNIT (APU)
APUs are the next generation of AMD processors, with the
combined power of AMD CPU technologies and discrete-class,
DirectX®11 capable, AMD Radeon™ graphics.
8 COTS Moves to Multi-core
9. MULTI-CORE APU BENEFITS
Performance Per Watt Platform Scalability Parallel Processing
• Take full advantage of • A single platform can scale • Leverage parallel
parallel processing from 1 to multiple cores processing to get the
maximum performance
• Scale x86 and graphics from the APU
performance
• Increase performance
Gflops/Watt
• Scale APU power from 5- without adding cost or power
18W to the system
5 • OpenCL™ allows
programmers to preserve
0 their expensive source code
Athlon™ II
G-Series
investment across multiple
P320
product generations.
Based on performance per watt comparisons between AMD Fusion APUs and the AMD Athlon™ II P320 CPU combined with the AMD Mobility Radeon™ HD 4250 GPU. In testing conducted by
AMD performance labs, AMD Fusion APUs demonstrated the following: A-Series-up to approximately 500 GFLOPS; E-Series/C-Series-up to approximately 90 GFLOPS at 18/9 W. In
comparison, the AMD Athlon™ II P320 CPU and AMD Mobility Radeon HD 4250 GPU deliver a combined total of 74 GLOPS at 38 W. Requires application support for AMD Accelerated Parallel
Processing (APP) technology. AMD Accelerated Parallel Processing technology works with applications designed to take advantage of GPU acceleration capabilities.
9 COTS Moves to Multi-core
10. AMD EMBEDDED G-SERIES PLATFORM
FUELING THE INNOVATION FOR TOMORROW’S
TECHNOLOGY…TODAY!
THANK YOU!
Industry Embedded
Standards Innovation
10 COTS Moves to Multi-core