The document discusses predictions for computers in 2020 and 2030 based on Moore's Law. In 2020, computers are predicted to have 32-core CPUs, 48-core GPUs, 16GB of DRAM integrated on-chip due to pin limitations. In 2030, the entire system is predicted to integrate onto a single chip with a 2000-core CPU, 3000-core GPU, and 1TB of on-chip memory due to transistor densities allowing entire systems to fit on chips. However, limitations around I/O bandwidth, process differences, power and packaging will provide challenges to scaling.

1. COMPUTERS OF
2020 AND 2030
Tat Iwamoto
January 2013
Saturday, January 19, 13

2. WHERE ARE WE NOW?
• Most popular computer of 2012, iPhone 5
• No longer PC. Desktop and laptops are irrelevant.
Saturday, January 19, 13

3. Modem x2
CPU
1.3GHz 4Gb LPDDR2
Wifi/BT
4Gb LPDDR2
x3
Misc GPU
Peripherals 325MHz
128Gbit
NAND
IPHONE 5 SYSTEM
Saturday, January 19, 13

4. DIE SIZE
• A6 (32nm) 100mm^2
• LPDDR2 (20nm) 100mm^2 x2
• Flash (20nm) 200mm^2
•= 400mm^2
• Just very rough estimate
Saturday, January 19, 13

5. MOORE’S LAW
Density converted to 2013 mm^2
1,000,000
• 2013 = 400mm^2
100,000
• Density increase 10,000
1,000
• 2020 = 16x
100
• 2030 = 1000x 10
1
2010 2015 2020 2025 2030
Saturday, January 19, 13

6. SCALE THE SAME
CONFIGURATION
• 2020 • 2030
• 32 core ARM CPU • 2000 core ARM CPU
• 48 core GPU • 3000 core GPU
• 16GB DRAM • 1TB DRAM
• 256GB Flash • 16TB Flash
Saturday, January 19, 13

7. LIMITERS (1)
• IO Speed
• Do not scale with density
• Assume scale with linear length
• 1.4x for 2x density
• 10Gbit/s limit for PCB
Saturday, January 19, 13

8. x2
CPU 4Gb LPDDR2
1.3GHz
1Gbit/s x64 bit=8GB/s
x3 4Gb LPDDR2
GPU
325MHz
40Mbit/s x4 bit=20MB/s
128Gbit
NAND
MEMORY IO BANDWIDTH
Saturday, January 19, 13

9. 1Gbit/s x16 > 10Gbit/s
CPU x32 More pins needed to scale
64GB DRAM
GPU x48 10Gbit/s x100 bit=128GB/s
640Mbit/s x4 bit=320MB/s
256GB Flash
MEMORY IO BANDWIDTH 2020
Saturday, January 19, 13

10. CPU x2000
1TB DRAM
GPU x3000 10Gbit/s x800 bit=8TB/s
800 pins is impossible
10Gbit/s x16 bit=20GB/s
16TB Flash
20Mbit/s x1000 >10Gbit/s
More pins needed to scale
MEMORY IO BANDWIDTH 2030
Saturday, January 19, 13

11. LIMITERS (2)
• Process difference
• Logic
• DRAM
• Flash
• Use different process
Saturday, January 19, 13

12. LIMITERS (3)
• Power
• Need to keep battery time
• Frequency and power roughly scales with linear length
• 2x Density = 1.4x Speed, 0.7x Power
• Need to lower activity to keep heat at same level
Saturday, January 19, 13

13. LIMITERS (4)
• Chips can’t get smaller
• Pad limit
• Package pin limit
Saturday, January 19, 13

14. INTEGRATE DRAM DIES
• DRAM pins run out first
• Memory is cooler than logic
• Keep flash off chip
• 2x transistors = 1.4x logic + 0.7x additional area
• Use additional area for memory
• DRAM -> SRAM
• DRAM : SRAM 6:1 bit density
Saturday, January 19, 13

15. 2020 RAM ON-CHIP
• 16x Density • 1GB DRAM -> 12mm^2
• Die -> 7mm^2 • DRAM vs Logic
density gap 2:1
•x 4 for same power
= 28mm^2 • DRAM:SRAM = 1:6
• 72mm^2 for memory • 1GB SRAM = 144mm^2
• 72mm^2 = 512MB SRAM
Saturday, January 19, 13

16. No external DRAM
CPU x8 No pins
No IO power
512MB
SRAM
CPU 1.3 x 4 = 5.2GHz
GPU x12 GPU 325 x 4 = 1.3GHz
Enough memory bandwidth
640Mbit/s x4 bit=320MB/s
256GB Flash
2020 SOC
Saturday, January 19, 13

17. 2030 ONE CHIP
• 1000x Density • 1GB DRAM -> 0.2mm^2
• Die -> 0.1mm^2 • 16GB Flash -> 0.2mm^2
•x 32 for same power •1 GB SRAM = 2.4mm^2
= 3mm^2
• 97mm^2 = 40GB
• 97mm^2 for memory
• Build chip on Flash process
• Logic only 3%
• SRAM + Flash
• Not dominant area
• Maybe lower frequency
Saturday, January 19, 13

18. No external DRAM/Flash
CPU x64 No pins
No IO power
40GB
SRAM
or Flash CPU 1.3 x 32 = 40GHz
GPU 325 x 32 = 10GHz
GPU x96
Consider SRAM / Flash mix
2030 SOC
Saturday, January 19, 13

19. TWEAKS
• Use better CPU/GPU
• Less cores / more memory
• Smaller overall die?
Saturday, January 19, 13

20. MORE OPTIONS
• Integrate other IO peripherals
• Should be enough room for that, too
• OK as long as pin count is low
• Special IO may require lower density
Saturday, January 19, 13

21. OTHER DEVELOPMENTS
• Mixed process technology: logic + DRAM + Flash
• Package technology: more pins, more interconnect speed
• Interconnect technology: 10Gbit/s+
Saturday, January 19, 13