This document describes a proposed design for a high-speed complex multiplier using Vedic mathematics techniques. The objectives are to implement a complex multiplier using Vedic mathematics, increase the speed of the multiplier, and reduce its power. It introduces Vedic mathematics and the existing array multiplier method. The proposed method implements the Urdhva-tiryakbhyam and Nikhilam Navatashcaramam Vedic multiplication algorithms for the complex multiplier. Simulation results show the implementation of these Vedic sutras for the complex multiplier provides substantial speed and power improvements over the existing array multiplier approach.