1. Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI)
substrates featuring raised source/drain and dual CESL
N. Collaert, R. Rooyackers, G. Dilliway, V. Iyengara
, E. Augendre, F. Leys, I. Cayrefourqb
, B. Ghyselenb
, R. Loo, M. Jurczak, S. Biesemans
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; a
also K.U. Leuven, ESAT-INSYS, Heverlee B-3001, Belgium and Electrical and Computer
Engineering Dept., the University of North Carolina at Charlotte, USA; b
SOITEC, Bernin, Crolles Cedex, France
Abstract
In this paper, we investigate for the first time the impact of raised
source/drain on the short channel current enhancement of MuGFET
devices on Super Critical Strained SSOI (SC-SSOI). Short channel nMOS
drive current can be improved up to 15% and even 50% in the case of
high tensile 30nm SSOI substrates. We also show that SC-SSOI has a
higher sensitivity to the mobility boost from tensile Contact Etch Stop
Layers (CESL). Therefore the combination of both mobility boosters is
very beneficial for nMOS MuGFET when used with SEG.
1. Introduction
The MuGFET (FinFET based multi-gate) transistor is the most widely
studied and known multi-gate architecture with potential to be scaled
beyond the 45 nm technology node. Since the current in a MuGFET flows
as well in the sidewalls, the difference in crystal orientation between the
top channel and the sidewalls will impact the mobility of electrons and
holes differently. Mostly nMOS is affected by the less favorable crystal
orientation of the sidewalls. In [1] we have already demonstrated that the
tensile strain of a 1.5 GPa Super Critical Strained SOI (SC-SSOI)
substrate can be retained in MUGFET devices with fin widths as narrow
as 20 nm. Although the current improvement for long channel devices can
be as high as 80%, the improvement is significantly reduced for short
channel devices. The latter can be attributed to the increased RSD for
narrow fin devices. The RSD reduction in MUGFET by selective epitaxial
growth (SEG) is seen as one of the most critical process issues [2]. In this
paper, we present two new key advancements over our previous report:
introduction of Si SEG on source and drain to reduce the RSD and the use
of strained CESL simultaneously introducing liners with different intrinsic
stress on nMOS and pMOS.
2. Device fabrication
The schematic presentation of the process flow is shown in Fig. 1. The
starting substrate is a SC-SSOI wafer with 55 nm Si film on top of 130
nm buried oxide. As reference, MUGFET devices on a standard
(100)/<110> (top orientation) SOI wafer were processed. The intrinsic
biaxial tensile stress of the SC-SSOI wafers is 1.5GPa. Fin widths down
to 25nm were fabricated using 193nm lithography and aggressive
trimming of the SiON hard mask. The gate stack is: 2nm ALCVD HfO2,
ALCVD/ 5 nm MOCVD TiN layer capped with 100nm poly. As and BF2
extensions and 40 nm RTCVD nitride spacers were formed. Elevated
source and drain were growth with recessed spacers [3]. After epitaxial
growth, HDD implantations were done, followed by a spike anneal. NiSi
was used as a salicide and a standard Cu BEOL was used to finish the
reference devices. Dual strained CESL was introduced on some devices.
In this case, 800MPa tensile CESL (tCESL) was used for nMOS and 1.5
GPa compressive CESL (cCESL) was used for pMOS. Fig. 2 shows a
SEM picture of the tCESL after etch-back on the pMOS areas.
3. Device results
A. SC-SSOI and elevated source/drain
As can be seen in Fig. 3, the impact of RSD on the nMOS current
improvement with SC-SSOI is significant, especially for the short channel
devices. Decreasing the RSD is mandatory in order to fully benefit from
the mobility enhancement by the uniaxial tensile strain. Fig. 4 and Fig. 5
show the Ion-Ioff curves for nMOS and pMOS respectively. In this case,
the standard SOI devices with SEG are compared to the SC-SSOI devices
with SEG. Whereas, the pMOS is degraded by 30%, the nMOS devices
show a 15% improvement at 100nA/µm leakage current. Fig. 6 shows the
increase in nMOS current improvement. Compared to the non-SEG case,
current improvement is shifted to higher values with the largest impact
seen on the short channel devices. The latter is confirmed by simulations
(Fig. 3). Note that the thermal budget of the SEG growth has no impact on
the retained tensile strain in the fins. The negative current improvement
(Fig. 6) for the case where no SEG is used can be attributed to the higher
RSD resistance for the SC-SSOI devices as can be seen in Fig. 7. The
difference in RSD is the highest for the non-SEG case and is related to the
thinner Si film of the SC-SSOI devices.
B. Dual CESL and elevated source/drain
Local stressors like strained CESL were shown to be beneficial in
improving short channel devices [4]. However, when SEG is used to
reduce the RSD, the mobility improvement of both top channel and
sidewalls is reduced (Fig. 8). This can be explained by the fact that the
proximity of the SiN liner to the channel is decreased as is shown in Fig.
9. The decrease is most significant for the top down stress component
(perpendicular for sidewalls) and the longitudinal stress. At the same time,
reduction of the RSD by SEG is beneficial for increasing the current
improvement at shorter gate lengths (Fig. 10). Fig. 11 shows the current
improvement for nMOS with tCESL and pMOS with cCESL respectively.
This demonstrates that, especially for nMOS, the stress reduction will be
the dominant factor for long channel lengths but the reduction of RSD
seems to be most beneficial for short channel devices.
C. Dual CESL and SC-SSOI
Interestingly, the performance improvement achieved with strained CESL
on standard SOI substrates and SC-SSOI is different. In Fig. 12, the
current improvement with CESL on the two different substrates is shown.
Whereas the improvement with CESL is reduced for pMOS on SC-SSOI,
the nMOS benefits from the mobility improvement with CESL on SC-
SSOI. The RSDlin is plotted as function of the gate length in Fig. 13. No
significant difference in RSD is seen. In Fig. 14 and 15 the mobility
extractions on long channel devices are shown. For holes, the
improvement with cCESL on SC-SSOI is only seen at higher electric
fields. 3D Taurus simulations (Table 1) show that the stress components
are additive. Consequently, the sensitivity of SC-SSOI to the stress
introduced by CESL is slightly larger than expected and different for
tensile and compressive stress. The higher impact of CESL on tensile SC-
SSOI is also demonstrated in Fig. 17. This figure shows the difference
between SC-SSOI with 30nm and 60nm fin height. Since the tensile strain
along the current direction is best retained in devices with decreasing fin
height (Fig. 16), the impact of the tensile CESL is increased for the 30nm
high devices. Since the RSD is higher for the 30nm fins the higher tCESL
improvement at short Lgate (40% vs. 20%) can not be attributed to the RSD
effect. Summarizing, the best performance for nMOS can be achieved by
using a SC-SSOI substrate with tCESL (Fig. 18) and reducing the RSD by
SEG thereby increasing the impact of the global and local stressor. For the
pMOS performance, it is mandatory to relax the uniaxial strain.
Relaxation of the stress can be done by means of implantation as is
described in [6]. The best pMOS performance can in this case be obtained
by using the cCESL on a standard SOI substrate (Fig. 19).
4. Conclusions
We have shown that the nMOS current improvement with SC-SSOI can
be optimized by reducing the RSD. Next to that, the impact of SEG on the
mobility improvement with strained CESL was investigated. Whereas the
use of SEG is beneficial for global stress engineering, it will reduce the
effect of the strained nitride liner for long channels. However, short
channels still benefit from the lower resistance therefore demonstrating
that RSD reduction is mandatory in order to fully benefit from global and
local strain engineering.
References
[1] N. Collaert et al., VLSI Symp., p. 64-65, 2006 [2] H. Shang et al., VLSI Symp., p.
66-67, 2006 [3] J. Kedzierski et al.,IEEE Trans. Electron Dev., vol. 50, pp. 952-
958, 2003 [4] S. Pidin et al., ., VLSI Symp., p. 54-55, 2004 [5] J. Kavalieros at al.,
VLSI Symp., p. 62-63, 2006 [6] A.V.-Y. Thean et al., VLSI Symp., p. 164-165, 2006

2. Figures
fin patterning
gate stack
extensions
RTCVD spacer
elevated S/D
S/D implantation
NiSi
dual CESL
Cu BEOL
fin patterning
gate stack
extensions
RTCVD spacer
elevated S/D
S/D implantation
NiSi
dual CESL
Cu BEOL tensile CESL
pMOS
tensile CESL
pMOS
XX YY ZZ
tCESL 114 -316 392
SSOI -7 -46 1187
SSOI+
tCESL
120 -325 1564
Table 1: sidewall stress components (in MPa)
for different mobility boosters XX=top-down,
YY=perpendicular and ZZ=longitudinal;
negative values indicate compressive stress
Fig. 1: schematic presentation of the process
flow
Fig. 2: tilted SEM of tensile CESL after etch-
back on the pMOS areas
-40
-20
0
20
40
60
0.01 0.1 1 10
currentimprovement[%]
L
gate
[µµµµm]
|V
DS
|=50 mV
|VGS
|=1 V
|V
T
|=0.25 V
nMOS
pMOS
reduced RSD
reduced R
SD
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
0.001
0 200 400 600 800 1000
reference
SC-SSOI
I
off
[A/µµµµm]
I
on
[µΑµΑµΑµΑ/µµµµm]
V
DD
=1.2 V
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
0 200 400 600 800 1000
reference
SC-SSOI
I
off
[A/µµµµm]
I
on
[µΑµΑµΑµΑ/µµµµm]
V
DD
=-1.2 V
Fig. 3: simulated current improvement with SC-
SSOI as function of the gate length; the impact
of RSD is shown
Fig. 4: Ion-Ioff curve for nMOS measured at
VDD=1.2 V; Wfin=25nm
Fig. 5: Ion-Ioff curve for pMOS measured at
VDD=-1.2 V; Wfin=25nm
-20
0
20
40
60
80
100
0.1 1 10
with elevated S/D
without elevated S/D
currentimprovement[%]
L
gate
[µµµµm]
+25%
1000
2000
3000
4000
5000
6000
7000
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
ref. + SEG
SSOI+SEG
SSOI
reference
normalizedR
DS
[ΩΩΩΩµµµµm]
L
gate
[µµµµm]
15
20
25
30
0 5 10 15 20 25 30 35 40
mobilityimprovement[%]
SEG thickness [nm]
topsidewalls
800MPa tensile CESL
Lgate
=50nm
H
fin
=60nm
W
fin
=30nm
reduced R
SD
Fig 6: nMOS current improvement for SC-SSOI
as function of gate length; the impact of the
SEG growth on source/drain is shown
Fig. 7: normalized nMOS RSD as function of the
gate length; reference devices with and without
SEG are compared to the SC-SSOI devices with
and without SEG
Fig 8: simulated (3D) mobility improvement for
a short channel devices with Lgate=50nm and
Wfin=30nm as function of the SEG thickness; Si
piezo-resistive coefficients were used to translate
the stress into mobility improvement
Si fin
gate
spacer
CESL
Si fin
gate
spacer
CESL
Si fin
gate
spacer
CESL
SEG SEG
Si fin
gate
spacer
CESLCESL
SEG SEG
(a) (b)
0
10
20
30
40
50
60
0.01 0.1 1 10
currentimprovement[%]
L
gate
[µµµµm]
R
SD
=200 ΩΩΩΩ
R
SD
=800 ΩΩΩΩ
V
DS
=50 mV
VGS
=1 V
V
T
=0.25 V
with increased strain
Fig. 9: schematic representation of the SEG impact on the mobility improvement from the local
stressor; two cases are shown; (a) no SEG and (b) thick SEG film
Fig. 10: simulated improvement with CESL as
function of the Lgate; a gradual increasing
mobility is assumed with decreasing Lgate

3. -20
-10
0
10
20
30
40
50
60
0.1 1 10
without SEG
with SEG
currentimprovement[%]
L
gate
[µµµµm]
pMOS + cCESL
nMOS + tCESL
-20
-10
0
10
20
30
40
0.1 1 10
SOI
SSOI
currentimprovementwithCESL[%]
L
gate
[µµµµm]
nMOS + tCESL
pMOS + cCESL
|V
GS
-V
T
|=0.7 V
|V
DS
|=1 V 500
1000
1500
2000
2500
3000
3500
4000
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
SOI
SSOI
SOI+tCESL
SSOI+tCESL
R
DSlin
[ΩΩΩΩµµµµm]
L
gate
[µµµµm]
+ SSOI
+ tCESL
+SSOI+ tCESL
Fig. 11: current improvement for 60nm SC-
SSOI devices with CESL as function of gate
length; devices with Wfin=25nm are shown;
reference devices are SC-SSOI devices
Fig. 12: current improvement for SC-SSOI
devices with CESL as function of gate length;
devices with Wfin=25nm are shown; SC-
SSOI+CESL is referenced to SC-SSOI and
SOI+CESL is referenced to SOI
Fig. 13: normalized nMOS RSD as function of the
gate length comparing the different substrates
0
100
200
300
400
500
600
700
800
0 0.8 1.6 2.4 3.2 4 4.8 5.6 6.4
SOI
SOI+tCESL
SSOI+tCESL
SSOI
holemobility[cm
2
/Vs]
N
inv
(x 1e12) [cm
-2
]
SOI
SSOI
0
50
100
150
200
250
300
0 1 2 3 4 5 6 7 8
SOI
SSOI
SSOI+cCESL
SOI+cCESL
holemobility[cm
2
/Vs]
N
inv
(x 1e12) [cm
-2
]
SOI
SSOI
300
400
500
600
700
800
900
1000
1100
0 0.02 0.04 0.06 0.08 0.1
top channel
sidewall
longitudinalstrain[MPa]
W
fin
[µµµµm]
+40%
Hfin
=30nm
Hfin
=60nm
Fig. 14: extracted electron mobility for a device
with Lgate=1 µm and Wfin=25 nm
Fig. 15: extracted hole mobility for a device with
Lgate=1 µm and Wfin=25 nm
Fig. 16: simulated longitudinal stress as function
of the fin width for different fin heights; the
intrinsic stress of the biaxial strained starting
substrate is 1.5 GPa tensile stress
0
50
100
150
200
250
0.1 1 10
without tCESL
with tCESL
currentimprovement[%]
L
gate
[µµµµm]
VGS
-VT
=0.7 V
V
DS
=1 V
30nm SSOI
60nm SSOI
+40%
+20%
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
0 200 400 600 800 1000 1200
reference + SEG
SSOI + SEG
SSOI + SEG + tCESL
I
off
[A/µµµµm]
I
on
[µΑµΑµΑµΑ/µµµµm]
VDD
=1.2 V
10
-12
10
-11
10
-10
10
-9
10
-8
0 100 200 300 400 500 600
reference
SEG+ cCESL
I
off
[A/µµµµm]
I
on
[µµµµA/µµµµm]
V
DD
=-1.2 V
Fig. 17: nMOS current improvement for 30nm
and 60nm SC-SSOI+SEG as function of gate
length; devices with Wfin=25nm are shown; the
improvement with and without tensile CESL is
shown; reference device for 30nm SC-SSOI is a
MuGFET device on 30nm SOI+SEG; ;
reference device for 30nm SC-SSOI is a
MuGFET device on 30nm SOI+SEG
Fig. 18: Ion-Ioff curve for nMOS measured at
VDD=1.2 V; Wfin=25nm
Fig. 19: Ion-Ioff curve for pMOS measured at
VDD=1.2 V; Wfin=25nm