Design of a two stage differential low noise amplifier for uwb applications

1. International INTERNATIONAL Journal of Electronics and JOURNAL Communication OF Engineering ELECTRONICS & Technology (IJECET), AND
ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 7, July (2014), pp. 63-71 © IAEME
COMMUNICATION ENGINEERING TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 5, Issue 7, July (2014), pp. 63-71
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IJECET
© I A E M E
DESIGN OF A TWO STAGE DIFFERENTIAL LOW NOISE AMPLIFIER
FOR UWB APPLICATIONS
Neeraj Malviya, R.S Gamad
Department of Electronics and Instrumentation Engineering,
SGSITS Indore, (M.P), India
63
ABSTRACT
This paper reports a design of a two stage differential LNA for Ultra-wideband (UWB)
applications. Design is consisted with a simple two stage with noise improvement technique. The
first stage is utilizing a resistive current through reuse and dual inductive degenerated technique to
attend a wideband input matching. Second stage is used as a common source amplifier with inductive
peaking technique to generate a response of flat power gain. Best simulation result are obtained that
is maximum power gain is 20.30 dBs, noise figure of 2.8 to 4.5 dBs, High reverse isolation of -45 dB
is obtain with good linearity that is IIP3 = -3.76dbm.
Keywords: Ultra Wide Band, Low Noise Amplifier, Noise Figure, Linearity, Reverse Isolation,
Inductive Degeneration.
INTRODUCTION
Now a days ultra wide frequency band is being mostly used in commercial application and
becoming great area of interest for wireless communication engineers. The need for low power and
high-throughput wireless communication systems has grown exponentially in the last few years.
UWB technology has attracted immense interest from the research and industry communities because
of its high data rate, robustness against multipath fading and low power dissipation. This technology
provides high-bandwidth wireless link for the transmission of audio, video and high speed data.
Frequency bands from 0 to 960 MHz (subgigahertz band) and from 3.1 to 10.6 GHz are allocated by
FCC for UWB communication respectively, for medium range less than 100 m low throughput and
short range less than 10m high-through- put (1GBPS) data. By definition, an UWB radio signal is
expected to have a fractional bandwidth greater than 20% or a bandwidth of at least 500MHz
[1-3]. This ultra-wide channel bandwidth B allows high channel capacity C, enabling data transfer at
a very high rate, while, keeping the transmitted signal-to-noise ratio (SNR) to a minimum.

2. International Journal of Electronics and Communication Engineering Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 7, July (2014), pp. 63-71 © IAEME
Since it is a first block of receiver so it should be able to catch sufficient amount of signal and
also able to amplify largely over desire or constant bandwidth and deliver sufficient amount to load
with addition of as minimum noise as possible. The ability to catch and deliver sufficient amount of
signal is totally depend on input and output load matching that is S11 and S22, addition of noise is
inherent property of devices, so it can be reduced only. The design of LNA is quiet difficult and
creates a large problem. In recent years much research have been done on designing of LNA such as
distributed amplifier, filter matching network amplifier, and current reuse amplifier. From all the
topology they have their own advantages and disadvantages for example the distributed amplifier
provide large gain over high bandwidth but has large power consumption similarly in folded cascode
topology it require high area high power consumption but give low noise figure [4-5]. The cascode
topology of LNA design will able to provide large gain as well good noise figure and having good
resistance against third order non linearity. In the same topology if current is feedback through
resistor then it becomes resistive feedback topology and it will able to provide good gain and good
linearity when the same topology, we use differentially, we get minimum noise figure at moderate
gain and moderate linearity [7-8]. Now it is clear that the design of RF-CMOSLNAs, the key
performance parameters are power-gain, noise figure (NF) and linearity besides the stability and
isolation. The goal of LNA design is to achieve maximum power-gain and minimum NF
simultaneously at any given amount of power dissipation with good linearity.
Proposed Design:
Since we are using cascode topology which involves common gate followed by common
source to design UWB LNA as it is able to provide high gain with good linearity and better noise
figure. Along with this topology authors have used a feedback resistor to get even better gain, noise
figure and input reflection coefficient. As shown in fig2. To avoid degradation in input impedance
and the -3db bandwidth at high frequency to overcome this problem, source degeneration that is
inductors are used to tune out parasitic capacitances at partial sides.
Figure 1: simple current reuse topology
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3. International Journal of Electronics and Communication Engineering Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 7, July (2014), pp. 63-71 © IAEME
Figure 2: Simple current reuse topology with resistor feedback
There are several techniques to increase third order input intercept point in order to get high
linearity such as MGTR Technique which involves two transistor connected back to back in parallel.
From these transistor one is operated in weak inversion region while the other is operated in strong
inversion region so that, they produce negative and positive third order frequency terms, and they can
be cancel out easily and improvement will obtained in linearity[9]. Another technique, which
involves Q-factor at the input side, to increase and get better linearity in the same way with
adjustment of overdrive voltage (vgs-vth) of input MOS [10].Such a way the another technique is very
simple which involves transconductance of transistor directly, in this if increases the
transconductance then in proportionate gain will increase but linearity got degraded. if decrease the
gain, third order input intercept point will improved and due to this overall linearity will improved
[11].
The overall gain of single ended LNAis given as:
Av = (gmn + gmp)(rf // rdsn//rdsp//zin2). (1)
Clearly the overall gain depend on sum of transconductance of two transistor and is directly
proportional to it.
The overall transconductance can be determine as:
Gm,tot = {gmn/(1+jlgmn)} + {gmp/(1+jlgmp)} (2)
noise figure of single ended LNA is given by [12] :
2+rs
65
NF = 1+(2/3)(The noise 1/(gmn + gmp) rs)((rf
2)/rsrf
2 ) + 2/3(gmn + gmp)rs(f/ft)2 + rs/rf (3)

4. International Journal of Electronics and Communication Engineering Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 7, July (2014), pp. 63-71 © IAEME
If increase the transconductance the overall gain will increases and due to this noise figure
decrease. the value of transconduction is depend on W/L ratio [13-15] and its mathematical
expression is as follows:
Gm = UnCox (W/l)(vgs - vth) (4)
As per the requirement authors have decrease the width of transistor to improve the linearity
of LNA. And for maintaining noise figure authors have connected differentially.
To overcome the problem of noise we use Differential circuits and these are an important part
of integrated circuit design because they offer several important advantages over single-ended
circuits. The significant and relevant benefit of using a differential circuit is noise reduction.
Differential LNA can restrain common mode interference, so the noise of source voltage and
underlay voltage can also be restrained. The schematic view of the proposed design is given in
figure 3.
Figure 3: Proposed design of LNA
66
Simulation Results
The proposed design is simulated over Cadence spectra, 0.18μm CMOS technology with
1.8V supply voltage. The simulated results are obtained and compared with earlier work, as shown in
table 1. As per reported results it is found that the proposed circuit has reliable Voltage gain
(maximum S2,1) of 20.37dbs, Reverse Isolation is less than -43dbs, better Linearity shown in IIP3 is -
3.36dbm with input and output matching is -20dbs and -1.75dbs respectively. After applying
differential technique, the improved Noise figure is obtained in the range of (3.12 to 4.12db) and
their graphs are given in figure 4,5,6,7,8 and 9 respectively.

5. International Journal of Electronics and Communication Engineering Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 7, July (2014), pp. 63-71 © IAEME
Figure 4: Voltage gain (S21)
Figure 5: Reverse Voltage gain (S12)
67

6. International Journal of Electronics and Communication Engineering Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 7, July (2014), pp. 63-71 © IAEME
Figure 6: Third order input intercept point (IIP3)
Figure 7: Input reflection coefficient (s11)
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7. International Journal of Electronics and Communication Engineering Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 7, July (2014), pp. 63-71 © IAEME
Figure 8: Output reflection coefficient (S22)
Figure 9: Noise figure (NF)
69

8. International Journal of Electronics and Communication Engineering Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 7, July (2014), pp. 63-71 © IAEME
Table 1: Comparison of the proposed results with earlier similar reported work
Specification [12] [8] [11] This work
Technology(μm) .18 .18 .18 .18
Frequency(GHz) 3.1 to 10.6 0.4 to 1.0 3.1 to 10.6 3.1 to 10
Input return loss(s11) -10 -12.3 -11db -12.5
Voltage gain(s21) 15.25 20.57 15 20.37
Reverse isolation(s12) -45 -23 -38 -43
Output return loss(s22) -10 -5.0 -8db -3.5
Supply voltage 1.5 1.8 1.8 1.8
Noise figure 2.8-4.7 1.6 to 3.5 3.5 to 3.9db 2.5 to 4.507
IIP3 -7 -3.8 6.4dbm -3.30db @ 6 and
70
6.1GHz
Power dissipation(mw) 14.3 14.03 16.2 22
CONCLUSION
This design employs current reuse technique with resistor feedback and source degeneration,
the input is given differentially and similarly the output is taken, in order to obtained high gain, high
linearity and minimum noise figure. The proposed design of Low Noise Amplifier is successfully
extended to UWB application as per the result obtained, as shown in table 1. It is observed that this
design is well suited for UWB application.
ACKNOWLEDGEMENT
This work has been carried out in SMDP VLSI laboratory of the Electronics and
Instrumentation Engineering Department of, Shri G.S. Institute of Technology and Science, Indore,
India. This SMDP VLSI project is funded by Ministry of Information and Communication
Technology, Government of India. Authors are thankful to the Ministry for facilities provided under
this project.
REFERENCES
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9. International Journal of Electronics and Communication Engineering Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 7, July (2014), pp. 63-71 © IAEME
[6] Abdelhalim Slimane, M. Trabelsi and M.T. Belaroussi et al., “A 0.9-V, 7-mW UWB LNA for
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AUTHOR’S DETAIL
Neeraj Malviya was born in 1989. He receives B.Eng. degree in electronics and
communication engineering from Acropolis institute of technology and research,
Indore, Madhya Pradesh, India in 2012. Currently he is pursuing M.Tech. degree
from S.G.S.I.T.S Indore, Madhya Pradesh, India. His current research interest are
low power and low noise LNAs.
R.S Gamad receives his B.E. degree in Electronics and Communication
Engineering from Government Engineering college, Ujjain, Madhya Pradesh,
India in 1995 and M.E. in Digital Techniques and Instruments from S.G.S.I.T.S,
Indore, Madhya Pradesh, India in 2003 and Ph.D. dynamic testing of an A/D
converter in 2010 from RGPV Bhopal, Technical university of Madhya Pradesh,
India. He worked as Assistant professor in Govt. engineering college, Ujjain,
Madhya Pradesh from 1999-2006. He is currently working as Associate professor
in department of Electronics and Instrumentation Engineering, S.G.S.I.T.S,
Indore, Madhya Pradesh, India. His field of specialisation is data converter, ADC design- testing,
image processing and mixed signal VLSI design. He is actively participates in SMDP project in
VLSI, a project funded by Ministry of Information and Communication Technology, Govt. of India.
He has teaching experience of over 16 years at under graduate level and 9 year at post graduate
level. He is associated with many professional societies. He is life member of Institution of
Engineers (IE) and IETE.