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CMOS Image Sensor Design_h20_3_photodiode_pixels_1sep2020.pdf
- 1. IN5350 – CMOSImage Sensor Design Lecture 3 - Light detection and 4T pixel circuit principles
- 2. Course project • Projectsize / scope: 40-60hrs total • Schedule: see next slide • Grade: Project report counts 25% of final grade (exam counts 75%) • Topic&field is flexible/optional. Some suggestions: – Analog design (e.g. SNR modelling, design&simulate pixel array and readout circuits, HDR sensor design, GS sensor design) – Digital design (e.g. RTL design: readout timing and/or ISP functions such as BLC, DPC, LENC, CI, TM, JPG) – Algorithm design (Matlab/Python: ISP, AEC, AWB) • Oblig. deliverables: (i) Project plan, (ii) Project report, (iii) Presentation • For access to nanolab in 5th floor email your name, username, and card number to Olav Stanly Kyrvestad <olavky@ifi.uio.no> • All SW (Cadence, Matlab, etc) available on all machines at IFI, as well as via remote login from external computer 2
- 3. Project schedule Task/milestone StartFinish Chose topic and define scope 1-Sep 8-Sep Create project plan (tasks, milestones, schedule) 8-Sep 15-Sep MS1 – project plan approved by Johannes 15-Sep 22-Sep Study literature on the topic (include summary in report) 22-Sep 29-Sep Design implementation&simulation 29-Sep 13-Oct Write up prelim report (inc references, design, results) 13-Oct 20-Oct MS2 – submit preliminary report to Johannes 20-Oct 20-Oct Design/simulation (fine tuning) 20-Oct 27-Oct Write up final report (incl references, design, results) 27-Oct 3-Nov MS3 – Presentation and discussion 3-Nov 3-Nov MS4 – submit final report to Johannes 10-Nov 10-Nov Exam 18-Nov 2019 3
- 4. References • Oblig materialare these slides and the accompanying exercises • Recommended books – Physics of Semiconductor Devices by Simon M. Sze and Kwok K. Ng (Oct 27, 2006) – Solid-State Imaging with Charge-Coupled Devices (Solid-State Science and Technology Library) by Albert J. P. Theuwissen (Mar 31, 1995) • Recommended online sources – Excellent PN junction literature on Wikipedia – http://pveducation.org/pvcdrom/pn-junction/conduction-in- semiconductors 4
- 5. Camera signal chain 01/09/20205 Photodiode This section
- 6. Valence band Conduction band Intrinsicsilicon 01.09.2020 6 Si atom density: 5x1022 cm-3 pi = ni ≅1010 cm-3 at 300K pi: intrinsic hole concentration (thermally generated) ni: intrinsic electron concentration (thermally generated) Electron energy, E EC EV Eg=1.12eV at RT
- 7. Photoelectric effect inSemiconductors 01.09.2020 7 - - - - - Eg Conduction band Valence band + + + + + ν h Ev Ec Condition for detection : Band-gap in Silicon: λcut-off ≈ 1,1 um Photon energy (Joule) : λ ν c h h E = = g E h ≥ ν J Eg 19 10 8 , 1 − ⋅ ≈ g E hc ≤ λ Cut-off wavelength in Silicon : Energy level
- 8. Photon absorption inSilicon Si Si Si Si Si Si Si Si Si Electron e- Hole • CMOS image sensors detect light by generating electron-hole pairs • Accumulated electrons are converted into a proportional voltage (the holes are drained to GND, ie do not contribute to signal out) h+ 01.09.2020 8 ν h
- 9. Photoelectric effect remarks •Occurs in both intrinsic and doped silicon (cf photodiode) • Normally one photon creates one electron, only. – Excess energy goes to heating – High-energy particles, e.g. X-ray, can create multiple electrons (as well as damage the Si crystal structure) • Other semiconductors with smaller bandgap energy (e.g. SiGe, PtSi) can detect longer wavelengths, i.e. in the IR spectrum 01.09.2020 9
- 10. Quantum efficiency (QE) 01.09.2020 100% QE (%) Idealresponse Wavelength (nm) Losses due to reflections, etc. Cut-off wavelength in Silicon • QE: probability of photon detection, i.e. Nelec/Nphot • Determines light sensitivity 50% 0% 300nm 1100nm Typical Silicon detector 10 Visible spectrum
- 11. QE remarks • Photo-generatedcharges outside the depletion layer do not experience any electric field. Hence, they tend to diffuse in all directions and may get lost through recombination • Depending on wavelength, photons can go several microns deep into silicon before being absorbed by a Si atom • Therefore, the larger the depletion layer width (read: low doping concentration) the better the QE 01.09.2020 11
- 12. Absorption of lightin Silicon 12 Φ(x) = Φ0𝑒𝑒𝑒𝑒𝑒𝑒(−𝛼𝛼𝛼𝛼) Φ(x): photon flux, α: absorption coefficient (cm-1) x: distance from silicon surface (cm)
- 13. Absorption of lightin Silicon (intensity versus depth) 13 ϕ(1/𝑎𝑎) =1/e=0.37 Light penetration depth, 1/α Ref: J Nakamura, ch-3
- 14. QE dependent onSi thickness, ie length of optical path in silicon 14 100% QE Wavelength Normal substrate thickness (3-5um) 50% 0% 300nm 1100nm 400nm 700nm Thick substrate (>10um)
- 15. N-type silicon withPhosphor donors 01/09/2020 15 ND: dopant concentration n0: free electron concentration n0 ≅ ND From n0p0= ni 2 we get p0 ≅ ni 2/ND Electron energy, E EC EV EF Ei qɸFn<0 𝜙𝜙𝐹𝐹𝐹𝐹 ≈ −𝜙𝜙𝑡𝑡𝑙𝑙𝑙𝑙 𝑁𝑁𝐷𝐷 𝑛𝑛𝑖𝑖 𝜙𝜙𝑡𝑡 = 𝑘𝑘𝑘𝑘 𝑞𝑞 ≈26mV at RT
- 16. P-type Silicon withBoron acceptors 01.09.2020 16 NA: dopant concentration p0 ≅ NA n0 ≅ pi 2/NA Electron energy EC EV EF Ei qɸFp>0 𝜙𝜙𝐹𝐹𝐹𝐹 ≈ 𝜙𝜙𝑡𝑡𝑙𝑙𝑙𝑙 𝑁𝑁𝐴𝐴 𝑛𝑛𝑖𝑖 𝜙𝜙𝑡𝑡 = 𝑘𝑘𝑘𝑘 𝑞𝑞 ≈26mV at RT
- 17. Electric field =∫(Charge density) 01.09.2020 17 Total charge density (⍴) is sum of all contributions: 𝜌𝜌 = 𝑞𝑞(𝑝𝑝 − 𝑛𝑛 + 𝑁𝑁𝐷𝐷 − 𝑁𝑁𝐴𝐴) (1) Gauss’s law: 𝑑𝑑𝑑 𝑑𝑑𝑑𝑑 = 𝜌𝜌(𝑦𝑦) ∈𝑠𝑠 (2) where ℇ(y)=electric field in y-direction 𝜌𝜌(𝑦𝑦)=charge density in y-position ∈𝑠𝑠=permittivity of silicon=ks∈0=11.9 x 8.854E-14 F/cm
- 18. PN junction 01.09.2020 18 Zerobias Forward bias Reverse bias
- 19. Reverse biased PNjunction 01.09.2020 19
- 20. Reverse biased PNjunction 01.09.2020 20 𝑄𝑄1 = +𝑞𝑞(𝑑𝑑1𝐴𝐴)𝑁𝑁𝐷𝐷 𝑄𝑄2 = −𝑞𝑞(𝑑𝑑2𝐴𝐴)𝑁𝑁𝐴𝐴 𝑄𝑄1 = −𝑄𝑄2 𝑑𝑑1 𝑑𝑑2 = 𝑁𝑁𝐴𝐴 𝑁𝑁𝐷𝐷 Using Gauss’ law, the electric field is the integral of charge density divided by permittivity. Thus: ℇ𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 = 𝑞𝑞𝑁𝑁𝐷𝐷𝑑𝑑1 𝜖𝜖𝑠𝑠 = 𝑞𝑞𝑁𝑁𝐴𝐴𝑑𝑑2 𝜖𝜖𝑠𝑠 Integrating the field gives the voltage. Thus: 𝜓𝜓1 = ℇ𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑑𝑑1 2 = 𝑞𝑞𝑁𝑁𝐷𝐷𝑑𝑑1 2 2𝜖𝜖𝑠𝑠 𝜓𝜓2 = ℇ𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑑𝑑2 2 = 𝑞𝑞𝑁𝑁𝐴𝐴𝑑𝑑2 2 2𝜖𝜖𝑠𝑠 𝜖𝜖𝑠𝑠 = 11.7 𝜖𝜖0 𝜖𝜖0 = 8.85 � 10−12𝐹𝐹/𝑚𝑚 ND NA
- 21. Reverse biased PNjunction • Let • where VR is the reverse bias voltage • Combining with previous page we get • where d1+d2 is the total depletion width of the reverse biased PN junction 01.09.2020 21 𝜓𝜓𝑐𝑐 = 𝜓𝜓1+ 𝜓𝜓2 = 𝑉𝑉𝑅𝑅 + 𝜙𝜙𝑏𝑏 𝑑𝑑1 + 𝑑𝑑2 = 2𝜖𝜖𝑠𝑠 𝑞𝑞 � 𝑁𝑁𝐴𝐴 + 𝑁𝑁𝐷𝐷 𝑁𝑁𝐴𝐴𝑁𝑁𝐷𝐷 � 𝜓𝜓𝑐𝑐
- 22. One-sided (n+p) stepjunction 01.09.2020 22 𝑁𝑁𝐷𝐷 >> 𝑁𝑁𝐴𝐴 𝑑𝑑2 >> 𝑑𝑑1 From above this implies 𝜙𝜙2 >> 𝜙𝜙1 𝜙𝜙2 ≅ 𝜓𝜓𝑐𝑐 This means the potential drop appears almost entirely on the p side. 𝑑𝑑2 = 2𝜖𝜖𝑠𝑠 𝑞𝑞𝑁𝑁𝐴𝐴 𝜓𝜓𝑐𝑐
- 23. PN junction lightdetector (Photodiode) 01.09.2020 23 Depletion region + - e- h+ ++++++++ ++++++++ ++++++++ ++++++++ ++++++++ ++++++++ ++++++++ ------------- ------------- ------------- ------------- ------------- ------------- ------------- N-type P-type VFD VRST VRST Exposure time VFD Low light level Medium light level Bright light
- 24. CMOS devices G D S S D BB p-substrate n-well P+ P+ n+ n+ G PMOS NMOS 01.09.2020 24
- 25. Pinned photodiode 0V p-substrate n-well P+ p+n+ n+ 01.09.2020 25 Floating diffusion output node Surface pinned to 0V Fully depleted after reset operation, i.e. at start of light integration FD Transfer gate TG
- 26. Potential well diagram TG 01.09.202026 RST VDD 1.8V 2.8V 3.0V 2.0V PD FD Vpin = photodiode pin voltage, i.e. when n- region is fully depleted
- 27. NP photodiode 27 P-doped siliconsubstrate N-doped photodiode Gate hυ e- e- e- e- e- e- e- e- Capacitive output node translates photon charges (e-) into proportional voltage drop (∆V) hυ hυ hυ hυ hυ Photons C G Source follower Vout ∆V Floating diffusion (FD) Problem: thermally generated (dark) electrons in Si/SiO2 interface (e.g. Idark=1-10nA/cm2)
- 28. Si – SiO2interface (crystal structure mismatch) 01.09.2020 28 + - Ev Ec electron hole Si/SiO2 crystal mismatch lead to interstitial energy levels that electrons use as stepping stones to reach Ec => dark current noise Ed1 Ed2 Ed3 Ed1-3: crystal defect states
- 29. Pinned photodiode 29 P-sup N-doped photodiode Transfer gate Floating diffusion node(FD) P+ doped surface layer (pinned at GND) absorbs any dark electrons SiO2
- 30. Camera signal chain 01/09/202030 Photodiode This section
- 31. Readout of pinnedphotodiode 01.09.2020 31 RST VRST VDD Mrst Msf Msel ROW COL TX Mtx RST ROW VFD Tint VCOL V1 V2 N.A. TX PD FD Mcs Vbias
- 32. Small-Signal Capacitance ofreverse biased PN junction 01.09.2020 32 Cj +∆Q -∆Q ∆VR + - If the reverse bias is increased by a small amount, then the depletion region width must increase on both sides. Hence, charges must flow on both sides of the diode. Operating region
- 33. Small-signal capacitance ofreverse biased PN junction 01.09.2020 33 ∆𝑄𝑄1= +∆𝑄𝑄 ∆𝑄𝑄2= −∆𝑄𝑄 𝐶𝐶𝑗𝑗 = ∆𝑄𝑄 ∆𝑉𝑉𝑅𝑅 𝐶𝐶𝑗𝑗 = − 𝑑𝑑𝑄𝑄2 𝑑𝑑𝑉𝑉𝑅𝑅 𝐶𝐶𝑗𝑗′ = 𝐶𝐶𝑗𝑗 𝐴𝐴 𝐶𝐶𝐶𝑗𝑗 = − 𝑑𝑑𝑄𝑄𝑄2 𝑑𝑑𝑉𝑉𝑅𝑅 𝐶𝐶𝑗𝑗 ′ = 2𝑞𝑞𝜖𝜖𝑠𝑠𝑁𝑁𝐴𝐴 2 𝑉𝑉𝑅𝑅 + 𝜙𝜙𝑏𝑏𝑏𝑏 = 𝜖𝜖𝑠𝑠 𝑑𝑑2 One sided: 𝑄𝑄2 ′ = − 2𝑞𝑞𝜖𝜖𝑠𝑠𝑁𝑁𝐴𝐴𝜙𝜙2 𝜙𝜙2 = 𝑉𝑉𝑅𝑅 + 𝜙𝜙𝑏𝑏𝑏𝑏
- 34. One-sided step junctionsmall-signal capacitance vs reverse-bias voltage 01.09.2020 34 Note: CMOS pixels use reverse biased diode capacitance (aka floating diffusion node) to convert photon charge into voltage. Above voltage dependency can sometimes cause non-linear response.
- 35. Camera signal chain 01/09/202035 Photodiode This section
- 36. Introduction • SF usedin almost every digital camera that exists; used in both CMOS and CCD sensors • Widely used also in general ASICs as a voltage buffer which can drive large capacitive loads • Widely used due to its small size (only one transistor inside pixel) which maximizes photodiode area 01.09.2020 36
- 37. SF in 4Tpixel 01.09.2020 37 RST VRST VDD Mrst Msf Msel ROW COL TX Mtx RST ROW VFD Tint VCOL V1 V2 N.A. TX PD FD Mcs Vbias
- 38. NMOS source follower 01.09.202038 Mcs Vbias Msf Vin Vout D G S D G S B B • Both devices in saturation • Mcs acts as a fixed current source (IDS set by Vbias) • Fixed IDS implies that VGS of Msf is fixed. Thus, Vout ‘follows’ Vin keeping a constant VGS • VSB of Msf is not zero => body effect applies VDD
- 39. Small signal equivalentcircuit of SF 01.09.2020 39 gmvgs gmbvsb vgs vout=vsb vin r02 r01 𝐴𝐴𝑣𝑣 = 𝑣𝑣𝑜𝑜𝑜𝑜𝑜𝑜 𝑣𝑣𝑖𝑖𝑖𝑖 = 𝑔𝑔𝑚𝑚 𝑔𝑔𝑚𝑚 + 𝑔𝑔𝑚𝑚𝑚𝑚 + 1 𝑟𝑟01 + 1 𝑟𝑟02 𝑅𝑅𝑜𝑜 = 1 𝑔𝑔𝑚𝑚 + 𝑔𝑔𝑚𝑚𝑚𝑚 + 1 𝑟𝑟01 + 1 𝑟𝑟02
- 40. SF remarks • Msfsources current, Mcs sinks current – Asymmetric drive capability – Check both rising and falling edge settling • Acts as a level shifter where Vout equals Vin minus approx. Vth – For PMOS: Vout equals Vin plus Vth • To keep Mcs in pinch-off (saturation), Vout cannot go too low => limited useful voltage swing – Typical requirement: allow max 1% deviation from the linear (straight line) curve 01.09.2020 40
- 41. For hand calculationsof devices in saturation use: 01.09.2020 41 𝑔𝑔𝑚𝑚 = 𝜇𝜇𝑛𝑛𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊 𝐿𝐿 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 2𝜇𝜇𝑛𝑛𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊 𝐿𝐿 𝐼𝐼𝐷𝐷 𝑟𝑟𝑜𝑜 = 1 𝜆𝜆𝐼𝐼𝐷𝐷 Assume: gmb<<gm 𝜆𝜆=0.1V-1 𝜇𝜇𝑛𝑛𝐶𝐶𝑜𝑜𝑜𝑜=400uA/V2