This document describes the design of memory address decoders for different memory configurations: 1. An 8Kx16 memory starting at address 30000h is described using discrete components for the address decoder and control signals MRD and MWR. 2. The same 8Kx16 memory configuration is then described using a 74138 line decoder instead of discrete components. 3. The changes needed for both the discrete and 74138 implementations if the starting address was changed to C0000h are discussed. 4. Finally, the changes needed for both implementations if the memory size was increased to 16Kx16 instead of 8Kx16 are outlined.

2. MEMORY
ADDRESS DATA
WR
OE
CE
MWR
MRD
CS

3. mbits
m bits
Address
bus
m bits
2n bits
Control
bus
Data bus
RAM 2m´ 2n
Data
in/out
RAM 2
2m´ n
RAM 1
2m
´ n
Data
in/out
D
D
nbits n bits

4. A17
A18
A19
A14
A15
A16
A0 BHE
8KX8
CS
A1-A13
D0-D7
8KX8
CS
A1-A13
D8-D15
A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0 BHE BANK
1 1 1 1 1 1 0 – 8K 0 0/1 BOTH/LOW
1 1 1 1 1 1 0 – 8K 0/1 0 BOTH/HIGH
F C 0 0 0 - F F F F E F C 0 0 0 - F F F F F
LOW BANK HIGH BANK
0
0
0
1
1
1
1
1
1

5. MEMORY
ADDRESS
DATA
WR
OE
CE
MWR
MRD
CS
M/ IO
WR
RD
0
0
0
0
0
0
1

6. A17
A18
A19
A14
A15
A16
A0 BHE
8KX8
CS
A1-A13
D0-D7 8KX8
CS
A1-A13
D8-D15
A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK
1 1 1 1 1 1 0 – 8K 0/1 LOW
1 1 1 1 1 1 0 – 8K 1/0 HIGH
F C 0 0 0 - F F F F E F C 0 0 0 - F F F F F
LOW BANK HIGH BANK
M/ IO
WR
RD
RD
RD
WR
WR

7. A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK
1 1 1 1 1 1 0 – 8K 0/1 LOW
1 1 1 1 1 1 0 – 8K 1/0 HIGH
A0 BHE
8KX8
CS
A1-A13
D0-D7 8KX8
CS
A1-A13
D8-D15
F C 0 0 0 - F F F F E F C 0 0 0 - F F F F F
LOW BANK HIGH BANK
M/ IO
WR
RD
RD
RD
WR
WR
A17
A18
A19
A14
A15
A16
A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK
0 0 0 0 0 0 0 – 8K 0/1 LOW
0 0 0 0 0 0 0 – 8K 1/0 HIGH
0 0 0 0 0 - 0 3 F F E 0 0 0 0 0 - 0 3 F F F

8. Data
bus
RAM 2M ´ 8
Address
bus
21 bits
Control
bus
20 bits
EN
EN
RAM 2
1M ´ 8
RAM 1
1M ´ 8
8 bits
8 bits
8 bits
20 bits

9. 8KX8
CS
8KX8
CS
A0
A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK
0 0 0 0 0 0 1 0 – 8K 0/1 LOW
0 0 0 0 0 0 1 0 – 8K 1/0 HIGH
BHE
8KX8
CS
A1-A13
D0-D7 8KX8
CS
A1-A13
D8-D15
LOW BANK HIGH BANK
M/ IO
WR
RD
RD
RD
WR
WR
A17
A18
A19
A14
A15
A16

10. 8KX8
CS
8KX8
CS
8KX8
CS
8KX8
CS
A0
A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK
0 0 0 0 0 0 1 0 – 8K 0/1 LOW
0 0 0 0 0 0 1 0 – 8K 1/0 HIGH
BHE
8KX8
CS
A1-A13
D0-D7 8KX8
CS
A1-A13
D8-D15
LOW BANK HIGH BANK
M/ IO
WR
RD
RD
RD
WR
WR
A17
A18
A19
A14
A15
A16

11. 8KX8
CS
8KX8
CS
8KX8
CS
8KX8
CS
8KX8
CS
A1-A13
D0-D7 8KX8
CS
A1-A13
D8-D15
LOW BANK HIGH BANK
M/ IO
WR
RD
RD
RD
WR
WR
ADDRESS
DECODER
A14-A19
A0
BHE

12. 0
0
0
0
0
1
0
1
0
1
0
1
3 8

13. A1-A13
D0-D7
74LS138
A14
A15
A16
M/ IO
A0
G2A
G2B
G1
A
B
C
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
8KX8
CS
CS
CS
CS
CS
CS
CS
CS
A17
A18
A19
RD
WR
00000-03FFE
04000-07FFE
08000-0BFFE
0C000-0FFFE
10000-13FFE
14000-17FFE
18000-1BFFE
1C000-1FFFE
LOW BANK

14. BHE
A1-A13
D8-D15
74LS138
A14
A15
A16
M/ IO
G2A
G2B
G1
A
B
C
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
8KX8
CS
CS
CS
CS
CS
CS
CS
CS
A17
A18
A19
RD
WR
00000-03FFF
04000-07FFF
08000-0BFFF
0C000-0FFFF
10000-13FFF
14000-17FFF
18000-1BFFF
1C000-1FFFF
HIGH BANK

15. 2764
8KX8
2764
8KX8
A1-A13
D0-D7
74LS138
A14
A15
A16
M/ IO
A0
G2A
G2B
G1
A
B
C
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
8KX8
CS
CS
CS
CS
CS
CS
CS
CS
A17
A18
A19 RD
WR
LOW
BANK
A1-A13
D8-D15
74LS138
A14
A15
A16
M/ IO
G2A
G2B
G1
A
B
C
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
8KX8
CS
CS
CS
CS
CS
CS
CS
CS
A17
A18
A19
RD
WR
HIGH
BANK
BHE

16. 1. Draw The address decoder (using discrete
components) for 8KX16 memory starting at
30000h with MRD & MWR cct.
2. Repeat (1) above but using 74138 line decoder.
3. What will be changed (for both 1 &2 of the
above) if the start address becomes C0000h?
4. What will be changed (for both 1 &2 of the
above) if 16KX16 memory is needed instead of
8KX16 memory?