This slide is used for fifth year student of Computer Engineering Department, Hanoi University of Technology.

1. Thiết kế nhờ máy tính Nguyễn Thành Kiên Bộ môn Kỹ thuật Máy tính Khoa Công nghệ thông tin, ĐH BKHN

13. Quy trình thiết kế mạch dựa trên VHDL

15. Một ví dụ VHDL đơn giản

16. Một ví dụ VHDL đơn giản

18. Code structure library IEEE; use IEEE.std_logic_1164.all; ENTITY full_adder IS PORT (a,b,cin: in bit; s,cout:out bit); END full_adder; Architecture dataflow of full_adder is begin s <= a xor b xor cin; cout <= (a and b) or (a and cin) or (b and cin); end dataflow;

29. Ví dụ về ENTITY ENTITY mux IS PORT (a, b: IN std_logic_vector(7 downto 0); sel: IN STD_LOGIC_VECTOR(0 to 1); c: OUT STD_LOGIC_VECTOR(7 downto 0)); END mux;

35. library IEEE; use IEEE.std_logic_1164.all; ENTITY adder IS PORT (A,B: IN std_logic_vector(7 downto 0); C: OUT std_logic_vector(7 downto 0)); END adder; Architecture dataflow of adder is begin C <= A+B; end dataflow; Adder A(7:0) B(7:0) C(7:0)

39. VD3: asyn-reset DFF & NAND ENTITY example IS PORT ( a, b, clk: IN BIT; q: OUT BIT); END example; --------------------------------------- ARCHITECTURE example OF example IS SIGNAL temp : BIT; BEGIN temp <= a NAND b; PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN q<=temp; END IF; END PROCESS; END example; --------------------------------------- Sự kết hợp giữa mạch tổ hợp và mạch dãy DEMO

40. VD4: Bộ dồn kênh Multilpexor a,b: hai kênh vào 8bit sel: các bit chọn kênh c: kênh ra 8bit

57. LIBRARY ieee; USE ieee.std_logic_1164.all; ----------------------------------------- ENTITY mux IS PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; y: OUT STD_LOGIC); END mux; ----------------------------------------- ARCHITECTURE not_ok OF mux IS SIGNAL sel : INTEGER RANGE 0 TO 3; BEGIN PROCESS (a, b, c, d, s0, s1) BEGIN sel <= 0; IF (s0='1') THEN sel <= sel + 1;END IF; IF (s1='1') THEN sel <= sel + 2;END IF; CASE sel IS WHEN 0 => y<=a; WHEN 1 => y<=b; WHEN 2 => y<=c; WHEN 3 => y<=d; END CASE; END PROCESS; END not_ok; LIBRARY ieee; USE ieee.std_logic_1164.all; ----------------------------------------- ENTITY mux IS PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; 7y: OUT STD_LOGIC); END mux; ----------------------------------------- ARCHITECTURE ok OF mux IS BEGIN PROCESS (a, b, c, d, s0, s1) VARIABLE sel : INTEGER RANGE 0 TO 3; BEGIN sel := 0; IF (s0='1') THEN sel := sel + 1; END IF; IF (s1='1') THEN sel := sel + 2; END IF; CASE sel IS WHEN 0 => y<=a; WHEN 1 => y<=b; WHEN 2 => y<=c; WHEN 3 => y<=d; END CASE; END PROCESS; END ok;

58. So sánh giữa Signal & Variable

61. 3.2. Các kiểu dữ liệu VHDL

67. ENTITY traffic_light IS PORT(sensor : IN std_logic; clock : IN std_logic; red_light : OUT std_logic; green_light : OUT std_logic; yellow_light : OUT std_logic); END traffic_light; ------------------------------------------------------------ ARCHITECTURE simple OF traffic_light IS TYPE t_state is (red, green, yellow); Signal present_state, next_state : t_state; BEGIN PROCESS(present_state, sensor) BEGIN CASE present_state IS WHEN green => next_state <= yellow; red_light <= ‘0’; green_light <= ‘1’; yellow_light <= ‘0’; WHEN red => red_light <= ‘1’; green_light <= ‘0’; yellow_light <= ‘0’; IF (sensor = ‘1’) THEN next_state <= green; ELSE next_state <= red; END IF; WHEN yellow => red_light <= ‘0’; green_light <= ‘0’; yellow_light <= ‘1’; next_state <= red; END CASE; END PROCESS; PROCESS BEGIN WAIT UNTIL clock’EVENT and clock=‘1’; present_state <= next_state; END PROCESS; END simple;

85. Kiểu bản ghi record TYPE word IS ARRAY(0 TO 3) OF std_logic; TYPE t_word_array IS ARRAY(0 TO 15) OF word; TYPE addr_type IS RECORD source : INTEGER; key : INTEGER; END RECORD; TYPE data_packet IS RECORD addr : addr_type; data : t_word_array; checksum : INTEGER; parity : BOOLEAN; END RECORD; PROCESS(X) VARIABLE packet : data_packet; BEGIN packet.addr.key := 5; --Ok packet.addr := (10, 20); --Ok packet.data(0) := (‘0’, ‘0’, ‘0’, ‘0’); packet.data(10)(4) := ‘1’; --error packet.data(10)(0) := ‘1’; --Ok END PROCESS;

90. Các kiểu DL có thể tổng hợp

92. Đề tài môn học Thiết kế nhờ MT Nhóm: 6 người/nhóm