ISSN: 2278 – 1323                         International Journal of Advanced Research in Computer Engineering & Technology ...
ISSN: 2278 – 1323                                 International Journal of Advanced Research in Computer Engineering & Tec...
ISSN: 2278 – 1323                                              International Journal of Advanced Research in Computer Engi...
ISSN: 2278 – 1323                                      International Journal of Advanced Research in Computer Engineering ...
ISSN: 2278 – 1323                                    International Journal of Advanced Research in Computer Engineering & ...
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  1. 1. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology Volume 1, Issue 5, July 2012 Design and Verification Eight Port Router for Network on Chip Sana.Ranjitha,IEEE-2012,B.Vijay Bhaskar ,R.SuryaPrakash St.Theressa College of Engineering,JNTU-2012ABSTRACT`: Multiprocessor system on chip is with less effort. Recent advancement towards thisemerging as a new trend for System on chip design goal is methodologies. The methodology defines abut the wire and power design constraints are skeleton over which one can add flesh and skin toforcing adoption of new design methodologies. their requirements to achieve functional verification.Researchers pursued a scalable solution to this OVM (open verification methodology) is one suchproblem i.e. Network on Chip (NOC). Network on efficient methodology and best thing about it is, it ischip architecture better supports the integration of free. This ovm is built on system Verilog and usedSOC consists of on chip packet switched network. effectively to achieve maintainability, reusability,Thus the idea is borrowed from large scale speed of verification etc. This project is aimed atmultiprocessors and wide area network domain building a reusable test bench for verifying 8 Portand envisions on chip routers based network. Cores Router Protocol Bridge by using system Verilog andaccess the network by means of proper interfaces ovmand have their packets forwarded to destination In this document the use of vmm and systemthrough multichip routing path. In order to Verilog to verify a design and to develop a reusableimplement a competitive NOC architecture, the test bench is explained in step by step as defined byrouter should be efficiently design as it is the verification principles and methodology. The testcentral component of NOC architecture. Design bench contains different components and eachAnd Verify the functionality of the “Design and component is again composed of subcomponents,Verification Eight Port Router for Network on these components and subcomponents can be reusedChip” IP core using the latest verification for the future projects as long as the interface ismethodologies, Hardware Verification Languages same.and EDA tools and qualify the IP for Synthesis animplementation. Router: System on chip is a complex interconnection of various functional elements. It creates Introduction communication bottleneck in the gigabit communication due to its bus based architecture. My research is based on the paper” router Thus there was need of system that explicitdesign for network on chip”. Now in this paper I modularity and parallelism, network on chip possesshave designed a eight port router which is the many such attractive properties and solve theadvancement for the previous four port router problem of communication bottleneck. It basicallynetwork.But in the four port network we have the works on the idea of interconnection of cores usingability to connect a network of four systems which is on chip I extended this network upto 8 ports The communication on network on chip isand I observed the results using verilog HDL. carried out by means of router, so for implementing better NOC , the router should be efficiently design. The challenge of the verifying a large design This router supports four parallel connections at theis growing exponentially. There is a need to define same time. It uses store and forward type of flownew methods that makes functional verification easy. control and Fsm Controller deterministic routingSeveral strategies in the recent years have been which improves the performance of router. Theproposed to achieve good functional verification 42 All Rights Reserved © 2012 IJARCET
  2. 2. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology Volume 1, Issue 5, July 2012switching mechanism used here is packet switching packet is driven out. The router has an active lowwhich is generally used on network on chip. synchronous input resetn which resets the router. In packet switching the data the data .Data packet moves in to the input channeltransfers in the form of packets between cooperating of one port of router by which it is forwarded to therouters and independent routing decision is taken. output channel of other port. Each input channel andThe store and forward flow mechanism is best output channel has its own decoding logic whichbecause it does not reserve channels and thus does increases the performance of the router. Buffers arenot lead to idle physical channels. The arbiter is of present at all ports to store the data temporarily.rotating priority scheme so that every channel once The buffering method used here is store andget chance to transfer its data. In this router both forward. Control logic is present to make arbitrationinput and output buffering is used so that congestion decisions. Thus communication is establishedcan be avoided at both sides. between input and output ports.. According to the A router is a device that forwards data destination path of data packet, control bit lines ofpackets across computer networks. Routers perform FSM are set. The movement of data from source tothe data "traffic direction" functions on the Internet. destination is called switching mechanism TheA router is a microprocessor-controlled device that is packet switching mechanism is used here, in whichconnected to two or more data lines from different the flit size is 8 bits .Thus the packet size varies fromnetworks. When a data packet comes in on one of 0 bits to 8 bits. A detailed explanation of Design isthe lines.the router reads the address information in as followthe packet to determine its ultimate destination.Then, using information in its routing table, it directsthe packet to the next network on its journey. The router is a ” Eight Port NetworkRouter” has a one input port from which the packet DATA outenters. It has seven output ports where the packet is packet_validdriven out. Packet contains 3 parts. They are Header, VLD out suspend_datadata and frame check sequence. Packet width is 8bits and the length of the packet can be between 1 err 8 Port Read Enablebytes to 64 bytes. Packet header contains three fields RoutersDAand length.Destination address(DA) of the packetis of 8 bits. The switch drives the packet to clockrespective ports based on this destination address of resetthe packets. Each output port has 8-bit unique portaddress. If the destination address of the packetmatches the port address, then switch drives the Block Diagram Of Eight Port Routerpacket to the output port, Length of the data is of 8bits and from 0 to 63. Length is measured in terms ofbytes. Data should be in terms of bytes and can takeanything. Frame check sequence contains thesecurity check of the packet. It is calculated over theheader and data.Router is a packet based protocol. Router drives theincoming packet which comes from the input port tooutput ports based on the address contained in thepacket The router has a one input port from whichthe packet enters. It has three output ports where the 43 All Rights Reserved © 2012 IJARCET
  3. 3. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology Volume 1, Issue 5, July 2012 8 7 6 4 3 21 0 Data registers latches the data from data Length addr byte 0 Header input based on state and status control signals, and data[0] byte 1 this latched data is sent to the fifo for storage. Apart data[1] from it, data is also latched into the parity registers Payload for parity calculation and it is compared with the parity byte of the packet. An error signal is generated if packet parity is not equal to the calculated parity data[N] byte N+1 parity byte N+2 ParityData Packet Format clock delay reset packet_valid data H D D D P H D D D PSuspend_data err sent packet Packet 1 (addr = 0) Packet 1 (addr = 0) H = Header, D = Data, P = Parity Router Input Protocolclockresetpacket_validdata H D D D P H D D D Pvld_out_0 response delayread_enb_0data_out_0 H D D D Preceived Packet 1 (addr = 0)packet Router output ProtocolRegister Block: This module contains status, data and parityregisters required by router. All the registers in thismodule are latched on rising edge of the clock. 44 All Rights Reserved © 2012 IJARCET
  4. 4. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology Volume 1, Issue 5, July 2012 Router Output Block There are 7 fifos used in the router design. Each fifo is of 8 bit width and 16 bit depth. The fifo works on system clock. It has synchronous input signal reset. 8 Port Router Output If resetn is low then full =0, empty = 1 and data_out =0 Conclusion The FIFO has doing 7 deferent operations As the functional verification decides the Write Operation quality of the silicon, we spend 60% of the design Read operation cycle time only for the verification/simulation. In Read and Write Operation order to avoid the delay and meet the TTM, we use The functionality of FIFO explain Below the latest verification methodologies and technologies and accelerate the verification process. This project helps one to understand the complete functional verification process of complex ASICs an SoC’s and it gives opportunity to try the latest verification methodologies, programming concepts like Object Oriented Programming of Hardware Four port Router FIFO Verification Languages and sophisticated EDA tools, Write operation: for the high quality verification. The FIFO write operation is done by when the data from input data_in is sampled at rising edge of In this Four Port Router project I Design and the clock when input write_enb is high and fifo is verified the functionality of Router with the latest not this condition onaly FIFO Write operation Verification methodology i.e.,System Verilog and is done. observed the code coverage and functional coverage Read Operation: of Router by using coverpoints ,cross and different The FIFO Read Operation is The data is read test cases like constrained, weighted and directed from output data_out at rising edge of the clock, testcases.By using these testcases I improved the when read_enb is high and fifo is not empty. functional coverage of Router. In this I used one Read and Write operation can be done master and eight slaves to monitor the Router.Thus simultaneously. the functional coverage of Router was improved. Full – it indicates that all the locations inside fifo has The results shows that System Verilog been written. methodology can be used to make reusable test Empty – it indicates that all the locations of fifo are benches successfully. Large part of the test bench is empty. made reusable over multiple projects.even though this reusablity is limited to the interfaces. A large class of devices that are build on these inerfaces can be verified successfully. Once these components are 45 All Rights Reserved © 2012 IJARCET
  5. 5. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology Volume 1, Issue 5, July 2012 made the amount of time required to build test  Router for NOC by Michael K. Papamichael benches for other projects can be reduced a lot.  Writing test benches using system Verilog by Janick Bergeron References  OVM Cook book Verilog HDL- Digital Design and Synthesis, by  OVM Reference manual Samir Palnitkar Websites  Open Cores project site  CISCO Integrated Services Router –SRND(Solution Reference Network Design) document  NORTEL ISP Router Design document.  VMM User guide  VMM Reference manual System Verilog for verification by Chris Spear 46 All Rights Reserved © 2012 IJARCET