Recent Advances in Low-Dimensional Heterojunction-Based Tunnel Field Effect Transistors

PROGRESS REPORT
1800569 (1 of 15) © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
www.advelectronicmat.de
Recent Advances in Low-Dimensional Heterojunction-
Based Tunnel Field Effect Transistors
Yawei Lv, Wenjing Qin, Chunlan Wang, Lei Liao,* and Xingqiang Liu*
DOI: 10.1002/aelm.201800569
depleted silicon-on-insulator (FDSOI)
configuration.[5] However, because of the
60 mV dec−1 limitation in the subthreshold
swing (SS) of traditional MOSFETs,[6–8]
effective method to reduce supply voltage
is still under exploration.
Owing to the carriers’ band-to-band tun-
neling (BTBT) transport mechanism,[9–11]
the SS limitation can be conquered by
tunnel FETs (TFETs). It is believed that
TFETs based on ultrathin semiconducting
films or nanowires could achieve a 100-
fold power reduction over MOSFETs.[6]
Early TFETs made of bulk materials
suffer from low tunneling ability caused
by uniform band structures and rough
interfaces. The explosive expansion of
low-dimensional materials after the redis-
covery of graphene in 2004 has inspired
worldwide efforts on TFET designs based
on these materials because of their high
current densities,[12,13] easily modulated
electronic properties,[14,15] and clean sur-
faces and interfaces.[16,17] Furthermore,
they can be fabricated into heterojunctions
(HJs) via thickness, width, van der Waals (vdW) stacking, and
other engineering methods due to their unique quantum con-
finement properties. The introducing of HJs can improve the
on- and off-state behaviors of TFETs simultaneously, which has
become the research focus in recent years. For an example, the
high carrier mobilities in graphene make it very suitable for
source injector, which is called the Dirac source.[18,19] A vital
drawback of graphene is the absence of bandgap between its
conduction and valence bands, leading to large off-state cur-
rent (Ioff).[20]
Therefore, alternative insulation layer is needed,
resulting in an interlayer TFET structure (ITFET) together with
the graphene.[12,21–23]
The current on-to-off (Ion/Ioff) ratios in the
ITFETs have reached several decades now, much larger than
the original graphene’s.
Here, this progress report is devoted to introducing the TFET
designs based on low-dimensional material HJs. Before that,
the device physics of TFETs are introduced briefly (Figure 1).
Then, the HJ construction strategies developed in recent years
are studied (Figure 2a). Based on these HJs, different kinds
of TFETs are introduced, including lateral and vertical vdW HJ
TFETs, hot electron transistors (HETs), and Dirac-source FETs
(Figure 2b). After performance demonstrations, the emerging
problems towards these TFETs are studied (Figure 2c). The
potential solutions and improvements are also proposed
with the assistance of simulation and modeling methods
Since the continuous scaling down of the transistor channel length, extraor-
dinary improvement is achieved in the switching speed. However, the rising
leakage current degrades the power consumption seriously. In this regard,
reducing supply voltage might be the most effective method. This require-
ment can be fulfilled well by tunnel field-effect transistors (TFETs), because
carriers transport via a band-to-band tunneling manner in the TFETs. Relying
on the special transport mechanism, the TFETs often require band structure
modulations and steep interfaces without trap state, which are challenging
for bulk materials. Therefore, these challenges have boosted TFET designs
based on low-dimensional materials ranging from Si/Ge nanowires to state-
of-art van der Waals heterostructures. Here, the key concepts of the currently
developed TFETs are studied from the aspects of structure, material, trans-
portation characteristic, and mechanism. According to the heterojunction
bonding types, they can be divided into lateral and vertical TFETs in general.
Furthermore, other related transistors based on tunneling are also included.
Emerging problems and promotion methods toward these TFETs are intro-
duced with the assistance of simulations. The main goal is to introduce the
frontiers of TFET explorations and provide readers with a perspective on how
to realize TFET applications in the future.
Tunnel Field Effect Transistors
Dr. Y. Lv, Prof. L. Liao, Prof. X. Liu
School of Physics and Electronics
Hunan University
Changsha, Hunan 410082, P. R. China
E-mail: liaolei@whu.edu.cn; liuxq@hnu.edu.cn
Dr. W. Qin
School of Physics and Electronics
Hunan Normal University
Changsha, Hunan 410081, P. R. China
Prof. C. Wang
School of Science
Xi’an Polytechnic University
Xi’an 710048, China
1. Introduction
One of the key words for the next-generation complementary
metal-oxide-semiconductor (CMOS) field-effect transistors
(FETs) is “low power.” As the continuous scaling down of tech-
nology node, power consumption caused by leakage current,[1]
short channel effect (SCE),[2] and other technical issues have
been studied intensely. Many strategies have been proposed
to solve this problem, including Fin-FET structure,[3]
alterna-
tive materials such as GeSi and III–V compounds,[4]
and fully
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(Figure 2d). Finally, the TFET simulation theory based on the
nonequilibrium Green’s function (NEGF) formalism is shown,
which is regarded as the most general and rigorous method in
quantum transport calculation. We conclude this report with a
performance comparison between the experimental results and
the theoretical modeling. Despite the long way to realize TFET
applications, they are still very promising for the next-genera-
tion integrated circuits (IC).
2. Brief Introduction to Band-to-Band Tunneling
Mechanism
According to quantum physics, a particle can pass through a
classically forbidden potential energy barrier through tunneling.
Different from conventional MOSFETs, in which the carrier
transports rely on thermionic emission over channel barriers,
carrier injections in TFETs primarily depend on the BTBT mech-
anism.[6,24] This mechanism can be explained intuitively through
a typical p–i–n structure, in which the source and drain regions
are heavily doped by p- and n-type impurities, leaving the channel
region undoped. At off-state (Figure 1a), the conduction band
(CB) of the drain is higher than the valence band (VB) of the
source in energy, no tunneling phenomenon being observed. The
leakage currents are mainly induced by thermionic emission.
When a positive gate voltage is applied (Figure 1b), the channel
potential is lowered, opening a tunneling window between the
VB of the source (almost filled with electrons) and the CB of
the channel (almost empty). Note that the two boundaries of the
window have prevented the carriers in higher or lower energies
from being transported. Generally, carriers within the tunneling
window possess lower energies compared with the thermionic
carriers in MOSFETs. Therefore, currents in TFETs are very
weakly dependent on the temperature.[25] This strict window also
contributes to the TFETs’ lower than 60 mV dec−1 SS behavior.
To outperform conventional transistors, the primary request
for TFET optimization is to boost their on-state performance.
According to the Wentzel–Kramer–Brillouin (WKB) approxi-
mation,[26,27] the tunneling probabilities in TFETs can be sig-
nificantly improved by reducing the bandgaps in the tunneling
regions. On the other hand, small bandgaps will also enhance
reverse hole injections from the CB of the drain to the VB of
the channel at off-state, degrading the TFETs’ off-state behav-
iors. The solution toward this problem is to build HJs in which
the bandgaps of different segments are different. In an ideal
HJ, the band structures in both sides of the junction are inde-
pendent. In this case, the corresponding TFETs on- and off-
states can be separately manipulated by the two segments of
the HJ. For an example (Figure 1c), if only the bandgap of the
source region is reduced, a shorter tunneling length at on-state
will be obtained without increasing the reverse hole injections,
suggesting that excellent on- and off-state behaviors of the
TFET can be achieved simultaneously.[28]
3. Heterojunction Construction
The WKB approximation has suggested that the bandgap and
effective mass in the tunneling region should be minimized for
Yawei Lv is an assistant
professor of electronic
science and technology
at Hunan University. He
received his Ph.D. degree in
microelectronics from Wuhan
University in 2018. His
research involves quantum
transport simulations of low-
dimensional material based
electronic devices.
Lei Liao is a professor of
electronic science and tech-
nology at Hunan University.
He received his Ph.D. degree
in physics from Wuhan
University in 2009. He was a
professor and head of depart-
ment of microelectronics
in Wuhan University before
joining Hunan University in
2016. His research involves
design and synthesis of low-
dimensional materials and processing methods for high-
performance electronics.
Xingqiang Liu is an asso-
ciate professor of electronic
science and technology
at Hunan University. He
received his Ph.D. degree
in physics from Wuhan
University in 2015. He joined
the School of Electronics and
Science at Hunan University
in 2016. His research involves
design of high-performance
low-power electronics.
high tunneling probability.[26,27]
Early TFETs built on bulk Si suf-
fered from poor on-state behavior because of the long tunneling
length. The large bandgap of Si and the nonideal doping profile
had led to this problem jointly. To boost tunneling, HJs were
adopted later by component modulations in III–V compound
materials. The bandgaps and tunneling lengths in the source–
channel interfaces were reduced effectively.[29,30]
Now, the on-
state current of the TFET built on an InAs/InGaAsSb/GaSb HJ
nanowire has reached several µA µm−1
.[31]
On the other hand, too small bandgap will degrade the
off-state behavior, which also should be avoided. Graphene, a
famous high mobility material, cannot be used for transistors
operating at room temperature because of the zero-bandgap
characteristic.[32–34]
Consequently, TFETs based on graphene
bear large leakage currents at off-state. Despite the large Ion,

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the Ion/Ioff ratios remain small values even in simulations.[35]
To meet the requirements of carrier blocking and tunneling at
off- and on-state simultaneously, HJ maybe the only feasible
method. In this section, we introduce the lateral and vertical
vdW HJs. For the lateral HJs, different segments are covalently
connected, demonstrating high reliability in applications. How-
ever, the synthesis technologies are complicate. In contrast, it is
simple to fabricate the vertical vdW HJs through exfoliation and
restacking methods, but the reliability needs to be improved.
3.1. Lateral Heterojunctions
As aforementioned, graphene is a zero-bandgap material.
Band structure engineering should be adopted before its TFET
applications. It is well known that the bandgap of graphene
and be induced by tailoring it into nanoribbons (GNRs).[36]
Along the scaling ribbon width, the bandgap variations are
non-monotonic and they can be divided into three families.[37]
Naturally, a lateral HJ can be constructed by connecting the
GNRs with different widths.[38–40] Although this kind of GNR
HJs had been investigated and used in TFET designs theoreti-
cally,[41–43] the realization was not an easy task, because of the
bad band width control ability in GNR technologies. Besides,
this HJ constructing method was also controversial in simu-
lations since the eigenstates in one segment might penetrate
into the others.[38,39,44–46] Until 2015, Chen et al. had experimen-
tally demonstrated a 7-13-7 width-modulated armchair GNR
(AGNR) HJ via the bottom-up synthesis method (Figure 3a).[17]
They had also confirmed that the electronic structure in this HJ
was spatially modulated, corresponding to type I HJ behavior.
Recently, Wang et al. further studied the quantum dot effect
using a 7-14-7 AGNR HJ,[47] suggesting that it was promising
to construct HJs in GNRs through the width modulation. We
found that interface states might exist in the zigzag edges of the
wide–narrow junctions.[43] These states pinned the Fermi levels
of the channels partially, restraining the tunneling at on-state.
To eliminate the interface states, we further proposed a GNR
HJ strategy in simulation using segmental edge saturation on
a uniform width GNR.[28] The bandgaps of different GNR seg-
ments were tuned by the edge saturation atoms. Therefore, the
interface zigzag edges were removed, so did their related states.
Additionally, there are also many other methods towards gra-
phene or GNR HJs, such as the controllable dehydrogenation
and partial doping.[48,49] The diverse HJ strategies make gra-
phene a competitive candidate in TFET applications.
Figure 1. Principle of TFET operation. a,b) Band structure diagrams of a uniform material TFET at off- and on-states. c) Band structure diagram of
a HJ TFET at on-state. The bandgap of the source region is smaller than other regions. Therefore, the tunneling length is reduced compared to the
uniform material TFET.
Figure 2. Schematic outline of this report. Reproduced with permission.[16,74,126,130,137] c) Copyright 2018, Nature Publishing Group; a) Copyright 2018,
Nature Publishing Group; d) Copyright 2016, Nature Publishing Group; b) Copyright 2018, IEEE; and c) Copyright 2015, IEEE, respectively.

1800569 (4 of 15)
Another 2D HJ construction method is to synthesize dif-
ferent materials in the same plane directly. This procedure
often requires strict process conditions. Gong et al. had synthe-
sized a WS2/MoS2 lateral HJ through vapor growth at low tem-
perature.[50] Gao et al. had produced a Graphene/h-BN in-plane
HJ via chemical vapor deposition (CVD) and using benzoic
acid precursor.[51] It required a more than 900 °C environment
temperature and the lateral HJ would be changed into vertical
one if the temperature was lowered. Zhang et al. had reported
a general synthesis strategy for highly robust grown of diverse
lateral HJs and superlattices.[52] A wide range of HJs including
WS2–WSe2 and WS2–MoSe2 were fabricated. Most recently,
via a one-pot synthetic approach, monolayer transition-metal
dichalcogenide (TMD) lateral HJs had been synthesized by
Sahoo et al. (Figure 3b).[53] By changing the reactive gas compo-
sition in the presence of water vapor, the sequential formation
of HJs was achieved. Undoubtedly, these works have stimulated
the explorations on 2D material based lateral HJs.[54–56]
Unlike graphene, many 2D materials possess bandgaps ini-
tially. Along the reducing number of layers, the bandgaps of
the TMDs all increase gradually and the indirect-to-direct gap
variations are observed,[57,58]
making the bandgap modulation
based on thickness engineering possible. However, considering
the relatively low carrier mobilities which lead to small Ion,[59,60]
they are commonly used in phototransistors.[61]
The primary
benefit using TMDs as phototransistors is the tunable channel
conductance.[62]
Consequently, the photoresponse is also con-
trollable.[63]
The layer-dependent electronic structure in phos-
phorene was first shown in their transistor behaviors.[64]
Later,
it was observed directly by Li et al. as shown in Figure 3c.[65]
They declared that distinct advantages over other 2D materials
in electronic applications would be achieved by phosphorene
because of its layer-dependent electronic property and high
electrical mobility.[66]
Then, the phosphorene TFETs with uni-
form thicknesses were studied.[67]
The phosphorene lateral HJ
based on thickness modulation strategy was proposed by Liu
et al.[68] Shown in Figure 3d, the HJ was achieved by connecting
the double- and single-layer phosphorene segments together.
They also mentioned that the edge states could be eliminated
via edge dangling bond saturations. Although it is also hard to
be realized, the primary advantage of varying thickness to form
a HJ is to avoid the lattice mismatch problem at the interface.[69]
Besides, Aaditya et al. found that the electronic properties of
a bilayer phosphorene could be tuned by normal compressive
strains.[70] A semiconductor to metal transition phenomenon
was observed at ≈13.35% strain, which could be easily realized
in experiments. Later, we also found that this strain–electronic
relation could be enhanced by zigzag bilayer phosphorene
nanoribbons.[71] We thus infer that few layer phosphorene HJs
can also be achieved by partial strains.
3.2. Vertical van der Waals Heterojunctions
Another HJ type which has been widely investigated is the ver-
tical vdW HJ. It is formed by stacking the 2D materials layer-
by-layer via mechanical transfer.[72]
The 2D films can either be
exfoliated directly through bulk materials or grown by CVD.[73]
To date, the exfoliation is still the most successful method.
However, it is not believed to be a manufacturable process
considering the low yields.[74]
Even it is challenging to pre-
pare samples using CVD, the CVD technique is promising for
semiconductor industry.[75]
Direct CVD of 2D materials on 3D
semiconductors also has been reported recently.[76,77]
The inter-
layer connections in this type of vertical HJs are achieved by the
vdW force and the lattice mismatch issue can be well avoided.
Due to the absence of dangling bond, the interfaces are pristine
without electronic trap state. Also due to the weak interlayer
interactions, many 2D materials can be combined together,
generating diverse types of HJs with a wide range of band
Figure 3. Lateral HJ structure strategies based on low-dimensional materials. a) Synthesis of 7-13-7 GNR HJs using a bottom-up approach. Reproduced
with permission.[17]
Copyright 2015, Nature Publishing Group. b) MoSe2/WSe2 lateral HJ through a one-pot synthetic approach. Reproduced with per-
mission.[53]
Copyright 2018, Nature Publishing Group. c) Layer dependent band structures in phosphorene (up) and the phosphorene HJ via thickness
modulation (down). Reproduced with permission.[65,68]
Copyright 2017, Nature Publishing Group; Copyright 2016, The Royal Society of Chemistry,
respectively.

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alignments.[78,79] For example, only the phosphorene/TMD HJs
are enough to produce all the three types of band alignments.[80]
The interlayer carrier transports in vdW HJs are dominated
by tunneling, thus particularly suitable for TFET design. The
first vdW HJ made of graphene/boron nitride (hBN) or
MoS2/graphene sandwich structure had been demonstrated
by Britnell et al.[20] Their main purpose was to overcome the
absence of an energy gap in graphene. The Ion/Ioff ratio of
the corresponding FET reached 1 × 104. Later, the materials
had been rapidly extended to WS2,[81] GaN,[82] phosphorene,[83]
WSe2,[84] and SnSe2
[85]
(Figure 4a–c). The transparency,[81]
negative differential conductance (NDR),[86,87] spin-dependent
tunneling,[88] and some other photoelectric properties[89–92] of
the vdW HJs had also been investigated.
Not only the 2D–2D materials, the vdW HJs also can be
obtained by stacking 2D onto 3D materials. A vertical HJ had been
reported by Sarkar et al. using highly doped Ge and atomi-cally thin
MoS2.[93] This structure exhibited stable subthermionic tunneling
behavior, generating an extremely low SS value of 3.9 mV dec−1
and an average value of 31.1 mV dec−1
for four decades. Similarly,
the graphene/Si vdW HJ had also been reported by Liu et al.[94]
A current density of 0.2 µA µm−1
was demonstrated.
Similar with the discovery of 2D materials, early prepara-
tions of vdW HJs also relied on the layer-by-layer exfoliation
and restacking, a much easier method than the chemical syn-
theses of lateral HJs.[53,95–98]
However, Haigh et al. pointed out
that the restacking might bring adsorbates between layers,
detrimental for creating vdW HJs with atomically sharp
interfaces.[99]
Recently, a vdW superlattice had been synthe-
sized by Duan’s group using an electrochemical molecular
intercalation approach which could avoid interlayer adsorbates
(Figure 4d).[100]
The intercalation of selected 2D materials with
alkali metal ions offered an alternative way to HJ construction.
The above vdW HJs possess some common characteristics.
For example, to boost tunneling, the materials with high carrier
mobilities such as graphene and Ge tend to be chosen as the
injection layers and the semiconductors and insulators such as
hBN and MoS2 tend to be chosen as barrier layers. This strategy
is also suitable for metal/semiconductor contacts because of
the perfect vdW interfaces and highly modulated tunneling
behavior. Due to this, devices with both vdW contacts and chan-
nels had been proposed recently.[101–103] A good application
potential of the vertical vdW HJs can be foreseen.
4. Performance Demonstration
After the introduction of the cutting-edge HJ construction
methods, we will discuss the TFET performance based on these
HJs next. According to the HJ categories, the TFETs also can
be generally sorted as lateral and vertical ones. Besides, other
TFETs including the HETs and Dirac-source FETs are shown
separately. Although they also belong to either of the two TFET
types, their working mechanisms are different to some extent.
4.1. Lateral Tunnel Field-Effect Transistors
Lateral TFETs built on III–V compound HJs keep attracting
attentions in these years because of their improved on-state
behavior and compatible with current semiconductor fabrica-
tion. However, the interface issue caused by defects and lat-
tice mismatches is still the major trouble along the continuous
SS scaling. In 2016, Moselund and co-workers had fabricated
the in-plane InAs/Si TFETs and discussed their SS behaviors
in comparisons with other excellent works.[4,104] As shown in
Figure 5a, no SS could be smaller than 60 mV dec−1. They
concluded that to experimentally realize the TFETs which were
comparable to simulation results, one had to establish the
nature of the traps and then find appropriate solutions to deal
with them.
The lattice mismatch issue can be overcome by GNR HJ nat-
urally, since both sides of the junction are all GNRs. The first
milestone towards TFET design based on this structure was
carried out by Lam et al. through an NEGF quantum transport
simulator.[41] They used a GNR HJ structure with four different
segments in the channel. The on- and off-states were tuned
simultaneously by a small bandgap GNR segment in the source–
channel interface and a large bandgap GNR segment in the
middle of the channel. Later, we simplified the structure to two
GNR segments named the tunneling and blocking regions.[43]
Limited by technology, the GNR HJ TFET using width mod-
ulation had not been experimentally realized for a long time.
Until recently, it was fabricated by Hamam et al. through a
reactive ion etching (RIE) technique on single layer CVD grown
graphene (Figure 5b).[105]
The small and large bandgaps in the
source–channel interface and the channel promoted tunneling
and blocking independently. An SS of 47 mV dec−1
and a cur-
rent density of 8.51 µA µm−1
were observed. Since the width of
the GNR channel was not able to be reduced to an extremely
small value by the RIE technique, they also pointed out that the
Ion/Ioff ratio was low, due to the small bandgap of the 9.4 nm
wide GNR channel. We expect that this problem can be solved
by the bottom-up synthesis method later.[106]
Figure 4. Schematic illustration of the recently developed a–c) vertical
vdW HJs and d) superlattices. Reproduced with permission.[83,87,100,124]
b) Copyright 2016, American Chemical Society; a) Copyright 2016,
American Chemical Society; d) Copyright 2018, Nature Publishing Group;
and c) Copyright 2017, American Chemical Society, respectively.

1800569 (6 of 15)
The layer dependent electronic property and high car-
rier mobility in phosphorene make it suitable for thickness
engineered HJ TFETs (Figure 5c).[69] Similar with the width
modulation in GNRs, this TFET is achieved by increasing the
layers in the source–channel interface and reducing the layers
in the middle channel region. This HJ is unstrained and the
interface states generated by the dangling bonds can be elimi-
nated through appropriate saturation procedures.[68] As seen in
its transfer characteristics, the excellent on- and off-state behav-
iors of the multilayer and monolayer phosphorene TFETs are
all inherited by this HJ TFET.
Lateral TMDs HJ TFETs are expected to be fabricated in the near
future because the HJs had been reported in experiments.[52,53,97,98]
However, the TMDs should be carefully selected, since too large
bandgaps are not suitable for carrier tunneling. A recent study on
MoS2/WS2 HJ FET had shown that even under 80 V gate bias,
the Ion is only 0.1 µA,[54] suggesting lateral HJs made of these two
materials not suitable for TFET application.
4.2. Vertical Tunnel Field-Effect Transistors
TFETs built on vertically stacked vdW HJs have been inves-
tigated for many years because of their extremely low opera-
tion voltages (generally below 0.5 V) and tunneling lengths
(equal to the thickness of the channel material). This HJ con-
cept was primarily proposed to promote the graphene FETs’
off-state behavior, by inserting a large bandgap 2D material
between two graphene monolayers.[20]
The large bandgap layer
acts as a barrier and the carriers mainly transport between
the two graphene layers via tunneling. We call this sandwich
type HJ device the interlayer TFET (ITFET). The two outside
layers are of the same material, which is beneficial for NDR
behavior.[21,86,107]
To make high-quality electrical contact, Wang
et al. reported a contact geometry which could metalize only
the 1D edges of the 2D graphene layers to enhance the ITFETs’
low-temperature ballistic transport property.[108]
The fasci-
nating NDR behavior of the ITFET has caused many attentions.
Kang at al. pointed out that increasing the thicknesses of the
graphene layers was adverse to the NDR behavior.[22] To enhance
the current peak-to-valley ratios (PVRs), Burg et al. demon-
strated a bilayer graphene−bilayer WSe2−bilayer graphene
ITFET, exhibiting the PVRs of 4 and 6 at T = 300 and 1.5 K,
respectively.[12] Besides, they also verified that the interlayer
transports were mainly contributed by energy and momentum
conserving tunneling. The ITFETs are suitable for the future
nanoelectronics because of their high Ion/Ioff ratios. Recently,
Zhang et al. replaced the graphene layers with two single-
walled carbon nanotubes (SWCNTs) and fabricated an ITFET
made of SWCNT-MoS2-SWCNT (Figure 6a).[101] Because of
the extremely reduced HJ interface, the effects of sulfur vacan-
cies in mechanically exfoliated MoS2 were greatly restrained
and thus the device could be effectively turned off, generating
a high Ion/Ioff ratio exceeding 105. Furthermore, a CMOS cir-
cuit was demonstrated, showing a typical complementary
inverter characteristic with a gain of 2.6.
The A-B-A HJ ITFETs studied above can further be simplified
to the A-B TFETs in which carriers directly tunnel from A to B
through vdW barriers. The first A-B vertical vdW FET was dem-
onstrated by Yu et al. using a graphene/MoS2 HJ.[96]
However, its
transport mechanism was proved to be the thermionic emission
acrossing a Schottky barrier. The most notable characteristic for
thermionic emission is that the on- and off-state currents will be
reduced simultaneously by decreasing temperature.[109,110]
The
tunneling phenomenon had been observed in a WSe2-based ver-
tical graphene-TMD HJ transistor by Shim et al.[84]
They found
that trap-assisted tunneling could dominate the transport in this
device under some specific conditions and induced an anoma-
lously increasing Ion with decreasing temperature (Figure 6b).
An extraordinarily large Ion/Ioff ratio of 5 × 107
was achieved at
180 K. The W vacancy defects in the WSe2 contributed to the
trap states participating in transport. Similarly, trap-assisted tun-
neling phenomenon was also observed in the graphene/black
phosphorus (BP) vertical transistor with very strict conditions,
including low temperature and negative gate voltage.[83]
Even
worse, the tunneling could contribute to the off-state leakage
Figure 5. a) SS behaviors of the lateral HJ TFETs made of traditional materials. Reproduced with permission.[4] Copyright 2016, IEEE. b) Width engi-
neered GNR HJ TFET and its working mechanism. Reproduced with permission.[105] Copyright 2018, Elsevier. c) Thickness engineered phosphorene
HJ TFET and its transfer characteristics. From the red transfer curve, the HJ TFET behaves like the monolayer and the multilayer phosphorene TFETs
in off- and on-states simultaneously. Reproduced with permission.[69]
Copyright 2017, IEEE.

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currents. At on-state, carriers were mainly transported through
thermionic emission over the Schottky barrier.
From these analyses in A-B vertically stacked vdW HJ FETs,
the competition between thermionic emission and tunneling
often ends up with the former’s victory.[111] Therefore, they may
not suitable for two-valued logic transistor application. Never-
theless, they can be used in the multivalued logic via the NDR
behavior. The NDR device made of BP/ReS2 HJ was reported to
show high peak-to-valley current ratio values of 4.2 and 6.9 at
room and low temperatures.[112]
As mentioned above, the lateral HJs made of two large bandgap
vdW materials are not suitable for TFET application. Therefore,
to enhance tunneling, graphene layers can be included, since the
carrier effective mass and bandgap in graphene are incredibly
tiny. However, for the A-B vertical vdW devices, these graphene
layers easily lead to the thermionic emission transport. Shim et al.
had pointed out that if the barrier height between graphene and
another vdW material was less than 0.4 eV, the FET built on them
mainly operated under the thermionic emission mechanism.[78] To
restrain the thermionic emission, graphene should be avoided in
A-B vertical vdW TFETs. Note that the tunneling lengths have been
extremely scaled by the vdW HJs. Therefore, a vertical vdW TFET
made of two large bandgap materials is reasonable, since the tun-
neling probability reduction will be compensated by the tunneling
length. Seen in Figure 6c, a practical vertical n-type HJ TFET built
on SnSe2/WSe2 HJ had been demonstrated by Yan et al.[113]
The
type-II staggered HJ band structure was obtained. Under positive
gate voltages, this type-II HJ was changed to the type-III one and
high BTBT currents were observed. They reported a minimum SS
of 37 mV dec−1
and a Ion/Ioff ratio exceeding 106
in this work.
4.3. Other Transistors Based on Tunneling
Similar with TFETs, many other transistors also operate with
the assistance of tunneling. Here, we introduce two kinds of
recently developed transistors using HJ structures and tun-
neling mechanism: HETs and Dirac-source FETs. Besides
these tunneling devices, there are still large amount of
low-dimensional HJ based applications, such as the photo-
detector.[114–117] The low-dimensional HJs have inspired world-
wide investigations, showing their vast potential for future
electronics.
Since the emergence of graphene, its potential applica-
tions are being investigated during recent decades, most of
which devoting to overcoming its zero-bandgap drawback and
improving the off-state behavior. Among these, the graphene is
expected to promote the behaviors of HETs which allows expo-
nential control over tunneling currents.[118] HETs are regarded
as a promising candidate for high-speed electronic devices
because of their short base transit time. This advantage can be
further enlarged by graphene. At off-state (Figure 7a), carriers
of the emitter are blocked by the emitter–base and base–col-
lector insulators (EBI and BCI) jointly. At on-state, the effective
tunneling barrier of the EBI is reduced by increasing the base
voltage, enabling Fowler–Nordheim tunneling and ballistic
transport across the graphene. The graphene-base HET was
experimentally demonstrated by Vaziri et al.[119]
and an Ion/Ioff
ratio exceeding 104
was obtained. An important parameter
to evaluate the HETs’ performance is the common-base cur-
rent gain α, defined as IC/IE where IC and IE are the emitter
and collector currents, respectively. To improve it, Zeng et al.
had modified the device structures and the material para
meters, obtaining an effective gain of 44%.[120]
To enhance
sub-nanometer-scale control on the thickness and the lateral
uniformity, Kong et al. had further replaced the oxide layer
between the emitter and the graphene base to MoS2 in simula-
tion and declared that the device was capable of realizing THz
operation.[121]
The developments of HETs in recent years can be
described as a gradual material replacement from bulk to 2D
ones.[122–125]
However, whether they can afford the THz opera-
tion remains to be seen.
Figure 6. Schematic illustrations of recently developed vertical vdW TFETs. a) A CNT-MoS2-CNT ITFET, and b) a graphene-WSe2 TFET working on trap-
assisted tunneling process. Along decreasing temperature, its on- and off-state currents increase and decrease anomalously. c) A SnSe2-WSe2 TFET.
Direct tunneling is found under forward bias, whereas p-type MOSFET behavior is observed under reverse bias. Reproduced with permission.[84,101,113]
b) Copyright 2016, a) Copyright 2017 and c) Copyright 2017, Wiley-VCH, respectively.

1800569 (8 of 15)
Quite recently, Peng’s group proposed a novel Dirac-source
FET which can operate below the 60 mV dec−1 SS limit for
several decades at room temperature.[18] In a conventional
MOSFET with a normal source (Figure 7b), electrons of the
source follow the thermal Boltzmann distribution, leaving a
long thermal tail above the potential barrier of the channel.
This tail can contribute to the leakage currents and sets a
60 mV dec−1 limit on the SS. Now, it can be eliminated by the
Dirac source. Below the Dirac point, density of states (DOS)
decrease rapidly along the increasing energy, resulting in a
superexponentially decreasing trend of the electron density.
Since the much more localized electron distribution around
the Fermi level will definitely make the on–off switching more
fast, a smaller SS is achieved. It should be noted that in prin-
ciple, this Dirac-source FET do not purely work on tunneling
mechanism. However, we want to incorporate it into this
review because Peng’s group used tunneling to deal with the
contact and interface issues. Furthermore, their main point
towards this device is to break the SS limit and reduce supply
voltage, which is consistent with the TFETs’ features. Later, they
removed the tunneling process and added a bandgap in the
Dirac corner in simulation to complete the Dirac-source FET’s
theory.[19] We keep an optimal attitude on this device since it is
able to achieve small SS at room temperature.
5. Emerging Challenges
After an extraordinary years-long exploration, the fabrication of
low-dimensional lateral HJs is still not an easy task, hindering
the corresponding TFET application. Besides, the interface
states in these HJs begin to draw attentions recently. An impor-
tant figure of merit to replace the conventional bulk material
HJs with the ones made of low-dimensional materials is their
superior lattice mismatch suppression ability. However, that
does not guarantee that they can avoid interface state totally,
especially for the lateral HJs. Interface issue should be figured
out completely before TFET design. The graphene wide–narrow
ribbon HJs introduced above are regarded as free of lattice
mismatch, since the two sides of the HJs are composed by the
same material. However, interface states generating from the
zigzag interfaces had also been theoretically observed in our
recent studies (Figure 8a). In the corresponding TFET applica-
tion, these states can cause the Fermi level pining effect in the
tunneling region and add an additional barrier, degrading the
on-state behavior seriously.[43]
In the phosphorene lateral HJ TFETs based on thickness
modulation, the interface states caused by the edges of the
broken layers also had been observed in simulation.[68] How-
ever, it was suggested that these states could be removed by
dangling bond saturations. Considering these interface states
which have not been studied in TFET transport, more works
are needed to verify their impacts. More recently, Zhang et al.
had carried out an experiment on the interface states of a WSe2
bilayer–monolayer HJ (Figure 8b).[126] Interface states were
observed, inducing significant band bending in both sides of
the interface region, similar with the Fermi pining effect stated
above. The band bending from the valence band side was
much stronger, effectively reducing the bandgap starting about
3–4 nm away from the interface. Such a serious interface issue
will definitely affect the performance the TFET built on the HJ.
When two different materials are covalently connected
together laterally with an interface, we often hypothesis an ideal
band structure combination as shown in Figure 8c. In fact, the
electronic properties of the two sides will experience an inter-
acting procedure after their combination.[39]
In other words,
the electronic states of the two sides can penetrate mutually
through the connection, leaving a transition region in the band
structure. The electronic properties of the transition regions
are unpredictable. Their bandgaps can be larger or lower than
the two sides’. In many TFETs, the transition regions increase
the tunneling lengths at on-state, leading to Ion degradations.
More seriously, in some HJs,[126]
the transition regions are able
to be extended to several nanometers away from the interfaces.
If the length of a TFETs channel constructed by this kind of
HJs is only a few nanometers, the band structure of the whole
channel will become uniform, losing the HJs’ features.
Compared with the lateral HJ TFETs, one may not consider the
interface issue in the vertical vdW HJ TFETs because of the weak
vdW interactions. However, just because the weak connections, the
Figure 7. a) Band-diagrams of the HET at off- and on-states. Reproduced with permission.[119] Copyright 2013, American Chemical Society. b) State
and electron density distribution comparisons between a normal source and a Dirac source. The electron density in the Dirac source decreases more
rapidly along the increasing energy. Reproduced with permission.[18] Copyright 2018, American Association for the Advancement of Science.

1800569 (9 of 15)
relative positions of different layers can be varied easily, causing
unreliable device performance. Typical effects induced by the
interlayer displacements include lattice mismatch and misorienta-
tion. In view of momentum conservation for direct tunneling, lat-
tice mismatch will cause the k-point mismatch in the momentum
space of the whole HJ structure.[127] In most monolayer TMDs, the
valence band maximum (VBM) and conduction band minimum
(CBM) are located at the hexagonal Brillouin zone (BZ) corners
(K-points), meaning that the momenta of the VBM and CBM are
matched with each other initially.[128] When they are stacked layer-
by-layer to construct a vdW HJ, the k-point mismatch in the whole
structure is hard to be compensated. As a result, the tunneling
current is reduced at the beginning of conduction (Figure 8d).
Along the opening of the conduction window, the permitted tun-
neling k-range increases, eliminating the mismatch effect gradu-
ally. Therefore, we can conclude that the switching speeds of the
TFETs will be reduced by the lattice mismatch. Consequently, the
SS performance is degraded.
Another problem related to the vertical stacking of 2D mate-
rials is the misorientation. Its underlying mechanism is very
similar with the lattice mismatch. Therefore, Cao et al. also
observed tunneling degradation in their misorientation inves-
tigation.[129]
They pointed out that the device performance was
slightly affected by small momentum mismatches. Additionally,
the electron–phonon scattering was able to relieve this effect.
However, under large mismatches, the Ion reductions and the
SS degradations were all observed and unavoidable.
Finally, the electrical field screening effect of the overlap
regions in the vertical vdW TFETs is discussed. Imagine a
vertical vdW HJ with an overlap region in the middle and two
extended monolayer regions on the left and right, similar with
the structure in Figure 6c. The HJ is covered by a gate. When
the overlap region is always populated by excessive charges, it
will be immune to the gate voltage variation and only the Fermi
levels of the two extended monolayer regions are varied. Thus,
the tunneling is dominated by the monolayer regions, making
the junction region useless. Chen et al. had systematically
studied this phenomenon.[130] They held an optimized attitude
towards this kind of TFETs in low-power applications. However,
we still suggest that the excessive charges in the vdW junction
regions should be avoided.
In conclusion, the covalently bonded lateral HJ TFETs can
work stably. However, they suffer from interface and fabrication
problems. The vertical vdW HJ TFETs can be easily realized by
exfoliation methods. But they are not stable. Slight interlayer
displacements may cause significant tunneling degradations.
Until now, the low current density characteristic induced by
various problems still impedes the TFET applications. There-
fore, through simulations, we will introduce some improve-
ment strategies focused on the TFET on-state behavior.
6. Improvement Strategies
Along the emerging challenges towards low-dimensional HJ
TFETs, improvement strategies are also growing rapidly in
these years. First one is the electrostatic doping achieved by
multigate structure. Compared with MOSFETs, the doping
requirement is much stricter in TFETs. Steep doping pro-
files are needed in order to obtain short tunneling lengths
and high Ion. Unlike bulk materials, atom densities in low-
dimensional materials are extremely low. Only several foreign
atoms are enough to realize heavy doping. Thus, the number
of doping atoms should be carefully supervised. On the other
hand, the DOS in low-dimensional materials are also very low
compared to bulk materials, making the electrostatic doping a
feasible method. The graphene nanoribbon chemical doping
technology is relative mature now. However, the doping sites
inside the ribbon and the densities of impurities are still cannot
to be precisely controlled. Besides, additional defects such as
Figure 8. a) Interface states in graphene wide–narrow ribbon HJ and their impacts in TFET behaviors. Reproduced with permission.[43]
Copyright 2016,
IEEE. b) Interface regions in the band structure of the WSe2 bilayer–monolayer HJ. Reproduced with permission.[126]
Copyright 2016, Nature Publishing
Group. c) Ideal and realistic HJ band structure comparisons. The shapes of the transition regions are unpredictable. d) Current density variations along
gate voltage in the WSe2–SnSe2 lateral vdW TFET with or without considering the lattice constant mismatch and secondary band minima. Reproduced
with permission.[127]
Copyright 2017, IEEE.

1800569 (10 of 15)
the Stone–Wales defects are also easy to be induced during the
doping process.[131,132] In comparisons, the electrostatic doping
can overcome all these technology issues well.[133] Besides, the
p- and n-type doping switching, threshold variation immunity,
and bandgap dopant state elimination can also be achieved.[134]
In the multigate structure, the gate materials can also be
varied to induce work function engineering strategy. Adopting
gates with different work functions in different regions, built-
in potential profiles are thus generated prior to gate voltages.
Wang at al. had simulated an SWCNT TFET with this strategy
(Figure 9a).[135] The left gate segment was used to bend the band
structure at the source–channel interface. The middle one was
used to build blocking barrier. The right one was to restrain
leakage current caused by reverse tunneling. Without any gate
voltage, the tunneling junction and blocking barrier had been
constructed on the uniform SWCNT. The work function engi-
neering is especially suitable for enhancing band bending in the
tunneling region. As we mentioned above, the HJ interface states
will cause Fermi level pinning and hamper tunneling at on-state.
When the work function of the gate above the tunneling region
is reduced, an additional built-in potential is exerted on top of
this region, restraining the pinning effectively.[43] Besides, to
establish the built-in potential and enhance band bending, Raad
et al. alternatively buried a metallic layer in the oxide region
between gate and source electrode.[136]
The position deviation
in the buried layer did not affect the device performance sig-
nificantly. They also suggested that small work function in the
buried layer is suitable for superior device behaviors.
The TFET performance can be improved by the multi-
gate. Similarly, it can also be improved by multidielectrics.
Ilatikhameneh and co-workers had proposed the dielectric
engineered TFET (DE-TFET) concept in their works.[7,133,137]
The engineering is realized through a low-k dielectric sandwich
by two high-k ones (Figure 9b). When different voltages were
exerted on the two gates, the electric field in the low-k dielectric
would be higher (about 0.9 V nm−1
), according to the displace-
ment vector continuous equation εlowElow = εhighEhigh. Conse-
quently, the band structure below the low-k dielectric was more
significantly twisted, resulting in a shorter tunneling length at
on-state. Besides, the DE-TFETs offered advantages on oxide
thickness fluctuation compared to conventional TFETs.
Most low-dimensional transistors especially TFETs are believed
to suffer from contact issue. In an ideal metal–semiconductor
junction, the Schottky barrier is formed either for electrons or
holes. To reduce the contact resistance, the barrier height should
be effectively modulated. However, this modulation is commonly
hard to be realized because of severe chemical interactions that
are hard to avoid at the interfaces of the metals and the 2D mate-
rials.[138,139] These chemical interactions often cause a Fermi level
pinning effect, leading to unchanged Schottky barriers. Recently,
we reported a creation of vdW metal–semiconductor junction in
which the atomically flat Au thin film was laminated onto the
MoS2 without direct chemical bonding.[16] The Fermi level pin-
ning effect was thus avoided, making the Schottky barrier mod-
ulation follow the Schottky–Mott model again. To restrain the
Fermi level pinning, an alternative method of replacing device
contacts by vdW HJs had been proposed by Shin et al.[103] They
observed that graphene did rarely induce any Schottky barrier or
Fermi pinning on MoS2 due to the vdW interactions (Figure 9c).
Graphene was able to tune its own Fermi level according to the
MoS2’s without making any barrier. Similar graphene/WSe2 vdW
HJ had also been used as contact by Avsar et al.,[102]
resulting in
an average barrier height of only 80 meV. We believe that the
vdW contacts will be used widespread in the future.
7. Quantum Transport Modeling toward TFETs
Both the solving of emerging problems and the proposing
of improvement strategies need simulation and modeling as
theoretical guidance. Accuracy of the modeling will influence the
exploring directions to a great extent. Here, we will introduce the
quantum transport simulation theory based on the NEGF method.
As mentioned above, the carrier injection mechanism in
TFETs is BTBT, from the VBM of the source to the CBM of the
channel due to tunneling inside the forbidden gap. Therefore, it is
a quantum-mechanical behavior essentially.[140]
The strictest treat-
ment on BTBT is to solve the Schrodinger equation directly, such
Figure 9. Schematic illustrations of a) gate work function engineering, b) dielectric engineering, and c) vdW contact strategy to improve TFET performance.
Reproduced with permission.[103,135,137]
c) Copyright 2018, American Chemical Society; a) Copyright 2014, IEEE; and b) Copyright 2015, IEEE, respectively.

1800569 (11 of 15)
as the Schrodinger–Poisson solver. If a closed system is investi-
gated, the Hamiltonian will be compact because of the periodic
boundary conditions and thus the Schrodinger equation can
be solved easily. In fact, for TFETs and other transistors, they are
commonly connected with left and right contacts which may be
much larger in sizes compared with the channel regions, leading
to complex Hamiltonian (Figure 10a). The most fascinating prop-
erty of the NEGF approach is to reduce the complex Hamiltonian
to the size which is consistent with the channel, via the concept
of self-energy which is used in many-body physics to describe
electron–electron and electron–phonon interactions. The NEGF
approach is believed the most efficient and rigorous approach in
nanoscale electronic device transport simulations and it is par-
ticularly suitable for TFET modeling and simulations.[140]
The general form of the Green’s function is obtained from[141]
G E EI HC L R ph
1
[ ]
( ) = − − Σ − Σ − Σ
−
(1)
where the ΣL and ΣR are self-energy functions account for
the open boundary conditions and HC is the Hamiltonian of
the channel region in a device. In addition, electron–phonon
interactions can be incorporated through the Σph. Here, it is
neglected.[141]
Note that the E in Equation (1) can be varied by
the electrostatic potential in the channel. Once the Hamiltonian
and self-energies are constructed, the transport characteristics
are achieved through the solution of the Green’s function. The
transmission spectrum of the system can be written as
T E G G G G
trace trace
1 2 2 1
( ) ( )
( ) = Γ Γ = Γ Γ
+ +

(2)
where the Γ1 and Γ1 are broadening functions. Finally, the cur-
rent in the transmission formalism is obtained through
I q h ET E F F
/ d 1 2
∫
( ) ( )( )
= − − (3)
where F1 and F2 are the Fermi functions of the source and the
drain. The carrier density can be obtained via the density matrix
E
F E A F E A
d
2
0 1 1 0 2 2
∫
ρ
π
µ µ
[ ]
( ) ( )
= − + −

(4)
where A1 and A2 are left and right spectral functions.
On the other hand, the carrier density can be included into
the Poisson equation to renew the electrostatic potential through

ε r r q r
free fix
φ ρ ρ
( ) ( ) ( )
∇ ∇





= − +





 (5)
where

ε r
( ) is the dielectric constant,

r
( )
φ is the electrostatic
potential, and ρfix is the fixed charges which can be induced
by doping. Until now, the self-consistent iteration procedure is
constructed between the Schrodinger and Poisson equations
(Figure 10b).
The Hamiltonian used in the NEGF method is usually in a tight
binding (TB) form in order to reduce the computational burden. It
can be obtained either by a local atomic basis such as the sp3
d5
s*
TB model used in Si material,[142,143]
or by the effective-mass
approximation and the k·p methods.[144–146]
These methods have
been successfully utilized to predict the quantum transport behav-
iors of the devices based on traditional materials. However, for the
emerging low-dimensional materials such as the phosphorene and
tellurene,[66,147,148]
the required orbital parameters are missing.
Here, we introduce a Hamiltonian construction method
which can eliminate the parameter restriction. Due to the
Figure 10. a) Hamiltonian simplification under open boundary conditions using the NEFG method. b) Poisson–Schrodinger solver. c) Multiscale
simulation flow. d) Hamiltonian construction strategy for the MoS2-1T/MoS2-2H HJ. Reproduced with permission.[151]
Copyright 2017, American
Physical Society.

© 2018 WILEY-VCH Verlag GmbH Co. KGaA, Weinheim
1800569 (12 of 15)
extremely scaled sizes, the channel regions in TFETs can be
simulated directly from the first-principles density functional
theory (DFT). Then, the set of N Bloch wave functions
nk
ψ
describing the VBM and CBM are transformed to a set of N
Wannier functions through
w
V
U e k
nR
BZ
mn
k
mk
m
N ik R
|
2
| d
3 1

∑
π
ψ
( )
= ∫






( )
=
− ⋅

(6)
where U(k)
is a unitary matrix and

R is the Bravais lattice
vector. Next, we choose the U(k)
using some deliberate strat-
egies to minimize the spatial spreads of the Wannier func-
tions. Consequently, the Hamiltonian in TB form is obtained
from these Wannier bases naturally. This procedure is
called the maximally localized Wannier functions (MLWFs)
method. Now, a multiscale simulation flow from the ab
initio calculations to the quantum transport simulations has
been constructed by the DFT, MLWF, and NEGF methods
(Figure 10c).[141,149,150]
It should be noted that the first-principles calculations
require periodic units. As mentioned above, the TFET per-
formance can be improved significantly by HJs which are not
suitable for the first-principles calculations. This challenge had
been conquered recently by Marian et al. who built the Ham-
iltonian of the MoS2-1T/MoS2-2H interface.[151]
They declared
that attentions should be paid to the off-diagonal elements con-
necting the two different materials and used the off-diagonal
elements of the MoS2-2H’s in the interface (Figure 10d).
8. Conclusion
We have carried out a progress report on recently developed
TFETs based on low-dimensional HJs. Compared with conven-
tional MOSFETs, TFETs mainly work through the BTBT mech-
anism, resulting in large Ion/Ioff ratios within small supply
voltages. To boost the on- and off-state behaviors simultane-
ously, HJs should be adopted in the TFET design. In general, we
have introduced the state-of-art HJ strategies, including lateral
width and thickness engineering, in-plane covalent syntheses,
and vertical vdW stacking. Then, various novel TFETs based
on these HJs are studied from structures to working mecha-
nisms. Next, The emerging challenges and potential improve-
ment methods toward these novel TFETs are introduced. As
shown in Table 1, we want to conclude this report with a com-
prehensive performance comparison of these TFETs: i) from
simulations, the behaviors of the TFETs with HJs can meet
the requirements of future electronics, proving the feasibility
of TFET theoretically; ii) in both simulations and experiments,
behaviors in HJ TFETs are much better than the uniform ones,
indicating the correctness of doping HJs in TFETs; iii) after
years of explorations and developments, the performance of
Table 1. Performance comparisons of the recently simulated or fabricated TFETs
Main material Minimum SS [mV dec−1
] Ion [µA µm−1
or µA µm−2
] Ion/Ioff Voltage [V] Ref.
Simulation GNR lateral HJ 15 2000 2 × 107 0.4 [28]
15 600 1 × 109 0.6 [43]
Trilayer phosphorene 13 2 2 × 1011 0.9 [67]
Black phosphorus 25 200 1 × 1014 0.6 [152]
Trilayer/monolayer Phosphorene HJ – 1280 1 × 107 0.5 [69]
Ge/Si nanowire HJ 8 10 1 × 108 0.5 [153]
Monolayer WSe2 or WTe2 16 1000 1 × 107 0.8 [137]
Experiment WSe2/SnSe2 vdW HJ 100 3 × 10−2 1 × 107 1 [85]
MoS2/WSe2 vdW HJ 75 0.1 1 × 104 1 [87]
NbS2/n-MoS2 vdW HJ 60 1 5 × 104 2 [103]
Black phosphorus/MoS2 vdW HJ 51 1 × 10−3
1 × 104 1 [154]
55 1 2 × 106 3 [111]
Ge/MoS2 vdW HJ 4 1 1 × 1010 1 [93]
SnSe2/WSe2 vdW HJ 37 3 1 × 106 6 [113]
InAs/Si nanowire HJ 70 10 1 × 107 0.8 [4]
InAs/GaSb nanowire HJ 68 35 1 × 105 0.5 [155]
Monolayer MoS2 3100 4 × 10−5 1 × 102 10 [10]
L-shaped Si 34 1 × 10−3 1 × 105 2.5 [156]
GeSn 60 4 1 × 107 1 [157]
WSe2 260 0.2 1 × 106 1 [102]
GNR lateral HJ 47 8.5 3 × 103 3 [105]
Dirac-source HJ 40 40 1 × 106 0.5 [18]
InAs/InGaAsSb/GaSb Nanowire 43 10.4 1 × 104 0.3 [158]

1800569 (13 of 15)
experimentally realized TFETs has been comparable with the
simulation results in some single index evaluations. However,
no TFET exhibits a satisfactorily overall performance. Fatal
drawbacks almost exist in each of them; iv) among these per-
formance indexes, the Ion is the worst in experiments. No value
even exceeds 100 µA µm−1, suggesting that the tunneling issue
is still the most serious problem for TFETs. There is still a long
way to realize TFET application. However, we hold an opti-
mistic attitude towards this. At least, we have figured out one
investigation direction from this report: keep improving the
on-state behavior.
Acknowledgements
The authors acknowledge funding by the National Key Research and
Development Program of Ministry of Science and Technology (Grant
No. 2018YFB0406603), NSFC grant (Grant Nos. 61625401, 61574101,
61704051, 11604252, and U1632156), Hubei Province Natural Science
Foundation (Grant No. 2016CFA028), the Natural Science Foundation of
Hunan Province (Grant Nos. 2017RS3021 and 2017JJ3033), as well as the
Ten Thousand Talents Program for Young Talents.
Conflict of Interest
The authors declare no conflict of interest.
Keywords
field-effect transistors, heterojunctions, low-dimensional materials,
tunnel, van der Waals
Received: August 26, 2018
Revised: September 20, 2018
Published online:
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