Digital Design for B.Tech. / B.Sc.

04/15/17 Kishore Prabhala, Digital Design 1
Digital Design and EDA
Tools
Kishore Prabhala
Director,
VLSI Design Centre,
PSK Research Foundation
Opposite Acharya Nagarjuna University Mens
Hostel
Nagarjuna Nagar – 522 510
prabhalakishore@gmail.com

Digital Systems
 Integrated Circuits (ICs): Combinational
logic circuits, memory elements,
analog interfaces
 Printed Circuits (PC) boards: substrate for ICs
and interconnection, distribution of CLK, Vdd,
and GND signals, heat dissipation
 Power Supplies: Converts line AC voltage to regulated
DC low voltage levels
 Chassis (rack, card case, ...)
 1-25 conductive layers: holds boards, power supply,
fans, provides physical interface to user or other systems
 Connectors and Cables

Integrated Circuits
 Primarily Crystalline Silicon
 1mm - 25mm on a side
 200 - 400M effective transistors
 (50 - 75M “logic gates")
 3 - 10 conductive layers
 2007 feature size ~ 65nm = 0.065 x 10-
6
m
45nm coming on line
 “CMOS” most common -
complementary metal oxide
semiconductor
 Package provides:
 Spreading of chip-level signal paths
to board-level
 Heat dissipation.
 Ceramic or plastic with gold wires
Chip in Package

Printed Circuit Boards
 Fiberglass or
ceramic
 1-20in on a side
 IC packages are
soldered down

Integrated Circuits
Moore’s Law has fueled
innovation for the last 3 decades,
“Number of transistors on a die
doubles every 18 months”

Integrated Circuits
Uses for Digital IC technology today:
 Standard Microprocessors
 Used in desktop PCs, and embedded applications (ex: automotive)
 Simple system design (mostly software development)
 Memory chips (DRAM, SRAM)
 Application specific ICs (ASICs)
 custom designed to match particular application
 can be optimized for low-power, low-cost, high-performance
 high-design cost / relatively low manufacturing cost
 Field programmable logic devices (FPGAs, CPLDs)
 customized to particular application after fabrication
 short time to market, relatively high part cost
 Standardized low-density components
 still manufactured for compatibility with older system designs

Digital vs. Analog Waveforms
Analog:
values vary over a broad range
continuously
Digital:
only assumes discrete values
+5
V
–5
Time
+5
V
–5
1 0 1
Time

Logic Circuits
Truth
Table
Logic
Expression
Gate
Symbol
Logic
Function
Inverter AND OR EX-OR
A X X X X
A A A
BBB
X = A X = AB X = A + B X = A + B
A X
0 1
01
A X
0
0
1
1
0
0
01
1 1
0
0
B A X
0
1
1
1
0
0
01
1 1
0
1
B A X
0
1
0
1
0
0
01
1 1
0
1
B

MOS Transistor-level Logic Circuits
 MOSFET (Metal Oxide
Semiconductor Field Effect
Transistor), nMOS, pMOS and CMOS
The gate acts like a capacitor. A
high voltage on the gate
attracts charge into the
channel. If a voltage exists
between the source and drain
a current will flow. In its
simplest approximation, the
device acts like a switch. pMOS
nMOS

CMOS Logic Gates
Inverter (NOT
gate)
NAND
BAY •=
NOR
AY =
BAY +=

Logic and Layout: Inverter with VLSI
Stick Diagram
OutIn
VDD
M2
M1

Logic and Layout: NAND Gate with
VLSI Stick Diagram
B
VDD
A

Properties of Complementary CMOS
Gates
 High noise margins: Vih, Voh, Vdd,
Gnd
 No static power consumption
from Vdd to Ground in a steady
state
 Delay a function of load
capacitance and transistor
resistance
 Dynamic CMOS - relies on
temporary storage of signal
values on the capacitance of

CMOS Delay Model
CL
B
Rn
A
Rp
B
Rp
A
Rn
Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
NAND2
A
ReqA
A
Rp
A
Rp
A
Rn CL
INV NOR2

Input Pattern Effects on Delay
 Delay is dependent on
the pattern of inputs
 Low to high transition
 both inputs go low
 delay is 0.69 Rp/2 CL
 one input goes low
 delay is 0.69 Rp CL
 High to low transition
 both inputs go high
 delay is 0.69 2Rn CL
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
Rise and Fall times of output is a
key based on load

Delay Dependence on Input Patterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=1→0
A=1, B=1→0
A=1 →0, B=1
time [ps]
Voltage[V]
Input Data
Pattern
Delay
(psec)
A=B=0→1 67
A=1,
B=0→1
64
A= 0→1,
B=1
61
A=B=1→0 45
A=1,
B=1→0
80
A= 1→0,
B=1
81NMOS = 0.5µm/0.25 µm
PMOS = 0.75µm/0.25 µm
CL = 100 fF
Rise and Fall times of output is
a key based on load

Fan-In Considerations in CMOS
DCBA
D
C
B
A
C3
C2
C1
Distributed RC model
(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.

Complex CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C

Decoders
 A decoder is a combinational digital circuit
with a number of inputs ‘n’ and a number
of outputs ‘m’, where m= 2n
 Only one of the outputs is enabled at a
time. The output enabled is the one
specified by the binary number formed at
the inputs of the decoder.
 On the circuit below, the inputs of the
decoder are connected on three switches,
forming the number 5 [(101)2], thus only
LED #5 will be ON

Decoders digram
0
1
0
1
0
1 0 1 2 3 4 5 6 7
0 1 0 10 1
A 2
Y 2
A 0
Y 0
Y 1
Y 3
3/8DEC.
Y 6
Y 4
Y 5
Y 7
A 1

1-to-2 Decoder1-to-2 Decoder
 Truth table shown at right
 This one can be implemented
by just a simple fan-out and
an inverter:
x y0 y1
0 1 0
1 0 1
x
y1
y0
Circuit schematic
Icon
x
y1
y0

2 to 4 Decoder – Truth Table
 2 to 4 decoder
X1 X0 Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

2 to 4 Decoder Equations with Logic
0 1 0
1 1 0
2 1 0
3 1 0
Y X X
Y X X
Y X X
Y X X
=
=
=
=

3 to 8 Decoder – Truth Table
x2 x1 x0 y0 y1 y2 y3 y4 y5 y6 y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

3 to 8 Decoder Equations & Logic
0 2 1 0
1 2 1 0
2 2 1 0
3 2 1 0
Y X X X
Y X X X
Y X X X
Y X X X
=
=
=
=
4 2 1 0
5 2 1 0
6 2 1 0
7 2 1 0
Y X X X
Y X X X
Y X X X
Y X X X
=
=
=
=

Encoders
 Opposite of a decoder
 2n
to n encoder
 2n
inputs
 n outputs
 For each input, the circuit will
produce an “encoded” output

Example: 4 to 2 Binary Encoder
Truth Table
X3 X2 X1 X0 Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Assume only one input high at a time!!
0 1 3
1 2 3
Y X X
Y X X
= +
= +

Multiplexer(MUX)/Data Selector
 N to 1 multiplexer (or multiplexor)
 N=2k
data input lines, D0..(N−1)
 k=log2(N) control inputs, S(k−1)..0
 Binary encoding of index of selected data
 One output:
 This circuit will “connect” just the selected
input to the output.
 The selected input is specified by decoding the
control inputs.
( 1)..0kSF D −
=

The Simplest MultiplexerThe Simplest Multiplexer
 2-to-1 multiplexer truth table
 Output is a copy of
 D0 if S0=0
 D1 if S0=1
D0 D1 S0 F
D0 d 0 D0
d D1 1 D1
VCC
D[0..1] INPUT
2
2
2
and2_2b
inst1
2
or2_bus
inst2
FOUTPUT
VCC
S[0] INPUT
x y[0..1]
decoder_1-to-2
inst
D[0..1]
S[0]
F
mux_2-to-1
inst
example 2-to-1
MUX Icon
Schematic,
using 1-to-2
Decoder module

Example: 4 to 1 MUX Truth Table
D0 D1 D2 D3 S1 S0 F
D0 d d d 0 0 D0
d D1 d d 0 1 D1
d d D2 d 1 0 D2
d d d D3 1 1 D3
d = don’t care / Di = data on input i
Data Inputs
Control
Inputs
Output

4 to 1 MUX Equation
0 1 2 3F D AB D AB D AB D AB= + + +
2x4 Decoder Only a single AND gate will
be “ON” at a time.
Output
Control Inputs
Data Inputs

4-to-1 MUX from three4-to-1 MUX from three
2-to-1 MUXes2-to-1 MUXes
 Try building some larger sizes for yourself…
D[0..1]
S[0]
F
mux_2-to-1
inst
D[0..1]
S[0]
F
mux_2-to-1
inst1
D[0..1]
S[0]
F
mux_2-to-1
inst2
VCC
D[0..3] INPUT
VCC
S[1..0] INPUT
S[0]
FOUTPUT
F[0]
F[1]
S[1]
F[0..1]
D[2..3]
D[0..1]
D[0..3]

Logic with multiplexers
 You can implement any n-input logic
function with a single 2n
-to-1 multiplexer,
by feeding appropriate constants into the
MUX’s data inputs.
 Namely, the list of the function’s output values
from its truth table
 The multiplexer implements a “lookup
table”
 it simply looks up the function result from the
indicated row of the truth table
 Of course, this is generally not the most
hardware-efficient way to implement a
given function.

MUX Application Example
 Using a 4x1 MUX, design a logic
circuit which implements:
Y a b= ⊕
We have,
Y
0 1 2 3Y D AB D AB D AB D AB= + + +

Example
 Using a 4x1 MUX, design a logic
circuit which implements:
Y a b= ⊕
a b Y Dn
0 0 0 D0
0 1 1 D1
1 0 1 D2
1 1 0 D3
0 1 1 0Y AB AB AB AB AB AB= + + + = +

Solution

Multi-bit Multiplexers
 J-bit nx1 mux
sel
d0
d1
…
dn-1
d2 F
J bits
deep
log2n
J bits
deep
[ ] [ ]
0
j
i i
i
F j D j m
=
= ∑
j=0 to 3
This is just J separate nx1 multiplexers

Example: 1 to 4 DeMUX Truth Table
D A B F0 F1 F2 F3
D 0 0 D 0 0 0
D 0 1 0 D 0 0
D 1 0 0 0 D 0
D 1 1 0 0 0 D
d = don’t care / Di = data on input i

CMOS Transmission Gate
 Transmission gates are the
way to build “switches” in
CMOS
 In general, both transistor
types are needed:
 nFET to pass zeros
 pFET to pass ones
 The transmission gate is bi-
directional (unlike logic
gates)
A B
C
C
A B
C
C

Transmission Gate XOR
A
B
F
B
A
B
B
M1
M2
M3/M4

Pass-Transistor Based Multiplexer
A
M2
M1
B
S
S
S F
VDD

4-to-1 Multiplexer
 This version has
less delay from in
to out
 Care must be
taken to avoid
turning on multiple
paths
simultaneously
(shorting together
the inputs)
36 Transistors

4-to-1 Multiplexer
 The series
connection of
pass-
transistors in
each branch
effectively
forms the AND
of s1 and s0 (or
their
complement)
 20
transistors

CMOS Sequential Latch & Flip Flop
 Positive Level-sensitive
latch:
 Latch Transistor
Level:
clk’
clk
clk
clk’
Positive Edge-triggered
flip-flop built from two
level-sensitive latches:

Two Phase Non-Overlapping Clocking
Combinational
Logic
R
E
G
R
E
G
In Out
State
P1 P2
CLK
P1
P2
1/2 Register 1/2 Register

Verilog Structural description exampleVerilog Structural description example

module gates (o,i0,i1,i2,i3);
output o;
input i0,i1,i2,i3;
wire s1, s2;
and (s1, i0, i1);
and (s2, i2, i3);
and (o, s1, s2);
endmodule
i0
i1
i2
i3
Output
S1
S2
Verilog Structural description exampleVerilog Structural description example

Combinational circuit descriptionCombinational circuit description
modulemodule gates (d, a, c);gates (d, a, c);
outputoutput d;d;
inputinput a, c;a, c;
////wirewire b;b;
assignassign d = c ^ (~a);d = c ^ (~a);
//// assignassign b = ~a;b = ~a;
//// assignassign d = c ^ b;d = c ^ b;
endmoduleendmodule
a
b
c
d

Case Study of a Simple Logic Design:
Seven Segment Display
L1
L
6
L2
L3
L
7
L
4
L
5

Case Study
B3 B2 B1 B0 Val L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 1 1 0 1 1
L1
L
6
L2
L3
L
7
L
4
L
5

Case Study (cont.)
Some gate level implementation
of the Boolean function for L4

Basic Arithmetic Elements
Half Adder

Half Adder-Truth Table
 S=A+B (arithmetic sum)
A B S1 S0
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
0S a b= ⊕
1S ab=

Half Adder Circuit

Full Adder-Truth Table
 S=A+B+C
(arithmetic sum)
A B C S1 S0
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
0S a b c= ⊕ ⊕
1S ab ac bc= + +

Full Adder equations and Logic
0S a b c= ⊕ ⊕
Cout = ab + ac + bc or ab + (a⊕b

17
AND2 18
OR2
19 coutOUTPUT
16
AND2
VCC14 Cin INPUT
VCC13 B INPUT
10
XOR
11
XOR
15 sumOUTPUT
VCC12 A INPUT
Synthesis
Full Adder Circuit
S(0)
S(1)
C
A
B
S(0)
S(1)
Simulation

Full Adder from Two Half AddersFull Adder from Two Half Adders
 Given bits a,b,c, computes (s1s0)2 = a + b + c.
 Can build it using two half adders to compute the
low-order bit of the sum as s0 = (a⊕b)⊕c.
 Plus an extra OR gate needed to combine the carries.

Full Adder DesignFull Adder Design
VDD
VDD
VDD
VDD
A B
Ci
S
Co
X
B
A
Ci A
BBA
Ci
A B Ci
Ci
B
A
Ci
A
B
BA
Co = AB + Ci(A+B)
28 transistors

Full Adder Design with less transistorsFull Adder Design with less transistors
VDD
Ci
A
BBA
B
A
A B
Kill
Generate
"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
S
Co
24 transistors

Conceptualization
 4-bit adder (worst case)
1111
1111
11110
111
For the “worst case” we need to add
three bits to generate a single output bit
with a possible carry out.
Can we use our single bit adder for this?

Ripple Carry Adder
 We can cascade several full adders
to create a ripple carry adder
 The circuit gets its name because
the carry bit “ripples” from one bit
position to the next

Four Bit “Ripple” Adder
1-BitF.A.
C out S um
A B C in
1-BitF.A.
C out S um
A B C in
1-BitF.A.
C out S um
A B C in
1-BitF.A.
C out S um
A B C in
A 3 B 3 A 0 B 0A 2 B 2 A 1 B 1
0
S 3 S 2 S 1 S 0
C out

8-bit Ripple Carry Adder
 Use two 4-bit adders

16-bit Ripple Carry Adder
 Use two 8-bit adders

Subtraction Circuit
 Calculate 2’s complement of B
 Add –B to A
( ) 1S A B A B A B= − = + − = + +
B
1+
1S A B= + +

Add/Sub Circuit Module

Function Table for Add/Sub Module
Add Functional
Result
0 S=A+B
1 S=A-B
Add is a control input. It is active low. This means
that the module will compute A+B when Add=0. It
will compute A-B when Add=1.

Add/Sub Circuit
Design using Modules

Add/Sub Circuit

Add/Sub Circuit
Add operation. Add=0
0 0
S A B= +

Add/Sub Circuit
Sub operation. Add=1
1 1
1S A B= + +
B

Equal Comparator
 Design a logic circuit which will
compute
F0 = (A = B)

2-bit Equal Comparator Truth Table
b1 b0 a1 a0 F0
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0

2-bit Equal Comparator Truth Table
b1 b0 a1 a0 F0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

Solution
( )( )0 1 1 0 0F a b a b= ⊕ ⊕
You can show,

N-bit Equal Comparator
( ) ( )( )0 1 1 1 1 0 0n nF a b a b a b− −= ⊕ ⊕ ⊕K

Not Equal Comparator
compute
F = (A <> B)
F = (A = B)
i.e. Just invert our Equal Comparator circuit

Magnitude Comparator
compute
F2 = (A>B)
F1 = (A<B)
Let’s develop a truth table for 2-bits

2-bit Magnitude (unsigned) Comparator
Truth Table
b1 b0 a1 a0 F2 F1
0 0 0 0 0 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 0 0
0 1 1 0 1 0
0 1 1 1 1 0

Arithmetic Logic Units (ALUs)
The most commonly used circuits in
any microprocessor

Arithmetic Logic Unit (ALU)
A,B are data inputs of n bits each in depth
S is a control input. We have 2m
operations
F is the output

Example
 Let n=4,m=3
 We have A[3..0] and B[3..0]
 With m=3, we have 23
= 8 operations
 Let’s look at a possible function table

Function Table
s2 s1 s0 Function
0 0 0 F=AB
0 0 1 F=A+B (logical OR)
0 1 0 F=NOT A
0 1 1 F=A XOR B
1 0 0 F=A+B (Arithmetic)
1 0 1 F=A-B
1 1 0 F=A + 1
1 1 1 F=A - 1

Design using a Truth Table
 How large is the truth table?
 2n from data inputs A and B
 Example: n=8, we have 16 data inputs
 A[7..0] and B[7..0]
 3 control inputs
 Total of 2n+3 inputs
 N=8, we have 19 inputs
 Our truth table will have
 192
(361) rows and 8 outputs
 Too complex. Let’s explore another
alternative using a “system” or modular
approach

Design using Modules
 Note:
 For S2=0, we have logic operations
 For S2=1, we have arithmetic
operations
 So, let’s use S2 to control a 2x1 MUX
 to select between logic and arithmetic
operations, so our top level design
would look like:

ALU Design

ALU Design S2=0
With S2=0, F is the output from
the logic module

ALU Design S2=1
With S2=1, F is the output from
the arithmetic module

Logic Module Design

Function Table for Logic Module
 S2=0
s2 s1 s0 Function
0 0 0 F=AB
0 0 1 F=A+B (logical OR)
0 1 0 F=NOT A
0 1 1 F=A XOR B
We can use a 4x1 mux to
implement this module

Logic Module Design

Logic Module Design
AND Operation
S[1..0]=00
0 0
F=AB

Logic Module Design
OR Operation
S[1..0]=01
0 1
F=A+B

Logic Module Design
NOT Operation
S[1..0]=10
1 0
F=A

Logic Module Design
XOR Operation
S[1..0]=11
1 1
F=A XOR B

What do these logic modules
look like?

AND Module

OR Module

NOT Module
A F

XOR Module

Arithmetic Module
Let’s use our ADD/SUB Module

Add/Sub Circuit Module

Function Table for Arithmetic Ops
s2 s1 s0 Function
1 0 0 F=A+B (Arithmetic)
1 0 1 F=A-B
1 1 0 F=A + 1
1 1 1 F=A - 1
Note:
S0 can be use to indicate Addition or Subtraction.
S1 can be use to indicate the B data input

Arithmetic Module Design
B
A
S

B
A
S
0
0
F=A+B
S[1..0]=00

B
A
S
1
0
F=A-B
S[1..0]=01

B
A
S
0
1
F=A+1
S[1..0]=10

B
A
S
1
1
F=A-1
S[1..0]=11

Overall Design
We have

ALU Design

Logic Module Design

B
A
S

Total Design
Logic Module
Arithmetic Module

VLSI Design Centre
 Learn to design Digital Design with
Electronic Design Automation tools
 www.pskrf.com
 Thank YOU

Digital Design for B.Tech. / B.Sc.

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to Digital Design for B.Tech. / B.Sc.

Similar to Digital Design for B.Tech. / B.Sc. (20)

Recently uploaded

Recently uploaded (20)

Digital Design for B.Tech. / B.Sc.