Exploit FPGA-based Systems from Data Science High Level Languages

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NECST Lab @ Politecnico di Milano

NGC17 Talk @ Berkeley Lab - June 5, 2017

Engineering

1
A CAD FRAMEWORK FOR EXASCALE
PERFORMANCE FPGA-BASED SYSTEMS
luca.stornaiuolo@mail.polimi.it
06/05/2017
Alberto Scolari, Anna Maria Nestorov, Emanuele Del Sozzo, Enrico Reggiani,
Gianluca Durelli, Giuseppe Natale, Lorenzo Di Tucci, Luca Stornaiuolo,
Marco Rabozzi, Marco D. Santambrogio
NGCVIII
2017@SF

2
Heterogeneous Complex Systems
F1
Project Catapult

4
FPGAs
Fault
Tolerance
Power
Efficiency
Runtime
Adaptivity

5
Challenges
• Static design flow
• No designer-friendly multi-FPGA support
• To enable a co-design approach for developing
reconfigurable HPC architectures, tools and
applications
• To include reconfigurability as an explicit design
concept in future HPC systems
• And even more… ?

6
Problem definition
Hour Day Week Month
0.25
1
Year
4
16
64
256
Initial Design
Parallelisation
Clock Rate
Relative
Performance
Design-time
CPU
GPU
FPGA

8
CAOS
• Framework that uses reconfigurability of the
architecture for implementing applications
!
Usability Interactivity Modularity

9
CAOS
• Framework that uses reconfigurability of the
architecture for implementing applications
!
Usability Interactivity Modularity

10
CAOS
• Framework that uses reconfigurability of the
architecture for implementing applications
!
Usability Interactivity Modularity

11
CAOSWebUI
CAOSFlowManager
Backend
Functions
Optimization
Frontend
<system
>
…
</system
>
System
description
Profiling
datasets
______
__________
___
________
Application code
(C, C++, OPENCL)
______
__________
___
________
______
__________
___
________
1110010110
1010101111
1111010101
0101010101
0101010101
0111111
FPGAs
bitstreams
______
__________
___
________
System
runtime
ArchitecturalTemplates
Architectural Templates
( )
OpenCL
Streaming
…
( )
…
Computation Model Technology
SST

15
MaxCompiler
SST
Optimized functions Vendors tools
</>
</>
</>
</>
</>
</>
Output Generation

16
Data Science Case of Study
PCIe
IP-core

17
Data Science Case of Study
host.cpp
PCIe
IP-core

18
Data Science Case of Study
host.cpp
PCIe
IP-core
?
…

19
Data Science Case of Study
host.cpp
PCIe
IP-core mkfifo

20
Data Science Case of Study
host.cpp
PCIe
IP-core mkfifo
interface.cpp
Rcpp

21
Data Science Case of Study
host.cpp
PCIe
IP-core mkfifo
interface.cpp
MEX Files

22
Data Science Case of Study
host.cpp
PCIe
IP-core mkfifo
interface.cpp
Boost.Python

Questions
24
Thank you!
Luca Stornaiuolo
luca.stornaiuolo@mail.polimi.it
Politecnico di Milano

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1. 1 A CAD FRAMEWORK FOR EXASCALE PERFORMANCE FPGA-BASED SYSTEMS luca.stornaiuolo@mail.polimi.it 06/05/2017 Alberto Scolari, Anna Maria Nestorov, Emanuele Del Sozzo, Enrico Reggiani, Gianluca Durelli, Giuseppe Natale, Lorenzo Di Tucci, Luca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio NGCVIII 2017@SF

2. 2 Heterogeneous Complex Systems F1 Project Catapult

3. 3 FPGAs

4. 4 FPGAs Fault Tolerance Power Efficiency Runtime Adaptivity

5. 5 Challenges • Static design flow • No designer-friendly multi-FPGA support • To enable a co-design approach for developing reconfigurable HPC architectures, tools and applications • To include reconfigurability as an explicit design concept in future HPC systems • And even more… ?

6. 6 Problem definition Hour Day Week Month 0.25 1 Year 4 16 64 256 Initial Design Parallelisation Clock Rate Relative Performance Design-time CPU GPU FPGA

7. 7 Contributions

8. 8 CAOS • Framework that uses reconfigurability of the architecture for implementing applications ! Usability Interactivity Modularity

9. 9 CAOS • Framework that uses reconfigurability of the architecture for implementing applications ! Usability Interactivity Modularity

10. 10 CAOS • Framework that uses reconfigurability of the architecture for implementing applications ! Usability Interactivity Modularity

11. 11 CAOSWebUI CAOSFlowManager Backend Functions Optimization Frontend <system > … </system > System description Profiling datasets ______ __________ ___ ________ Application code (C, C++, OPENCL) ______ __________ ___ ________ ______ __________ ___ ________ 1110010110 1010101111 1111010101 0101010101 0101010101 0111111 FPGAs bitstreams ______ __________ ___ ________ System runtime ArchitecturalTemplates Architectural Templates ( ) OpenCL Streaming … ( ) … Computation Model Technology SST

12. 12 Frontend Modules

13. 13 Functions Optimizations Modules

14. 14 Backend Modules

15. 15 MaxCompiler SST Optimized functions Vendors tools </> </> </> </> </> </> Output Generation

16. 16 Data Science Case of Study PCIe IP-core

17. 17 Data Science Case of Study host.cpp PCIe IP-core

18. 18 Data Science Case of Study host.cpp PCIe IP-core ? …

19. 19 Data Science Case of Study host.cpp PCIe IP-core mkfifo

20. 20 Data Science Case of Study host.cpp PCIe IP-core mkfifo interface.cpp Rcpp

21. 21 Data Science Case of Study host.cpp PCIe IP-core mkfifo interface.cpp MEX Files

22. 22 Data Science Case of Study host.cpp PCIe IP-core mkfifo interface.cpp Boost.Python

23. 23 Conclusions

24. Questions 24 Thank you! Luca Stornaiuolo luca.stornaiuolo@mail.polimi.it Politecnico di Milano

Exploit FPGA-based Systems from Data Science High Level Languages

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