go through it you will fing interesting

1.  SANJAY . D .
DHNDARE
29/09/15 1ME(E&TC engg.),DYPSOE,Lohegaon,Pune

2. CONTENT :
 Introduction
 Brief history
 Need
 Boundary Scan Test
 Terminology used
 Working
 What is four wire test ?
29/09/15 2ME(E&TC engg.),DYPSOE,Lohegaon,Pune

3. Cont....
 BST cell and its VHDL code
 BST register
 TAP controller
 Signal specification
 Timing diagram
 Conclusion
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 3

4. INTRODUCTION
 What is scan test ?
 The method in which testing of boards , separate
components and ASIC is carried out in a efficient
way is called as scan test.
 It is also known as Boundary Scan Test (BST).
29/09/15 4ME(E&TC engg.),DYPSOE,Lohegaon,Pune

5. BRIEF HISTORY
 1985 : JETAG studied a board testing
 1986 : JETAG became JTEG
 1990 : ANSI provide 2.0 standard
 1994 : JTAG formed 2.0 standard with
1149.1 IEEE standard
 1994 : New standard for test port and BST
i.e.1149.1b
 From 1994 IEEE standard still referred as a
JTAG standard
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 5

6. NEED
 Existing technology i.e. Bed-of-nail had limited
specification .
 Difficult to test the IC with closer pin spacing.
 Testing speed is generally low .
 Only one component testing is carried out at
one time .
 Separation below 0.1mm or 100 mm with 200
or more pins is not possible in bed-of-nail
testing .
 Need standard System Test Port and Bus.
29/09/15 6ME(E&TC engg.),DYPSOE,Lohegaon,Pune

7. BOUNDARY SCAN TEST
29/09/15 7ME(E&TC engg.),DYPSOE,Lohegaon,Pune

8. WHAT IS FOUR WIRE TEST ?
 The method include four basic signal to test
the device.
 TDI : Test Data Input
 TDO :Test Data Output
 TCK :Test Clock
 TMS :Test Mode Select
 RST (OPTIONAL) : Reset signal
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 8

9. TERMINOLOGY USED
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 9

10. BST CELL AND ITS VHDL CODE
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 10

11. BST REGISTER
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 11

12. TAP CONTROLLER STATE DIAGRAM
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 12

13. TIMING DIAGRAM
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 13

14. POWER ON RESET FOR TAP
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 14

15. BST INSTRUCTION
 SAMPLE /PRELOAD : To get snapshot of
chip output signal i.e. put data on a chip to
be test .
 EXTEST : To test off-chip circuits
 INTEST : To test on-chip circuits
 CLAMP : Forces component output to be
driven by BSR
 INCODE :To get the ID of device to be
check
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 15

16. Cont...
 USER CODE :To get the ID of user
programmable device under test
 HIGH Z: To bring the output all components
at high impedance state
 It will avoid damage of components
 Need to reset the controller or board when
goes into high impedance state
29/09/15 ME(E&TC engg.),DYPSOE,Lohegaon,Pune 16

17. CONCLUSION
 From a given discussion we can conclude that it
is not possible to test printed circuit boards with
bed-of-nails tester to test multi-chip modules at all
without BST hence it is an important tool to test the
circuitry .
29/09/15 17ME(E&TC engg.),DYPSOE,Lohegaon,Pune

18. REFERENCES
 Digital system testing and testable design by
M.Abramovici .
 Agrawal.V. K. Multiple fault testing of large circuits
IEEE trans.vol c-30,no.11 pp 855 865.
 Introduction to testing and BIST by Breuer .M .A. And
A. D. Friedman.
29/09/15 18ME(E&TC engg.),DYPSOE,Lohegaon,Pune

19. .
Thank you ...
29/09/15 19ME(E&TC engg.),DYPSOE,Lohegaon,Pune