1. 12/04/06 E. E. Dept, IIT Bombay 1
Comprehensive Simulation of
Programming, Erase & Retention in
Charge Trapping Flash Memory
A. Paul, Ch. Sridhar, S. Gedam and S. Mahapatra
Department of Electrical Engineering
IIT Bombay, India

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Outline
Introduction
Physics of operation
Simulation details & assumptions
Results
Conclusion & outlook
Impact of parameters
Prediction of experimental data

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Introduction
Charge Trap Flash to replace
FG for NAND applications
Charge storage in traps in
nitride
A simulator to understand
Physics of operation
Impact of physical parameters
Impact of trap parameters
Substrate
Tunnel oxide
Nitride
Blocking oxide
Gate

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Simulator Features
Self consistent, 1D simulator
Provides electric field, tunneling current, trapped and
free carriers in the stack with time
Study impact of physical and trap parameters
Stack design: Impact of trap profiles on P, E and R
Simulation of Program, Erase and Retention
Extraction of experimental trap parameters

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Outline
Introduction
Physics of operation
Simulation details & assumptions
Results
Conclusion & outlook
Impact of parameters
Prediction of experimental data

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Program
Electron tunneling from Si
to N, and N to poly-Si
Hole tunneling from poly-Si
to N, and N to Si
Trapping / detrapping of
electrons & holes in nitride
Poly-Si
Top Ox
Nitride
Bottom Ox
Si-substrate
VG>0

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Erase
Detrapping & tunneling
of electrons from N to Si
VG<0
Poly-Si
Top Ox
Nitride
Bottom Ox
Si-
substrate
Tunneling of electrons
from poly-Si to N, trapping
Detrapping & tunneling of
holes from N to poly-Si
Tunneling of holes from
Si to N, trapping

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Retention
Thermal (FP) emission
followed by tunneling to
Si and poly-Si
Poly-Si
VG=0
Top Ox
Bottom Ox
Si-
substrate
Nitride
Trap to band tunneling
Trap to trap hopping
Not solved for holes due to
negligible hole tunneling
and trapping

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Outline
Introduction
Physics of operation
Simulation details & assumptions
Results
Conclusion & outlook
Impact of parameters
Prediction of experimental data

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System Equations
Poisson Tunneling
(FN or DT)
Continuity
& SRH
Substrate
Tunnel oxide
Nitride
Blocking oxide
Gate

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Simulation Flow
User Input Deck:
Structure, doping
Mesh
Trap profile
Bias, Time
Parameter file:
Physical & trap
Poisson-Schrödinger
Potential
Transport & Trapping
Tunneling (FN / DT)
Continuity & SRH
VT shift
Time
Final
result
NO
YES

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Assumptions
Bottom & top oxides are pure tunneling barriers with
no traps. Traps are only in nitride, fixed in time.
Elastic tunneling through barriers, calculated using
thermalized carrier concentration.
Single energy level, non-interacting electron & hole traps.
No traps at substrate and Poly-Si interfaces.
Effective mass in nitride is a fitting parameter.
Free carrier density < trapped carrier density in nitride.
Drift as the only transport mechanism in nitride.

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Outline
Introduction
Physics of operation
Simulation details & assumptions
Results
Conclusion & outlook
Impact of parameters
Prediction of experimental data

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Simulated Electric Field for P & E
Program: Increase in
negative trap charge in N
Erase: Decrease in
negative trap charge in N
Reduction in E (bottom)
Reduction in E (top)
Increase in E (bottom)
Increase in E (top)

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Impact of Effective Mass
Higher m*: lower JTUN
Higher m* (tunnel-oxide):
lower VT shift in P
Higher m* (top-oxide):
faster VT shift in E
(reduced back injection
through top-oxide)
e,ox
T
e,ox
T
e,ox
T

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Impact of Attempt to Escape Frequency
Higher :
Faster de-trapping
Lower VT shift in P
Higher VT shift in E

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Impact of Capture Cross-section
Higher : Faster trapping
Higher VT shift in P
Lower VT shift in E

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Impact of electron trap depth
Deeper traps: More
electron capture
Increase in trap depth
Increases ∆Vt during P
Increase in trap depth
Decreases ∆Vt during E

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Impact of Trap Profile – Program
Lower VT shift for lower trap density near tunnel oxide

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Impact of Trap Profile – Erase
Slower erase for lower trap density near tunnel oxide

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Prediction of Experimental P / E Results
SONOS: n+ poly-Si / 5.8nm SiO2 / 8nm Si3N4 / 5nm SiO2 / p-Si

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Prediction of Experimental P / E Results
SONOS: n+ poly-Si / 5.8nm SiO2 / 6nm Si3N4 / 5nm SiO2 / p-Si
During Erase devices
were pre-programmed
for 10s at Vg =11V.

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Prediction of Experimental R Results
SONOS: n+ poly-Si / 5.8nm SiO2 / 8nm Si3N4 / 5nm SiO2 / p-Si
Experimental data
is for pre-cycling
retention.

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Extracted Trap Distribution
All other parameters
are identical for these
devices
Higher trap density
near interfaces than
center
Larger trap density
at top interface

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Prediction of TANOS Result – Program
OT/N/OB = 15nm / 6.5nm / 4nm
Shin, IEDM 05
simulated
20us
~4V
~4
V
20us

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Prediction of TANOS Result – Erase
OT/N/OB = 15nm / 6.5nm / 4nm
Shin, IEDM 05
simulated
~4V
2 ms
~4V
2 ms

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Extracted Trap Distribution – TANOS
Higher trap density
near interface than
center
Larger density at top
interface
Similar trap profile for
SONOS and TANOS

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Outline
Introduction
Physics of operation
Simulation details & assumptions
Results
Conclusion & outlook
Impact of parameters
Prediction of experimental data

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Conclusion & Outlook
Self consistent, 1D simulator for P, E and R
Solves Poisson, Tunneling, Continuity & SRH
Good prediction of experimental results (SONOS &
TANOS) over wide experimental conditions
Provides physical and trap parameters, trap profiles
Useful tool to understand device physics, stack design,
parameter extraction
Acknowledgement:
IIT Bombay: J. Vasi, D. K. Sharma, N. Jain
Renesas Technologies (Japan): E. Murakami, K. Kubota, S. Kamohara