Low power ldpc decoder implementation using layer decoding

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Low power ldpc decoder implementation using layer decoding

  1. 1. LOW-POWER LDPC DECODERIMPLEMENTATION USINGLAYER DECODINGAJITH.C212111419001 Guide BYM.E VLSI Design Mr.P Kabilamani,Lecturer,ECE
  2. 2. Abstract Method for creating LDPC codes which arespecifically designed to be hardware friendly. Layer decoding is the one of the efficientapproach to decode the LDPC code with gooderror rate performance. Proposed approach will efficiently decrease thepower.
  3. 3. INTRODUCTION LDPC Code is a Linear Error Correcting Code. LDPC codes are finding increasing use◦ 1. reliable and highly efficient information transferover bandwidth◦ 2. return channel–constrained links in the presence ofdata-corrupting noise. Error correcting code in the new DVB-S2
  4. 4. Cont… Representations for LDPC CodesMatrix and Graphical Representations
  5. 5. Existing Method Layered Decoding
  6. 6. Cont… Most Practical LDPC Codes are structuredto support layered decoders in hardware. This concept is usually generalized bydividing the H-Matrix into Layers. Only one CN can access a given VNmemory at a specific time. In a layered decoder,one CN processorcan be designed to serially process thedifferent rows of the H-Matrix.
  7. 7. Proposed Method Vectored Layer Decoding
  8. 8. Cont… Vector Decoder Architectureovercomes the limitation of the layereddecoder by packing multiplemessages in the same memory unit. Throughput of a vector decoder canbe times that of a scalar decoder.
  9. 9. Phase I LDPC Encoding
  10. 10. Phase II LDPC Decoding using LayerDecoding. Vectored Layer Decoding.
  11. 11. LDPC Encoding Generator Matrix from Parity CheckMatrix. Encoding Technique.
  12. 12. Generator Matrix from ParityCheck Matrix Parity Check Matrix(H)H(qxn)=[Pqxk : Iq ]. Generator Matrix(G)G(kxn) =[Ik:Pkxq].
  13. 13. Encoding Technique Encoding by Matrix Multiplication Systematic codeword Generationcodeword,X=axGTa=(a1,a2,……ak),k information bits tobe encoded.GT=Generator Matrix Transpose
  14. 14. Software Used Simulation : Xilinx ISE 9.1i
  15. 15. Simulation For H Matrix To GMatrix Generation
  16. 16. Cont..
  17. 17. Simulation For LDPCEncoding
  18. 18. References R. Gallager, “Low-density parity-check codes,”IEEE Trans. Inf. Theory, vol. IT-8, no. 1, pp. 21–28, Jan. 1962. Z. Li, L. Chen, L. Zeng, S. Lin, and W.Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans.Commun.,vol. 53, no. 11, p. 1973, Nov. 2005. E. Yeo, P. Pakzad, B. Nikolic, and V.Anantharam, “High throughput low-density parity-check decoder architectures,” in Proc. IEEE GlobalTelecommun. Conf., 2001, vol. 5, pp. 3019–3024.
  19. 19. THANK YOU

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