The document discusses memory cells, registers, and system timings. It compares dynamic and static memory cells and describes how an array of memory cells can store 4-bit data using registers. A two-phase non-overlapping clock is assumed to write data to registers on the rising edge of the first clock phase and read data on the rising edge of the first clock phase in the next cycle. Common memory elements like dynamic shift registers are assessed based on their area requirements, power dissipation, and volatility.

1. Memory Cells, Registers and
System Timings
• Objectives:
– Raises the subject od memory/storage elements &
techniques
– Possible dynamic & static memory cells and key
properties compared
– The concept of an array of memory cells
– Arrangements of registers for 4 bit data storage
– Selection of memory cell in an array
– Configuration of such cells

2. System Timings Considerations
• A two phase non-overlapping clock signal is
assumed to be available. And this clock alone will
be used throughout the system.
• Clock phases are to be identified as ɸ1 and ɸ2 where
ɸ1 is assumed to lead ɸ2.
• Bits are to be stored are Written to register, storage
element, and subsystems on ɸ1 of the clock; i.e.,
write signal is WR are Anded with ɸ1.

3. • ɸ2 signals may be used to refresh the stored data.
• In general, delays through the data paths, are
assumed to be less than the intervals between the
leading edges of clock signals ɸ1 and ɸ2.
• Data may be read from the storage elements on the
next ɸ1 of the clock; i.e., RD are Anded with ɸ1.
• A general requirement for system stability is that
there must be at least one clocked storage element in
series with every closed loop signal path.

4. Some Commonly used Memory Elements
• Assessment of possible storage elements is done
based on the following factors.
– Area Requirement
– Estimated dissipation per bit stored
– Volatility

5. The Dynamic Shift Register Stage
• One method of storing a single bit is to use the
shift register approach

6. • Area: (nMOS)
Allowing for the sharing of VDD and VSS rails
between adjacent rows of register cell.
Each bit stored will require
(22λx28λ) x 2 = 1200λ^2
For λ = 2.5μm
Area / bit = 7500μm^2
This implies maximum number of bits stored
on a 4mm x 4mm chip area = 2.1 kbits.

7. • For CMOS
Each bit stored will require
(38λ x 28λ) x 2 =2100 λ^2
For λ = 2.5μm
Area / bit = 13000μm^2
This implies maximum number of bits stored
on a 4mm x 4mm chip area = 1.2 kbits.

8. • Dissipation:
– In CMOS design, the static dissipation is very
small, only the switching dissipation will be
significant.
The dynamic power consumption Pd can be written as
Pd = m x (CL x VDD^2 x f)
m is duty cycle
CL is effective load capacitance
F is the clock freq.

9. For an 8:1 nMOS inverter (noting that inerter pair is
always on )
Zpu = 4Rs
And
Zpd = ½ Rs
Therefore
Current = VDD/(Zpu + Zpd) = 110 μA
Thus 2.1 kbits on a single chip would dissipate
2.1k x 550 μW = 1.15 W

10. • Volatility:
– Data is stored by the charge on the gate
capacitance of each inverter stage, so that storage
time is limited to 1msec or less.