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Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
INTERNATIONAL JOURNAL OF ELECTRONICS AND 
17 – 19, July 2014, Mysore, Karnataka, India 
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) 
ISSN 0976 – 6464(Print) 
ISSN 0976 – 6472(Online) 
Volume 5, Issue 8, August (2014), pp. 97-106 
© IAEME: http://www.iaeme.com/IJECET.asp 
Journal Impact Factor (2014): 7.2836 (Calculated by GISI) 
www.jifactor.com 
IJECET 
© I A E M E 
DESIGN, IMPLEMENTATION AND COMPARISON OF VARIOUS CMOS 
CHARGE PUMPS 
Stuti Sharon1, Vani V2, Shobha B N3, Archana H R4 
1Student, Dept. of ECE, SCE, Bangalore, India 
2Assistant Professor, Dept. of ECE, SCE, Bangalore, India 
3PG Coordinator, Dept of ECE, SCE, Bangalore, India 
4Assitant Professor, Dept. of ECE, BMSCE, Bangalore, India 
97 
ABSTRACT 
A charge pump is a kind of DC to DC converter that uses capacitors as energy storage 
elements to create a higher or lower voltage power source. Charge pumps make use of switching 
devices for controlling the connection of voltage to the capacitor. The use of charge transfer switches 
(CTSs) can improve the voltage pumping gain. Applying dynamic control to the CTSs can reduce 
reverse currents. This paper includes voltage and power analysis of various charge pump circuits. 
And a comparison is drawn between the three charge pumps analyzed. 
Keywords: Charge Pump, Charge Transfer Switch, DC-DC Converter, Dickson Charge Pump, 
Dynamic Charge Pump, Static Charge Pump. 
I. INTRODUCTION 
Charge Pump (CP) is an electronic circuit that converts the supply voltage Vin to a DC output 
voltage VOUT that is several times higher than Vin (i.e., it is a DC-DC converter whose input voltage 
is lower than the output one). Unlike the other traditional DC-DC converters, which employ 
inductors, CPs are only made of capacitors and switches (or diodes), thereby allowing integration on 
silicon [1]–[2]. CPs were originally used in smart power ICs[3]–[6] and nonvolatile memories [7]– 
[13] and, given the continuous scaling down of ICs power supplies, they have also been employed in 
a vast variety of integrated systems such as switched capacitor circuits, operational amplifiers, 
voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, RF antenna switch controllers, etc. 
[14]–[23]. Charge pumps usually operate at high frequency level in order to increase their output 
power within a optimum size of total capacitance used for charge transfer. This operating frequency 
is adjusted by compensating for changes in the power requirements and saving the energy delivered 
to the charge pump.
Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
17 – 19, July 2014, Mysore, Karnataka, India 
Here in this paper we analyze and compare three kinds of charge pumps Dickson Charge 
Pump, Charge Pump using Static CTSs and Charge Pump using Dynamic CTSs. This paper 
describes new charge pumps that are suitable for low-voltage operation and offer better voltage 
pumping gains and higher output voltages than the Dickson charge pump. The various types of 
Charge pumps implemented and their performances are provided in sections II to VI. The charge 
pump utilizing the CTSs is described in Section V. A 4 stage prototype implemented in standard, 
180nm CMOS technology is demonstrated. The circuit can operate with a 1.5V supply and generate 
a boosted output of 4.2 V. In Section VI new charge pumps employing the dynamic CTSs to increase 
the voltage Pumping gain are described. The performance improvement is verified by simulation 
results. 
II. COCKCROFT WALTON CHARGE PUMP 
The first widely used voltage boosting circuit was the Cockcroft-Walton voltage multiplier. 
This circuit, shown in fig. 1, uses diodes and serially connected capacitors and can boost to several 
times the supply voltage. The Cockcroft-Walton charge pump provides efficient multiplication only 
if the coupling capacitors are much larger than the stray capacitance in the circuit, making it 
undesirable for use in integrated circuits. 
Fig.1: 4-Stage Cockcroft-Walton Charge Pump 
98 
III. DICKSON CHARGE PUMP 
Most MOS charge pumps are based on the circuit proposed by Dickson [5]–[7]. As shown in 
Fig. 2, the MOST’s in the Dickson charge pump function as diodes, so that the charges can be 
pushed only in one direction. The two pumping clocks clk1 and clk2 are out-of-phase and have a 
voltage amplitude of Vclk. The value of Vclk is usually identical to the supply voltage Vin. Through 
the coupling capacitors C1–C4, the two clocks push the charge voltage upward through the 
transistors. Neglecting the boundary conditions, the voltage fluctuation V at each pumping node is 
identical and can be expressed as: 
V = Vclk .{[C/(C+ Cs)] – {I o /[f(C+Cs)]}} (1) 
where C is the capacitance of C1–C4, Cs is the parasitic capacitance associated with each 
pumping node, f is the frequency of the pumping clocks, Io and is the output current loading. 
When clk1 goes from low to high and clk2 from high to low, the voltage at node 1 is settled 
to V1 + V , and the voltage at node 2 is settled to V2, where V1 and V2 are the steady-state lower 
voltage at node1 and node2 respectively. Both M1 and M3 are reverse biased, and the charges are 
being pushed from node 1 to node 2 through M2. The final voltage difference between node 1 and 2
Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
17 – 19, July 2014, Mysore, Karnataka, India 
is the threshold voltage of M2. The necessary condition for the charge pump to function is that V 
must be larger than the MOST’s threshold voltage Vtn , i.e.: 
V  Vtn (2) 
The voltage pumping gain for the second pumping stage Gv2 is defined as the voltage 
difference between and, which can be expressed as (3), 
Gv2 = V2 - V1 = V - Vtn (V2) (3) 
Where Vtn(V2) is the threshold voltage of M2, modified by the body effect due to the source 
voltage V2. The geometric dimension of the MOST’s has no effect on the voltage pumping gain. 
However, if the W/L ratio of the MOST diodes is too small so that the transient response of the 
pumping operation cannot settle within the period when the corresponding clock is high, then the 
resulting voltage pumping gain will be smaller than that predicted by (3). 
As the supply voltage decreases, both Vclk and V are decreased accordingly, and the voltage 
pumping gain per stage is reduced. Furthermore, if V is not much larger than the MOST’s threshold 
voltage, then the influence of the MOST’s body effect cannot be neglected. Especially at the high 
voltage nodes near the output, the increase in the threshold voltage can lower the voltage pumping 
gain significantly. In fact, the circuit’s output voltage reaches its maximum when the body effect 
causes the threshold voltage to be equal to V [6]. It is possible to use floating-well devices to 
eliminate the body effect [8]. However, the resulting charge pumps may generate substrate currents 
and the voltage pumping gain per stage is still reduced by the threshold voltage. 
Fig.2: 4-Stage Dickson Charge Pump 
Fig.3: 4-Stage Schematic of Dickson Charge Pump 
99
Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
17 – 19, July 2014, Mysore, Karnataka, India 
Fig.4. Output Waveform of 4-Stage Dickson Charge Pump 
The drawback of the Dickson charge pump circuit is that the boosting ratio is degraded by the 
threshold drops across the diodes. The body effect makes this problem even worse at higher voltages. 
IV. CHARGE PUMPS (NCP 1) USING STATIC CTSS 
Instead of using the diodes to direct the flow of charges in pumping operation, the MOST 
switches with proper on/off cycles, referred to as CTSs, have been used to realize the charge pumps 
and show better voltage pumping gain than the diodes [9]–[13]. Fig. 5 shows a new charge pump 
(NCP-1) using the MOST CTSs with static backward control [3]. MD1–MD4 are diodes for setting 
up the initial voltage at each pumping node. They are not involved in the pumping operation. MS1– 
MS4 are the CTSs. The idea is using the already established high voltage to control the CTS of the 
previous stage. If the switches can be turned on and turned off at the designated clock phases, they 
can also allow the charge to be pushed in only one direction. Then for each pumping stage, the upper 
voltage of the input is equal to the lower voltage of output, since the MOST switch is turned on at 
this moment. The voltage pumping gain per stage can be expressed as: 
Gv = Gv2 = V2 - V1 = V (4) 
Comparing with (3), the NCP-1 is expected to have better charge pumping performance. In 
Fig. 4, when clk1 is high and clk2 is low, the voltage at node 1 is pushed from V1 to V2 , the voltage 
at node 2 is V2, the voltage at node 3 is V3 + V. For nominal operation, the MS2 switch must be 
turned on by the voltage at node 3. The gate-to-source voltage of MS2 is 2V which must be larger 
than the threshold voltage Vtn modified by the source voltage V2, i.e: 
2V  Vtn (V2) (5) 
Comparing with (2), the NCP-1 is more suitable for low-voltage operation. 
On the other hand, when is clk1 low and clk2 is high, the voltage at node 1 is V1, the voltage 
at node 2 is V3, and the voltage at node 3 is also V3. For ideal operation, MS2 is to be turned off. 
Therefore, the gate-to-source voltage of MS2, which is 2V, must be smaller than the threshold 
voltage modified by the source voltage V1, i.e.: 
2V  Vtn (V1) (6) 
100
Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
17 – 19, July 2014, Mysore, Karnataka, India 
Fig.5: 4-Stage Static Charge Pump 
Fig.6: 4-Stage Schematic of Static Charge 
Fig.7: Output Waveform of 4-Stage Static Charge Pump 
Since (5) must always be true, the requirement of (6) can never be met. Therefore, MS2 
cannot be completely turned off, and reverse charge sharing between node 2 and node 1 can occur. In 
such cases, the operation of the charge pump becomes complicated. The voltage fluctuations at the 
pumping nodes are different and smaller than that predicted by (1). As a result, the overall voltage 
101
Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
17 – 19, July 2014, Mysore, Karnataka, India 
pumping gain is reduced. Note that the maximum voltage pumping gain between node 1 and node 3 
is determined only by the threshold voltage of MS2, i.e.: 
Max (Gv2 + Gv3) = Max(V3 - V1) = Vtn (V1) (7) 
A four-stage NCP-1 is fabricated using standard 180nm CMOS technology. The prototype 
is similar to the circuit shown in Fig. 5, except that MD5 and MDO are merged into one device, the 
pumping capacitor C5 is connected to the source node of MDO, and the output voltage is smoothed 
by an RC low-pass filter [3]. The threshold voltage of the nMOST’s is 0.7 V. The gate geometric 
size is 1.4μm by 1μm for all devices. All pumping capacitors are 20 pF. The circuit is used in a 1.5V 
switched-capacitor system for driving MOST analog switches. Fig. 7 shows the measured output 
voltage of the prototype while a 1.5V supply is applied. The prototype can maintain a 2.7V output 
voltage. For comparison, the output voltage of a five-stage Dickson charge pump operating under 
identical condition is 2.2 V. 
V. CHARGE PUMP (NCP 2) USING DYNAMIC CTSs 
If the reverse charge sharing phenomenon inherent in the NCP-1 circuit can be eliminated, 
better pumping performance can be obtained. In other charge pump designs [9]–[11], each CTS is 
accompanied by an auxiliary pass transistor so that the CTSs can be turned off completely in the 
designated period. However the CTSs in those charge pumps are difficult to turn on in the low 
voltage environment. Techniques such as putting CTSs in individual wells to eliminate the body 
effect and applying boosted clocks to drive the CTSs can be used [11]. The four-phase clock scheme 
can be used to pre-charge the CTSs so that they become easier to turn on [9], [11]. However, 
additional concern is that the auxiliary pass transistors must be turned on during the pre charging 
phase. 
Fig. 8 shows a new charge pump (NCP-2) that can assign the control inputs for the CTSs 
dynamically by adding pass transistor NMOS and PMOS to the NCP-1 circuit [14]. The CTSs in 
NCP-2 can be turned off completely when required and still can be turned on easily by the backward 
control as in the NCP-1 case. The expression for the single-stage voltage pumping gain is the same 
as (4). 
The operation of the dynamically controlled CTSs is explained as follows. When clk1 is high 
and clk2 is low, both the voltages at node 1 and node 2 are V2, and the voltage at node 3 is 2V 
above. If: 
2V  Vtp and 2V  Vtn(V2) (8) 
where Vtp is the threshold voltage of pMOST’s, then MP2 is turned on, causing MS2 being 
turned on by the voltage at node 3. In this period, MN2 is always off since its gate-to-source voltage 
is zero.On the other hand, when is clk1 low and clk2 is high, the voltage at node 1 is V1, both the 
voltages at node 2 and node3 are 2V above. If: 
2V  Vtn(V1) (9) 
then MN2 can be turned on and MS2 can be turned off completely. In this period, MP2 is 
also off, disengaging MS2 from the control of node 3. Unlike the NCP-1 case, the two necessary 
conditions of (8) and (9) can be satisfied simultaneously. Note that, for each pMOST in Fig.8, each 
individual well is connected to the device’s drain node. During the short period of transition when 
clk1 goes from high to low, it is possible for the charges at the CTSs gate node to be injected into the 
well. 
102
Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
17 – 19, July 2014, Mysore, Karnataka, India 
All coupling capacitors are 2pF. The frequency of the pumping clocks is 25MHz. The NCP-2 
exhibits the best charge pumping performance among the three circuits. For the NCP-1 charge pump, 
the effect of the reverse charge sharing become more apparent as the supply voltage increases. In 
case of 1.5V supply voltage the NCP-1 performs no better than the Dickson charge pump. Fig. 10 
shows the measured output voltage at 1.5Vsupply voltage is 4.1V. Under the same condition, the 
output voltage is 2.2 V for the Dickson charge pump and is 2.7 V for the NCP-1. 
Fig.8: 4-Stage Dynamic Charge Pump 
Fig.9: 4-Stage Schematic of Dynamic Charge Pump 
Fig.10: Output Waveform of 4-Stage Dynamic Charge Pump 
103
Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
17 – 19, July 2014, Mysore, Karnataka, India 
104 
VI. RESULT 
Table 1: Output voltage 
Dickson NCP-1 NCP-2 
Vout 2.2V 2.7V 4.2V 
Pd 17.66pW 34.32pW 38.79pW 
Parameters: 
1. Vin = 1.5V 
2. Pumping Capacitors- 2pf 
3. Technology used-180nm 
4. Width of NMOS-1.4micron 
5. Clock Frequency-25MHz 
Fig11: Simulated output voltages of various charge pumps. Vin= 1.5V 
VII. CONCLUSION 
The NCP-2 exhibits the best charge pumping performance among the three circuits. For the 
NCP-1 charge pump, the effect of the reverse charge sharing become more apparent as the supply 
voltage increases. In case of 1.5V supply voltage the NCP-1 performs no better than the Dickson 
charge pump. 
Charge pumps utilizing CTSs to direct charge flow can provide better voltage pumping gain 
than those using MOST diodes. Using the internal boosted voltage to backward control the CTS of 
the previous stage yields charge pumps that are suitable for low-voltage operation. The resulting 
charge pumps (NCP-1) can operate under a supply voltage below 1.2 V and still offer good pumping 
performance. 
The reverse charge sharing phenomenon inherent in the NCP-1 circuits can be eliminated by 
applying dynamic control to the CTSs. The NCP-2 charge pumps use two additional MOST’s per 
stage to implement the dynamic CTSs. The performance improvement of the NCP-2 over the NCP-1 
is more significant at higher supply voltages.
Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
17 – 19, July 2014, Mysore, Karnataka, India 
105 
VIII. REFERENCES 
[1] J F Dickson, “On-chip high-voltage generation in MNOS integrated circuits using an 
improved voltage multiplier technique,” IEEE J. Solid- State Circuits, vol. 11, pp. 374–378, 
June 1976. 
[2] Jieh-Tsorng Wu,” MOS charge pump for low voltage operation”, IEEE J. Solid State 
Circuits, vol 33, NO.4, April 1988. 
[3] T. Tanzawa, T. Tanaka, K. Takeuchi, and H. Nakamura, “Circuit technologies for a single- 
1.8 V flash memory,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1997, pp. 63–64. 
[4] T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. 
Sato, J. Yugami, H. Kume, and K. Kimura, “Bit-line clamped sensing multiplex and 
accurate high voltage generator for quarter-micron flash memories,”IEEE J. Solid-State 
Circuits, vol. 31, pp. 1590–1600, Nov. 1996. 
[5] J.T. Wu, Y.-H. Chang, and K.-L. Chang, “1.2 V CMOS switched-capacitor circuits,” in 
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1996, pp. 388–389. 
[6] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,”IEEE J. 
Solid-State Circuits, vol. 30, pp. 166–172, Mar. 1995. 
[7] J.S. Witters, G. Groeseneken, and H. E. Maes, “Analysis and modeling of on-chip high-voltage 
generator circuit for use in EEPROM circuits,” IEEE J. Solid-State Circuits, vol. 24, 
pp. 1372 1380, Oct. 1989. 
[8] T. Tanzawa and T. Tanaka, “A dynamic analysis of the Dickson charge pump circuit,”IEEE 
J. Solid-State Circuits, vol. 32, pp. 1231–1240, Aug. 1997. 
[9] K.-H. Choi, J.-M. Park, J.-K. Kim, T.-S. Jung, and K.-D. Suh, “Floating-well charge pump 
circuits for sub-2.0 V single power supply Flash memories,” inSymp. VLSI Circuits Dig. 
Tech. Papers, June 1997, pp. 61–62. 
[10] A. Umezawa, S. Atsume, M. Kuriyama, H. Banba, K. Imamiya, K. Naruke, S. Yamada, E. 
Obi, M. Oshikiri, T. Suzuki, and S. Tanaka, “A 5-V-only operation 0.6-ım Flash EEPROM 
with row decoder scheme in triple-well structure,” IEEE J. Solid-State Circuits, vol. 27, 
pp. 1540–1546, Nov. 1992. 
[11] K. D. Tedrow, J. J. Javanifard, and C. Galindo, “Method and apparatus for a two phase 
bootstrap charge pump,” U.S. Patent 5 432 469, July 1995. 
[12] K. Sawada, Y. Sugawara, and S. Masui, “An on-chip high-voltage generator circuit for 
EEPROM’s with a power supply voltage below 2 V,” inSymp. VLSI Circuits Dig. Tech. 
Papers, June 1995, pp. 75–76. 
[13] E. Lingstaedt and P. Miller, “MOSFET multiplying circuit,” U.S. Patent 5 029 063, July 
1991. 
[14] J. Tsujimoto, “Charge pump circuit having a boosted output signal,” U.S. Patent 4 935 644, 
June 1990 
[15] Nan-Xiong Huang1, Miin-Shyue Shiau2, Zong-Han Hsieh, Hong-Chong Wu4, Don-Gey 
Liu,” Improving the Efficiency of Mixed-Structure Charge Pumps by the Multi-Phase 
Technique”,2010 IEEE 
[16] S. Singer, ”Inductance-less up dc-dc converter,” IEEE Journal of Solid-State Circuits, vol. 
SC-17, pp. 778-781, Aug. 1982. 
[17] J. Witters, G. Groeseneken, and H. Maes, “Analysis and modeling of on-chip high voltage 
generator circuits for use in EEPROM circuits,” IEEE J. Solid-State Circuits, vol. 24, no. 5, 
pp. 1372–1380, Oct. 1989. 
[18] S. Hobrecht, “An intelligent BiCMOS/DMOS quad 1-A high-side switch,” IEEE J. Solid 
State Circuits, vol. SC-25, no. 6, pp. 1395–1402, Dec. 1990. 
[19] R. Gariboldi and F. Pulvirenti, “A 70 mV intelligent high side switch with full diagnostics, ” 
IEEE J. Solid State Circuits, vol. 31, no. 7, pp. 915–923, July 1996
Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 
17 – 19, July 2014, Mysore, Karnataka, India 
[20] T. Iinbo, et al., “A 5-V-only 16-Mb flash memory with sector erase mode,” IEEE J. Solid 
State Circuits, vol. 27, no. 11, pp. 1547–1553, Nov. 1992 
[21] G. Palumbo, D. Pappalardo, and M. Gaibotti, “Charge pump with adaptive stages for non-volatile 
memories,” IEE Proc. Circuits, Devices System., vol. 153, no. 2, pp. 136–142, 
106 
Apr. 2006. 
[22] R. Castillo and L. Tomasini,“1.5-V high-performance SC filters in BiCMOS technology,” 
IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 930–936, July 1991. 
[23] Y. Tsiatouhas, “A stress-relaxed negative voltage-level converter,” IEEE Trans. Circuits 
System. II, vol. 54, no. 3, pp. 282–286, Mar. 2007.

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Design implementation and comparison of various cmos charge pumps

  • 1. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 INTERNATIONAL JOURNAL OF ELECTRONICS AND 17 – 19, July 2014, Mysore, Karnataka, India COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 – 6464(Print) ISSN 0976 – 6472(Online) Volume 5, Issue 8, August (2014), pp. 97-106 © IAEME: http://www.iaeme.com/IJECET.asp Journal Impact Factor (2014): 7.2836 (Calculated by GISI) www.jifactor.com IJECET © I A E M E DESIGN, IMPLEMENTATION AND COMPARISON OF VARIOUS CMOS CHARGE PUMPS Stuti Sharon1, Vani V2, Shobha B N3, Archana H R4 1Student, Dept. of ECE, SCE, Bangalore, India 2Assistant Professor, Dept. of ECE, SCE, Bangalore, India 3PG Coordinator, Dept of ECE, SCE, Bangalore, India 4Assitant Professor, Dept. of ECE, BMSCE, Bangalore, India 97 ABSTRACT A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. The use of charge transfer switches (CTSs) can improve the voltage pumping gain. Applying dynamic control to the CTSs can reduce reverse currents. This paper includes voltage and power analysis of various charge pump circuits. And a comparison is drawn between the three charge pumps analyzed. Keywords: Charge Pump, Charge Transfer Switch, DC-DC Converter, Dickson Charge Pump, Dynamic Charge Pump, Static Charge Pump. I. INTRODUCTION Charge Pump (CP) is an electronic circuit that converts the supply voltage Vin to a DC output voltage VOUT that is several times higher than Vin (i.e., it is a DC-DC converter whose input voltage is lower than the output one). Unlike the other traditional DC-DC converters, which employ inductors, CPs are only made of capacitors and switches (or diodes), thereby allowing integration on silicon [1]–[2]. CPs were originally used in smart power ICs[3]–[6] and nonvolatile memories [7]– [13] and, given the continuous scaling down of ICs power supplies, they have also been employed in a vast variety of integrated systems such as switched capacitor circuits, operational amplifiers, voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, RF antenna switch controllers, etc. [14]–[23]. Charge pumps usually operate at high frequency level in order to increase their output power within a optimum size of total capacitance used for charge transfer. This operating frequency is adjusted by compensating for changes in the power requirements and saving the energy delivered to the charge pump.
  • 2. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India Here in this paper we analyze and compare three kinds of charge pumps Dickson Charge Pump, Charge Pump using Static CTSs and Charge Pump using Dynamic CTSs. This paper describes new charge pumps that are suitable for low-voltage operation and offer better voltage pumping gains and higher output voltages than the Dickson charge pump. The various types of Charge pumps implemented and their performances are provided in sections II to VI. The charge pump utilizing the CTSs is described in Section V. A 4 stage prototype implemented in standard, 180nm CMOS technology is demonstrated. The circuit can operate with a 1.5V supply and generate a boosted output of 4.2 V. In Section VI new charge pumps employing the dynamic CTSs to increase the voltage Pumping gain are described. The performance improvement is verified by simulation results. II. COCKCROFT WALTON CHARGE PUMP The first widely used voltage boosting circuit was the Cockcroft-Walton voltage multiplier. This circuit, shown in fig. 1, uses diodes and serially connected capacitors and can boost to several times the supply voltage. The Cockcroft-Walton charge pump provides efficient multiplication only if the coupling capacitors are much larger than the stray capacitance in the circuit, making it undesirable for use in integrated circuits. Fig.1: 4-Stage Cockcroft-Walton Charge Pump 98 III. DICKSON CHARGE PUMP Most MOS charge pumps are based on the circuit proposed by Dickson [5]–[7]. As shown in Fig. 2, the MOST’s in the Dickson charge pump function as diodes, so that the charges can be pushed only in one direction. The two pumping clocks clk1 and clk2 are out-of-phase and have a voltage amplitude of Vclk. The value of Vclk is usually identical to the supply voltage Vin. Through the coupling capacitors C1–C4, the two clocks push the charge voltage upward through the transistors. Neglecting the boundary conditions, the voltage fluctuation V at each pumping node is identical and can be expressed as: V = Vclk .{[C/(C+ Cs)] – {I o /[f(C+Cs)]}} (1) where C is the capacitance of C1–C4, Cs is the parasitic capacitance associated with each pumping node, f is the frequency of the pumping clocks, Io and is the output current loading. When clk1 goes from low to high and clk2 from high to low, the voltage at node 1 is settled to V1 + V , and the voltage at node 2 is settled to V2, where V1 and V2 are the steady-state lower voltage at node1 and node2 respectively. Both M1 and M3 are reverse biased, and the charges are being pushed from node 1 to node 2 through M2. The final voltage difference between node 1 and 2
  • 3. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India is the threshold voltage of M2. The necessary condition for the charge pump to function is that V must be larger than the MOST’s threshold voltage Vtn , i.e.: V Vtn (2) The voltage pumping gain for the second pumping stage Gv2 is defined as the voltage difference between and, which can be expressed as (3), Gv2 = V2 - V1 = V - Vtn (V2) (3) Where Vtn(V2) is the threshold voltage of M2, modified by the body effect due to the source voltage V2. The geometric dimension of the MOST’s has no effect on the voltage pumping gain. However, if the W/L ratio of the MOST diodes is too small so that the transient response of the pumping operation cannot settle within the period when the corresponding clock is high, then the resulting voltage pumping gain will be smaller than that predicted by (3). As the supply voltage decreases, both Vclk and V are decreased accordingly, and the voltage pumping gain per stage is reduced. Furthermore, if V is not much larger than the MOST’s threshold voltage, then the influence of the MOST’s body effect cannot be neglected. Especially at the high voltage nodes near the output, the increase in the threshold voltage can lower the voltage pumping gain significantly. In fact, the circuit’s output voltage reaches its maximum when the body effect causes the threshold voltage to be equal to V [6]. It is possible to use floating-well devices to eliminate the body effect [8]. However, the resulting charge pumps may generate substrate currents and the voltage pumping gain per stage is still reduced by the threshold voltage. Fig.2: 4-Stage Dickson Charge Pump Fig.3: 4-Stage Schematic of Dickson Charge Pump 99
  • 4. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India Fig.4. Output Waveform of 4-Stage Dickson Charge Pump The drawback of the Dickson charge pump circuit is that the boosting ratio is degraded by the threshold drops across the diodes. The body effect makes this problem even worse at higher voltages. IV. CHARGE PUMPS (NCP 1) USING STATIC CTSS Instead of using the diodes to direct the flow of charges in pumping operation, the MOST switches with proper on/off cycles, referred to as CTSs, have been used to realize the charge pumps and show better voltage pumping gain than the diodes [9]–[13]. Fig. 5 shows a new charge pump (NCP-1) using the MOST CTSs with static backward control [3]. MD1–MD4 are diodes for setting up the initial voltage at each pumping node. They are not involved in the pumping operation. MS1– MS4 are the CTSs. The idea is using the already established high voltage to control the CTS of the previous stage. If the switches can be turned on and turned off at the designated clock phases, they can also allow the charge to be pushed in only one direction. Then for each pumping stage, the upper voltage of the input is equal to the lower voltage of output, since the MOST switch is turned on at this moment. The voltage pumping gain per stage can be expressed as: Gv = Gv2 = V2 - V1 = V (4) Comparing with (3), the NCP-1 is expected to have better charge pumping performance. In Fig. 4, when clk1 is high and clk2 is low, the voltage at node 1 is pushed from V1 to V2 , the voltage at node 2 is V2, the voltage at node 3 is V3 + V. For nominal operation, the MS2 switch must be turned on by the voltage at node 3. The gate-to-source voltage of MS2 is 2V which must be larger than the threshold voltage Vtn modified by the source voltage V2, i.e: 2V Vtn (V2) (5) Comparing with (2), the NCP-1 is more suitable for low-voltage operation. On the other hand, when is clk1 low and clk2 is high, the voltage at node 1 is V1, the voltage at node 2 is V3, and the voltage at node 3 is also V3. For ideal operation, MS2 is to be turned off. Therefore, the gate-to-source voltage of MS2, which is 2V, must be smaller than the threshold voltage modified by the source voltage V1, i.e.: 2V Vtn (V1) (6) 100
  • 5. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India Fig.5: 4-Stage Static Charge Pump Fig.6: 4-Stage Schematic of Static Charge Fig.7: Output Waveform of 4-Stage Static Charge Pump Since (5) must always be true, the requirement of (6) can never be met. Therefore, MS2 cannot be completely turned off, and reverse charge sharing between node 2 and node 1 can occur. In such cases, the operation of the charge pump becomes complicated. The voltage fluctuations at the pumping nodes are different and smaller than that predicted by (1). As a result, the overall voltage 101
  • 6. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India pumping gain is reduced. Note that the maximum voltage pumping gain between node 1 and node 3 is determined only by the threshold voltage of MS2, i.e.: Max (Gv2 + Gv3) = Max(V3 - V1) = Vtn (V1) (7) A four-stage NCP-1 is fabricated using standard 180nm CMOS technology. The prototype is similar to the circuit shown in Fig. 5, except that MD5 and MDO are merged into one device, the pumping capacitor C5 is connected to the source node of MDO, and the output voltage is smoothed by an RC low-pass filter [3]. The threshold voltage of the nMOST’s is 0.7 V. The gate geometric size is 1.4μm by 1μm for all devices. All pumping capacitors are 20 pF. The circuit is used in a 1.5V switched-capacitor system for driving MOST analog switches. Fig. 7 shows the measured output voltage of the prototype while a 1.5V supply is applied. The prototype can maintain a 2.7V output voltage. For comparison, the output voltage of a five-stage Dickson charge pump operating under identical condition is 2.2 V. V. CHARGE PUMP (NCP 2) USING DYNAMIC CTSs If the reverse charge sharing phenomenon inherent in the NCP-1 circuit can be eliminated, better pumping performance can be obtained. In other charge pump designs [9]–[11], each CTS is accompanied by an auxiliary pass transistor so that the CTSs can be turned off completely in the designated period. However the CTSs in those charge pumps are difficult to turn on in the low voltage environment. Techniques such as putting CTSs in individual wells to eliminate the body effect and applying boosted clocks to drive the CTSs can be used [11]. The four-phase clock scheme can be used to pre-charge the CTSs so that they become easier to turn on [9], [11]. However, additional concern is that the auxiliary pass transistors must be turned on during the pre charging phase. Fig. 8 shows a new charge pump (NCP-2) that can assign the control inputs for the CTSs dynamically by adding pass transistor NMOS and PMOS to the NCP-1 circuit [14]. The CTSs in NCP-2 can be turned off completely when required and still can be turned on easily by the backward control as in the NCP-1 case. The expression for the single-stage voltage pumping gain is the same as (4). The operation of the dynamically controlled CTSs is explained as follows. When clk1 is high and clk2 is low, both the voltages at node 1 and node 2 are V2, and the voltage at node 3 is 2V above. If: 2V Vtp and 2V Vtn(V2) (8) where Vtp is the threshold voltage of pMOST’s, then MP2 is turned on, causing MS2 being turned on by the voltage at node 3. In this period, MN2 is always off since its gate-to-source voltage is zero.On the other hand, when is clk1 low and clk2 is high, the voltage at node 1 is V1, both the voltages at node 2 and node3 are 2V above. If: 2V Vtn(V1) (9) then MN2 can be turned on and MS2 can be turned off completely. In this period, MP2 is also off, disengaging MS2 from the control of node 3. Unlike the NCP-1 case, the two necessary conditions of (8) and (9) can be satisfied simultaneously. Note that, for each pMOST in Fig.8, each individual well is connected to the device’s drain node. During the short period of transition when clk1 goes from high to low, it is possible for the charges at the CTSs gate node to be injected into the well. 102
  • 7. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India All coupling capacitors are 2pF. The frequency of the pumping clocks is 25MHz. The NCP-2 exhibits the best charge pumping performance among the three circuits. For the NCP-1 charge pump, the effect of the reverse charge sharing become more apparent as the supply voltage increases. In case of 1.5V supply voltage the NCP-1 performs no better than the Dickson charge pump. Fig. 10 shows the measured output voltage at 1.5Vsupply voltage is 4.1V. Under the same condition, the output voltage is 2.2 V for the Dickson charge pump and is 2.7 V for the NCP-1. Fig.8: 4-Stage Dynamic Charge Pump Fig.9: 4-Stage Schematic of Dynamic Charge Pump Fig.10: Output Waveform of 4-Stage Dynamic Charge Pump 103
  • 8. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India 104 VI. RESULT Table 1: Output voltage Dickson NCP-1 NCP-2 Vout 2.2V 2.7V 4.2V Pd 17.66pW 34.32pW 38.79pW Parameters: 1. Vin = 1.5V 2. Pumping Capacitors- 2pf 3. Technology used-180nm 4. Width of NMOS-1.4micron 5. Clock Frequency-25MHz Fig11: Simulated output voltages of various charge pumps. Vin= 1.5V VII. CONCLUSION The NCP-2 exhibits the best charge pumping performance among the three circuits. For the NCP-1 charge pump, the effect of the reverse charge sharing become more apparent as the supply voltage increases. In case of 1.5V supply voltage the NCP-1 performs no better than the Dickson charge pump. Charge pumps utilizing CTSs to direct charge flow can provide better voltage pumping gain than those using MOST diodes. Using the internal boosted voltage to backward control the CTS of the previous stage yields charge pumps that are suitable for low-voltage operation. The resulting charge pumps (NCP-1) can operate under a supply voltage below 1.2 V and still offer good pumping performance. The reverse charge sharing phenomenon inherent in the NCP-1 circuits can be eliminated by applying dynamic control to the CTSs. The NCP-2 charge pumps use two additional MOST’s per stage to implement the dynamic CTSs. The performance improvement of the NCP-2 over the NCP-1 is more significant at higher supply voltages.
  • 9. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India 105 VIII. REFERENCES [1] J F Dickson, “On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid- State Circuits, vol. 11, pp. 374–378, June 1976. [2] Jieh-Tsorng Wu,” MOS charge pump for low voltage operation”, IEEE J. Solid State Circuits, vol 33, NO.4, April 1988. [3] T. Tanzawa, T. Tanaka, K. Takeuchi, and H. Nakamura, “Circuit technologies for a single- 1.8 V flash memory,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1997, pp. 63–64. [4] T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, and K. Kimura, “Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories,”IEEE J. Solid-State Circuits, vol. 31, pp. 1590–1600, Nov. 1996. [5] J.T. Wu, Y.-H. Chang, and K.-L. Chang, “1.2 V CMOS switched-capacitor circuits,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1996, pp. 388–389. [6] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,”IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar. 1995. [7] J.S. Witters, G. Groeseneken, and H. E. Maes, “Analysis and modeling of on-chip high-voltage generator circuit for use in EEPROM circuits,” IEEE J. Solid-State Circuits, vol. 24, pp. 1372 1380, Oct. 1989. [8] T. Tanzawa and T. Tanaka, “A dynamic analysis of the Dickson charge pump circuit,”IEEE J. Solid-State Circuits, vol. 32, pp. 1231–1240, Aug. 1997. [9] K.-H. Choi, J.-M. Park, J.-K. Kim, T.-S. Jung, and K.-D. Suh, “Floating-well charge pump circuits for sub-2.0 V single power supply Flash memories,” inSymp. VLSI Circuits Dig. Tech. Papers, June 1997, pp. 61–62. [10] A. Umezawa, S. Atsume, M. Kuriyama, H. Banba, K. Imamiya, K. Naruke, S. Yamada, E. Obi, M. Oshikiri, T. Suzuki, and S. Tanaka, “A 5-V-only operation 0.6-ım Flash EEPROM with row decoder scheme in triple-well structure,” IEEE J. Solid-State Circuits, vol. 27, pp. 1540–1546, Nov. 1992. [11] K. D. Tedrow, J. J. Javanifard, and C. Galindo, “Method and apparatus for a two phase bootstrap charge pump,” U.S. Patent 5 432 469, July 1995. [12] K. Sawada, Y. Sugawara, and S. Masui, “An on-chip high-voltage generator circuit for EEPROM’s with a power supply voltage below 2 V,” inSymp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 75–76. [13] E. Lingstaedt and P. Miller, “MOSFET multiplying circuit,” U.S. Patent 5 029 063, July 1991. [14] J. Tsujimoto, “Charge pump circuit having a boosted output signal,” U.S. Patent 4 935 644, June 1990 [15] Nan-Xiong Huang1, Miin-Shyue Shiau2, Zong-Han Hsieh, Hong-Chong Wu4, Don-Gey Liu,” Improving the Efficiency of Mixed-Structure Charge Pumps by the Multi-Phase Technique”,2010 IEEE [16] S. Singer, ”Inductance-less up dc-dc converter,” IEEE Journal of Solid-State Circuits, vol. SC-17, pp. 778-781, Aug. 1982. [17] J. Witters, G. Groeseneken, and H. Maes, “Analysis and modeling of on-chip high voltage generator circuits for use in EEPROM circuits,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1372–1380, Oct. 1989. [18] S. Hobrecht, “An intelligent BiCMOS/DMOS quad 1-A high-side switch,” IEEE J. Solid State Circuits, vol. SC-25, no. 6, pp. 1395–1402, Dec. 1990. [19] R. Gariboldi and F. Pulvirenti, “A 70 mV intelligent high side switch with full diagnostics, ” IEEE J. Solid State Circuits, vol. 31, no. 7, pp. 915–923, July 1996
  • 10. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India [20] T. Iinbo, et al., “A 5-V-only 16-Mb flash memory with sector erase mode,” IEEE J. Solid State Circuits, vol. 27, no. 11, pp. 1547–1553, Nov. 1992 [21] G. Palumbo, D. Pappalardo, and M. Gaibotti, “Charge pump with adaptive stages for non-volatile memories,” IEE Proc. Circuits, Devices System., vol. 153, no. 2, pp. 136–142, 106 Apr. 2006. [22] R. Castillo and L. Tomasini,“1.5-V high-performance SC filters in BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 930–936, July 1991. [23] Y. Tsiatouhas, “A stress-relaxed negative voltage-level converter,” IEEE Trans. Circuits System. II, vol. 54, no. 3, pp. 282–286, Mar. 2007.