Power 9 Overview

1. OpenPOWER and POWER9
Steve Fields
IBM Fellow
Chief Engineer of Power Systems
August 13, 2018

2. ©2016 IBM Corporation 2
Fundamental forces are accelerating change in our industry
Price/Performance
Full system stack innovation required
Moore’s Law
IT innovation can no longer come from
just the processor
Cognitive
Custom Hyperscale
Data Centers
Hybrid Cloud
Open Solutions
IT consumption models
are expanding
Technology and
Processors
2000 2020
Firmware / OS
Accelerators
Software
Storage
Network
2
Full Stack
Acceleration
(Lower is
better)
Not only is Moore’s Law “coming to an end in practical term, in that chip speeds can be expected to stall, but it
is actually likely to roll back in terms of performance …”– William Holt, Intel Executive Vice President and General Manager

3. ©2016 IBM Corporation 3
System Architecture Must Keep Up
3
Memory
I/O
Bandwidth per Core
2012 2018
1. Bandwidth demand of applications is
increasing
2. Inefficiencies of traditional I/O subsystem
become more pronounced at high
throughput
3. Storage Class Memory will be a major
disruptor
Must think about CPU & System
Architecture Differently
• More bandwidth to memory, network, storage
• New interfaces to remove software overhead
and allow I/O and accelerator devices to
integrate natively within applications
• Flexibility to exploit diversity of memory
technologies

4. Proposed Ecosystem Enablement
System Operating Environment Software Stack
A modern development environment is emerging
based on tools and services
Cloud
Software
Operating
System / KVM
Standard Operating
Environment
(System Mgmt)
Software
Power Open Source Software Stack Components
Existing
Open
Source
Software
Communities
Firmware
Hardware
New OSS
Community
OpenPOWER
Technology
OpenPOWER
Firmware
CAPP
PCIe
POWER8
CAPI over PCIe
Standard POWER Products – 2014
Hardware
“Custom POWER SoC” – Future
Customizable
Framework to Integrate
System IP on Chip
Industry IP License Model
Multiple Options to Design with POWER Technology Within OpenPOWER
40,000 packages now available

5. PCI Gen X
OpenCAPI Northbound
OpenCAPI & PCI
Yesterday’s Plumbing
Tomorrow’s Differentiation
JEDEC Buffer
OpenCAPI / NVLink
Future Evolution of System Architecture
CPU/Accelerator Bandwidth
System Bus
768 GB/s
BBBBBB BBBBBB BBBBBB
Cores &
Caches
Cores &
Caches
Cores &
Caches
Yesterday’s Plumbing
Tomorrow’s Differentiation
System bottleneck
1x 2x
5x 7-10x
5

6. IBM Systems | 6
POWER8

7. © 2016 IBM Corporation7
Memory
Interface
Control
Memory
IBM & Partner
Devices
CAPI/PCI
POWER8 Processor
DMI
Cores
• 12 cores / 8 threads per core
• TDP: 130W and 190W
• 64K data cache, 32K instruction cache
Accelerators
• Crypto & memory expansion
• Transactional Memory
Caches
• 512 KB SRAM L2 / core
• 96 MB eDRAM shared L3
Memory Subsystem
• Memory buffers with 128MB Cache
• ~70ns latency to memory
Bus Interfaces
• Durable Memory attach Interface (DMI)
• Integrated PCIe Gen3
• SMP Interconnect for up to 4 sockets
Virtual Addressing
• Accelerator can work with same memory
addresses that the processors use
• Pointers de-referenced same as the host
application
• Removes OS & device driver overhead
Hardware Managed Cache Coherence
• Enables the accelerator to participate in “Locks”
as a normal thread
• Lowers Latency over IO communication model
6 Hardware Partners developing with CAPI
Over 20 CAPI Solutions
• All listed here http://ibm.biz/powercapi
Examples of Available CAPI Solutions
• IBM Data Engine for NoSQL
• DRC Graphfind analytics
• Erasure Code Acceleration for Hadoop
Coherent Accelerator Processor Interface
(CAPI)
22nm SOI, eDRAM, 15 ML 650mm2
Server Class Memories
(SCM)
• First Functioning Demo of SCM in an Enterprise system
• 15x better than SSD
• Natively non-volatile ST-MRAM DIMMs (Everspin)
• Avoids NVDIMM complications (DRAM to FLASH and back)
• No Supercaps with umbilicals required
SMP

8. Traditional I/O Subsystem
8Think 2018 / DOC ID / March 21, 2018 / © 2018 IBM Corporation
CPU and Memory overheads increase with device throughput
Accelerator only useful for large operations with very high value

9. Coherent Attach Model
POWER8 CAPI (coherent accelerator/processor interface)
9Think 2018 / DOC ID / March 21, 2018 / © 2018 IBM Corporation
CPU and memory overhead is eliminated
CPU and Accelerator cooperate natively to execute the application
Programmer treats accelerator much like another CPU thread

10. IBM Systems
|10
Introducing 822LC Power System for HPC
First Custom-Built GPU Accelerator Server with NVLink
2.5x Faster CPU-GPU Data
Communication via NVLink
NVLink
80 GB/s
GPU
P8
GPU GPU
P8
GPU
PCIe
32 GB/s
GPU
x86
GPU GPU
x86
GPU
No NVLink between CPU & GPU
for x86 Servers: PCIe Bottleneck
NVIDIA P100 Pascal GPU
POWER8 NVLink Server x86 Servers with PCIe
• Custom-built GPU Accelerator Server
• High-Speed NVLink Connections between
CPUs & GPUs and among GPUs
• Features novel NVIDIA P100 Pascal GPU
accelerator

11. IBM Systems | 11
POWER9

12. © 2014 IBM Corporation
POWER9 Processor – Common Features
12
New Core Microarchitecture
• Stronger thread performance
• Efficient agile pipeline
• POWER ISA v3.0
Enhanced Cache Hierarchy
• 120MB NUCA L3 architecture
• 12 x 20-way associative regions
• Improved LRU heuristics
• Fed by 7 TB/s On Chip Bandwidth
Cloud + Virtualization Innovation
• Quality of service assists
• New interrupt architecture
• Workload optimized frequency
• Hardware enforced trusted execution
Leadership
Hardware Acceleration Platform
• Enhanced on-die acceleration
• NVLINK 2.0: High bandwidth,
coherent GPU (25G Link)
• CAPI 2.0: Coherent accelerator and
storage attach (PCIe G4)
• OpenCAPI: Improved latency and
bandwidth (25G Link)
State of the Art IO Subsystem
• 48 PCIeG4 lanes – 192GB/s
High Bandwidth
Signaling Technology
• 16 Gb/s interface
– local SMP
• 25 Gb/s IBM interface
– Accelerator, remote SMP
Accel
Link
Cor
e
L2 L2 L2 L2
L2 L2 L2 L2
L2 L2 L2 L2
L3
Region
Memory
Interface
Accel
Link
SMP
SMPInterconnect&
OffChipAcceleratorEnablement
PCIe
Memory
Interface
SMP/Accelerator Signaling
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
Cor
e
On Chip Accel
Memory Signaling
SMP/Accelerator Signaling Memory Signaling
SMPSignaling
PCIeSignaling
L3
Region
L3
Region
L3
Region
L3
Region
L3
Region
L3
Region
L3
Region
L3
Region
L3
Region
L3
Region
L3
Region
14nm finFET Semiconductor Process
- Improved device performance &
reduced energy
- 17 layer metal stack, eDRAM
- 8.0 Billion Transistors

13. © 2014 IBM Corporation
Scale Out
Direct Attach Memory
8 Direct DDR4 Ports 8 Buffered Channels
POWER9 – Dual Memory Subsystems
Scale Up
Buffered Memory
13
• Up to 140 GB/s of sustained bandwidth
• Low latency access
• Commodity packaging form factor
• Adaptive 64B / 128B reads
• Up to 230GB/s of sustained bandwidth
• Extreme capacity – up to 8TB / socket
• Superior RAS w/ chip kill & lane sparing
• Durable from POWER8 systems
• Agnostic interface for alternate memory innovations

14. © 2014 IBM Corporation
14

15. © 2018 IBM Corporation
OpenCAPI – An Open heterogeneous architecture standard
OpenCAPI 3.0
OpenCAPI 3.1
OpenCAPI specifications
are downloadable from the
website
at www.opencapi.org
- Register
- Download

16. IBM Systems | 16
NVLink Evolution in POWER HPC
Graphics Memory Graphics Memory
NVIDIA Volta GPU with NVLink 2.0
POWER9
Graphics Memory
System Memory
75+75
G
B
/s
75+75
G
B
/s
75+75 GB/s
Graphics Memory
System Memory
50+50
G
B/s
50+50
GB/s
50+50
GB/s
50+50GB/s
50+50 GB/s
Graphics Memory
System Memory POWER9
Graphics Memory
POWER8
NVIDIA P100 GPU with NVLink 1.0
2016 2017-2018
Graphics Memory
50+50
GB/s

17. © 2014 IBM Corporation
Two super computers for Oak Ridge and Lawrence
Livermore Labs in 2017.
Sequoia (LLNL)
2012 - 2017
Mira (ANL)
2012 - 2017
Titan (ORNL)
2012 - 2017
Current DOE Leadership Computers
IBM, Mellanox, and NVIDIA awarded
$325M U.S. Department of Energy’s Super Computer bids
5X – 10X Higher Application Performance versus Current Systems
>100 PF, 2 GB/core main memory, local NVRAM,
Mellanox EDR 100Gb/s InfiniBand, IBM POWER CPUs, NVIDIA Tesla GPUs
© 2015 OpenPOWER Foundation
17
US DOE CORAL Program

18. PowerAI
18
Open Source Frameworks:
Supported Distribution
Developer Ease-of-Use Tools
Faster Training Times via
HW & SW Performance Optimizations
Integrated & Supported AI Platform
Higher Productivity for Data Scientists
Enable non-Data Scientists to use AI
GPU-Accelerated
Power Servers
Storage