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VI Chip PRM® Pre-Regulated Module




                                    1
VI Chip Regulator Module (PRM)
                                       ›   Non-isolated ‘Buck-Boost’ topology
                                       ›   Fixed, high frequency (~1.3 MHz)
                                       ›   Efficiency up to 97%
                                       ›   Wide input range to regulated output
                                           – Commercial:
                                             › Input voltage:
                                               18 – 36 V, 18 – 60 V, 38 – 55 V, 36 – 75 V
                                             › Output voltage: 26 – 55 V, 5 – 55 V
                                             › Output power:
                                               120 W, 170 W, 200 W, 240 W, 320 W, 400 W
                                           – MIL-COTS:
                                             › Input voltage: 16 – 50 V
                                             › Output voltage: 26 – 50 V
   Full-chip: 1.28” x 0.87” x 0.265”         › Output power: 120 W
   Half-chip: 0.65” x 0.87” x 0.625”
                                       › Usage
                                           – Upstream regulator for a downstream VTMs
                                           – Stand-alone, non-isolated regulator




                                                                                            2
Value Proposition: Power Density

› High power density enables:
 – More functions (Gbps, ports, flops, capacity) in the same space
 – A more powerful system without a larger power supply
 – A more powerful system without a heavier power supply
› VI Chip power density enables:
 – Systems that would be impossible with conventional approaches
 – Systems that would be too large, too heavy or not cost effective
   with a conventional approach
› VI Chips decrease power footprint by 40% today
› Power density increase of 25% every 2.5 years



                                                                      3
Value Proposition: Efficiency

› High efficiency enables:
 – Smaller, cooler, quieter systems
 – Energy cost savings for end user
 – High performance systems with minimal total cost of ownership
› VI Chip architectures reduce hidden power losses
 – A “whole system approach”, not just a focus on one conversion stage
› VI Chip technology continues to raise the efficiency standard
 – IBC has half the power loss compared to industry IBC average.
 – Alternative solutions are at the technological limit with
   respect to efficiency improvements
 – New Vicor products cut losses by 20% every 2.5 years



                                                                         4
Value Proposition: Flexibility
                                 › Flexibility enables:
                                  – Re-use of power components
                                     in multiple products
                                  – Fewer SKUs, higher volume,
                                     lower cost
                                  – Fast time to market
                                  – Reduced development effort
                                 › VI Chip technology reduces the need
                                   for custom power systems
                                  – Power component paradigm
                                 › Expanding portfolio of products
                                   increases flexibility over time
                                  – More options, more configurability,
                                     less complexity, shorter design time


                                                                            5
Factorized Power Architecture
› Definition: Factorized Power is…
 – The separation of Regulation, Isolation, and voltage Transformation functions
   typically contained together within a “brick” DC-DC converter
› Components:
 – Small, highly efficient, flexible, building blocks called “VI Chips”
  › PRM – Pre Regulation Module
  › VTM – Voltage Regulation Module
  › BCM – Bus Converter Module
› Advantages:
 –   Reduces the physical area and volume space of the power converters
 –   Reduces power dissipation at the Point of Load
 –   Reduces distribution losses
 –   Eliminate unnecessary converter functions to improve system efficiency


                                                                                   6
48 V Factorized Bus Architecture (FPA)
› Intermediate Bus Architecture (IBA)
 –   e.g., 48 – 12 V bus converters, then 12 V – 1.x V buck regulators
 –   Trade-off between I2R distribution loss and buck duty cycle
 –   Load <1 V means <10% duty cycle
 –   FET peak voltage much higher (>12 V) than load voltage (1 V)
› Factorized Power Architecture (FPA)
 –   Pre-regulators (PRM), then Current Multipliers (VTM)
 –   Efficient power distribution (48 V)
 –   Load <1 V with ~ 100% VTM duty cycle
 –   FETs are low voltage (e.g., 3 V) so low RDS(ON)
     and high performance                                     Full-chip
› Benefits of current multiplication at the load              Up to 130 A
                                                              1.28 x 0.87 x 0.265 in (1.1 in2), 0.5 oz
 –   Fast transient response                                  3.25 x 2.2 x 0.67 cm (7.2 cm2), 15 g

 –   No bulk capacitors                                       Half-chip
                                                              Up to 200 W
 –   High density                                             0.64 x 0.87 x 0.265 in (0.55 in2), 0.25 oz
                                                              1.63 x 2.2 x 0.67 cm (7.2 cm2), 8 g
 –   High efficiency
 –   High PoL functionality

                                                                                                           7
Wide (11:1) Trim Range

› Extreme trim range with simple, small system
– Use K = ¼ for 1.25 – 13.75 V range
– Use K = 1/40 for 0.125 – 1.375 V

                                           To set…                        To get…
                     Adjust                  55 V                         13.75 V
          55 V        R1
   48 V                       PRM                        VTM                        12 V
   nom                                                                              nom
          38 V
                          PRM48BF048T200               VTM48EH120T010
                             Regulator     26 V         12V, K=1/4 VTM                     11:1 trim
                                                                                            range
                                                                         6.5 V
                                                  5V

                                                                           1.25 V




                                                                                                       8
Local Loop Regulation: No sense lines




                                      K-factor
          Unregulated    Regulated
          Wide Range     Factorized              Vf • K- IOUT•ROUT
             Input          Bus
 Source                                                      Load    3 – 5%
                                Vf


                        Local
                        Loop
                                                                         9
Adaptive Loop Regulation: No sense lines and POL Regulation




                                      K-factor
          Unregulated    Regulated
          Wide Range     Factorized
             Input          Bus
 Source                                           Load   1 – 2%
                            Vf


                          Adaptive
                           Loop
                                                            10

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VI Chip PRM® Pre-Regulated Module

  • 1. VI Chip PRM® Pre-Regulated Module 1
  • 2. VI Chip Regulator Module (PRM) › Non-isolated ‘Buck-Boost’ topology › Fixed, high frequency (~1.3 MHz) › Efficiency up to 97% › Wide input range to regulated output – Commercial: › Input voltage: 18 – 36 V, 18 – 60 V, 38 – 55 V, 36 – 75 V › Output voltage: 26 – 55 V, 5 – 55 V › Output power: 120 W, 170 W, 200 W, 240 W, 320 W, 400 W – MIL-COTS: › Input voltage: 16 – 50 V › Output voltage: 26 – 50 V Full-chip: 1.28” x 0.87” x 0.265” › Output power: 120 W Half-chip: 0.65” x 0.87” x 0.625” › Usage – Upstream regulator for a downstream VTMs – Stand-alone, non-isolated regulator 2
  • 3. Value Proposition: Power Density › High power density enables: – More functions (Gbps, ports, flops, capacity) in the same space – A more powerful system without a larger power supply – A more powerful system without a heavier power supply › VI Chip power density enables: – Systems that would be impossible with conventional approaches – Systems that would be too large, too heavy or not cost effective with a conventional approach › VI Chips decrease power footprint by 40% today › Power density increase of 25% every 2.5 years 3
  • 4. Value Proposition: Efficiency › High efficiency enables: – Smaller, cooler, quieter systems – Energy cost savings for end user – High performance systems with minimal total cost of ownership › VI Chip architectures reduce hidden power losses – A “whole system approach”, not just a focus on one conversion stage › VI Chip technology continues to raise the efficiency standard – IBC has half the power loss compared to industry IBC average. – Alternative solutions are at the technological limit with respect to efficiency improvements – New Vicor products cut losses by 20% every 2.5 years 4
  • 5. Value Proposition: Flexibility › Flexibility enables: – Re-use of power components in multiple products – Fewer SKUs, higher volume, lower cost – Fast time to market – Reduced development effort › VI Chip technology reduces the need for custom power systems – Power component paradigm › Expanding portfolio of products increases flexibility over time – More options, more configurability, less complexity, shorter design time 5
  • 6. Factorized Power Architecture › Definition: Factorized Power is… – The separation of Regulation, Isolation, and voltage Transformation functions typically contained together within a “brick” DC-DC converter › Components: – Small, highly efficient, flexible, building blocks called “VI Chips” › PRM – Pre Regulation Module › VTM – Voltage Regulation Module › BCM – Bus Converter Module › Advantages: – Reduces the physical area and volume space of the power converters – Reduces power dissipation at the Point of Load – Reduces distribution losses – Eliminate unnecessary converter functions to improve system efficiency 6
  • 7. 48 V Factorized Bus Architecture (FPA) › Intermediate Bus Architecture (IBA) – e.g., 48 – 12 V bus converters, then 12 V – 1.x V buck regulators – Trade-off between I2R distribution loss and buck duty cycle – Load <1 V means <10% duty cycle – FET peak voltage much higher (>12 V) than load voltage (1 V) › Factorized Power Architecture (FPA) – Pre-regulators (PRM), then Current Multipliers (VTM) – Efficient power distribution (48 V) – Load <1 V with ~ 100% VTM duty cycle – FETs are low voltage (e.g., 3 V) so low RDS(ON) and high performance Full-chip › Benefits of current multiplication at the load Up to 130 A 1.28 x 0.87 x 0.265 in (1.1 in2), 0.5 oz – Fast transient response 3.25 x 2.2 x 0.67 cm (7.2 cm2), 15 g – No bulk capacitors Half-chip Up to 200 W – High density 0.64 x 0.87 x 0.265 in (0.55 in2), 0.25 oz 1.63 x 2.2 x 0.67 cm (7.2 cm2), 8 g – High efficiency – High PoL functionality 7
  • 8. Wide (11:1) Trim Range › Extreme trim range with simple, small system – Use K = ¼ for 1.25 – 13.75 V range – Use K = 1/40 for 0.125 – 1.375 V To set… To get… Adjust 55 V 13.75 V 55 V R1 48 V PRM VTM 12 V nom nom 38 V PRM48BF048T200 VTM48EH120T010 Regulator 26 V 12V, K=1/4 VTM 11:1 trim range 6.5 V 5V 1.25 V 8
  • 9. Local Loop Regulation: No sense lines K-factor Unregulated Regulated Wide Range Factorized Vf • K- IOUT•ROUT Input Bus Source Load 3 – 5% Vf Local Loop 9
  • 10. Adaptive Loop Regulation: No sense lines and POL Regulation K-factor Unregulated Regulated Wide Range Factorized Input Bus Source Load 1 – 2% Vf Adaptive Loop 10