This document summarizes the results of device modeling and simulation for a CMOS digital integrated circuit (TC7SET02F) manufactured by Toshiba. It includes truth tables, circuit diagrams, simulation waveforms and comparison tables for propagation delay, input/output voltage levels, and output responses under different input conditions. The simulation results closely match measurements with less than 1% error.
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SPICE MODEL of TC7SET02F in SPICE PARK
1. Device Modeling Report
COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT
PART NUMBER : TC7SET02F
MANUFACTURER : TOSHIBA
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
2. Truth Table
Circuit simulation result
U1:A 0
U1:B 0
Y1 1
0s 0.5us 1.0us
Time
Evaluation circuit
U1
LO
INB VCC
LO
INA
GND OUTY
Y1
TC7SET02 V1
R1
1MEG 5
0
Comparison table
Input Output
%Error
An Bn Yn (Measurement) Yn (Simulation)
L L H H 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
3. Truth Table
Circuit simulation result
U1:A 0
U1:B 1
Y1 0
0s 0.5us 1.0us
Time
Evaluation circuit
U1
HI INB VCC
LO
INA
GND OUTY
Y1
TC7SET02 V1
R1
1MEG 5
0
Comparison table
Input Output
%Error
An Bn Yn (Measurement) Yn (Simulation)
L H L L 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
4. Truth Table
Circuit simulation result
U1:A 1
U1:B 0
Y1 0
0s 0.5us 1.0us
Time
Evaluation circuit
U1
LO
INB VCC
HI INA
GND OUTY
Y1
TC7SET02 V1
R1
1MEG 5
0
Comparison table
Input Output
%Error
An Bn Yn (Measurement) Yn (Simulation)
H L L L 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
5. Truth Table
Circuit simulation result
U1:A 1
U1:B 1
Y1 0
0s 0.5us 1.0us
Time
Evaluation circuit
U1
HI INB VCC
HI INA
GND OUTY
Y1
TC7SET02 V1
R1
1MEG 5
0
Comparison table
Input Output
%Error
An Bn Yn (Measurement) Yn (Simulation)
H H L L 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
6. High Level and Low Level Input Voltage
Circuit simulation result
5.0V
Output
2.5V Input
0V
0s 1.0ms 2.0ms 3.0ms 4.0ms
V(R1:1) V(V1:+)
Time
Evaluation circuit
U1
INB VCC
LO
INA
GND OUTY
V1
V1 = 0 V2
TC7SET02
V2 = 5
TD = 0.5m
TR = 0.1m 5
TF = 0.1m R1
PW = 1m
PER = 2m 1MEG
0
Comparison table
VCC = 5V Measurement Simulation %Error
VIH (V) 2.0 2.0021 0.105
VIL (V) 0.8 0.799535 -0.058
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
7. High Level and Low Level Output Voltage
Circuit simulation result
5.0V
2.5V
Output
0V
V(R1:1) Input
5.0V
2.5V
SEL>>
0V
0s 5ms 10ms
V(V1:+)
Time
Evaluation circuit
U1
INB VCC
LO
INA
GND OUTY
V1
V1 = 0 V2
TC7SET02
V2 = 4.5
TD = 0.5m
TR = 3n 4.5
TF = 3n R1
PW = 1m
PER = 2m 1MEG
0
Comparison table
VCC = 4.5V Measurement Simulation %Error
VOH (V) 4.5 4.4990 -0.022
VOL (V) 0 0 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
8. Propagation Delay Time
Circuit simulation result
5.0V
Output
2.5V Input
0V
0s 50ns 100ns
V(U1:Y) V(V1:+)
Time
Evaluation circuit
U1
INB VCC
LO
INA
GND OUTY
V1 V2
TC7SET02
V1 = 0
V2 = 5
TD = 10n 5
TR = 3n
TF = 3n C1
PW = 50n
PER = 100n 15p
0
Comparison table
CL=15pF,VCC=5V,Tr=Tf=3ns Measurement Simulation %Error
tpLH (ns) 4.2 4.2316 0.752
tpHL (ns) 4.2 4.2442 1.052
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005