This document summarizes the results of device modeling simulations for a TC7SZ125F CMOS digital integrated circuit manufactured by Toshiba. The document includes truth tables, circuit schematics, simulation waveforms, and comparison tables that evaluate the circuit's performance against specifications for input/output voltage levels, propagation delay times, and enable/disable times under varying operating conditions.

1. Device Modeling Report
COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT
PART NUMBER : TC7SZ125F
MANUFACTURER : TOSHIBA
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

2. Truth Table
Circuit simulation result
U1:INA 1
U1:GBAR 1
5.0V
2.5V
0V
0s 0.5us 1.0us
V(R1:1)
Time
Evaluation circuit
U1
_
HI G VCC
DSTM1
CLK IN A
OFFTIME = .2uS
ONTIME = .2uS GND OUT Y
V1
5
TC7SZ125
R1
1G
0
Comparison table
Input Output
%Error
A G Y (Measurement) Y (Simulation)
X H Z Z 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

3. Truth Table
Circuit simulation result
U1:INA 0
U1:GBAR 0
5.0V
2.5V
0V
0s 0.5us 1.0us
V(R1:1)
Time
Evaluation circuit
U1
_
LO
G VCC
LO
IN A
GND OUT Y
V1
5
TC7SZ125
R1
1G
0
Comparison table
Input Output
%Error
A G Y (Measurement) Y (Simulation)
L L L L 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

4. Truth Table
Circuit simulation result
U1:INA 1
U1:GBAR 0
5.0V
2.5V
0V
0s 0.5us 1.0us
V(R1:1)
Time
Evaluation circuit
U1
_
LO
G VCC
HI IN A
GND OUT Y
V1
5
TC7SZ125
R1
1G
0
Comparison table
Input Output
%Error
A G Y (Measurement) Y (Simulation)
H L H H 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

5. High Level and Low Level Input Voltage (VCC = 1.8 V)
Circuit simulation result
2.0V
(588.005u,1.5841)
Output
1.0V Input
(511.904u,214.263m)
0V
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUTY) V(V1:+)
Time
Evaluation circuit
U1
_
LO
G VCC
IN A
GND OUT Y
OUTY V2
1.8
TC7SZ125
V1 = 0
V2 = 1.8 V1
TD = 0.5m R1
TR = 0.1m
TF = 0.1m 1G
PW = 1m
PER = 2m
0
Comparison table
VCC = 1.8V Measurement Simulation %Error
Min VIH = (0.88*VCC) V 1.584 1.5841 0.006
Max VIL = (0.12*VCC) V 0.216 0.214263 -0.804
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

6. High Level and Low Level Input Voltage (VCC = 5 V)
Circuit simulation result
5.0V
(575.002u,3.7501)
Output
2.5V Input
(524.901u,1.2450)
0V
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUTY) V(V1:+)
Time
Evaluation circuit
U1
_
LO
G VCC
IN A
GND OUT Y
OUTY
TC7SZ125 V2
V1 = 0
V2 = 5 V1 5
TD = 0.5m R1
TR = 0.1m
TF = 0.1m 1G
PW = 1m
PER = 2m
0
Comparison table
VCC = 5V Measurement Simulation %Error
Min VIH = (0.75*VCC) V 3.75 3.7501 0.003
Max VIL = (0.25*VCC) V 1.25 1.2450 -0.400
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

7. High Level Output Voltage (VCC = 1.8 V)
Circuit simulation result
2.0V
Output
Input
1.0V
0V
0s 5ms 10ms
V(U1:OUTY)
Time
Evaluation circuit
U1
_
LO
G VCC
IN A
GND OUT Y
V1 TC7SZ125 V2
1.6 1.8
I1
-100u
0
Comparison table
VIN = VIH, VCC = 1.8 V Measurement Simulation %Error
VOH (V) 1.8 1.7999 -0.006
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

8. Low Level Output Voltage (VCC = 1.8 V)
Circuit simulation result
5.0V
Output
Input
2.5V
0V
0s 5ms 10ms
V(U1:OUTY)
Time
Evaluation circuit
U1
_
LO
G VCC
IN A
GND OUT Y
V1 TC7SZ125 V2
0.2 1.8
I1
100u
0
Comparison table
VIN = VIL, VCC = 4.5 V Measurement Simulation %Error
VOL (V) 0 0 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

9. High Level Output Voltage (VCC = 4.5 V)
Circuit simulation result
5.0V
Output
Input
2.5V
0V
0s 5ms 10ms
V(U1:OUTY)
Time
Evaluation circuit
U1
_
LO
G VCC
IN A
GND OUT Y
V1 TC7SZ125 V2
3.4 4.5
I1
-100u
0
Comparison table
VIN = VIH, VCC = 4.5 V Measurement Simulation %Error
VOH (V) 4.5 4.4991 -0.02
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

10. Low Level Output Voltage (VCC = 4.5 V)
Circuit simulation result
5.0V
Output
Input
2.5V
0V
0s 5ms 10ms
V(U1:OUTY)
Time
Evaluation circuit
U1
_
LO
G VCC
IN A
GND OUT Y
V1 TC7SZ125 V2
1 4.5
I1
100u
0
Comparison table
VIN = VIL, VCC = 4.5 V Measurement Simulation %Error
VOL (V) 0 0 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

11. Propagation Delay Time (VCC = 1.8 V)
Circuit simulation result
2.0V
Output
Input
1.0V
0V
0s 0.5us 1.0us
V(TPLH) V(V1:+)
Time
Evaluation circuit
U1
_
LO
G VCC
IN A
tplh
GND OUT Y
V1 = 0 V2
TC7SZ125
V2 = 1.8
TD = 0.2u V1
TR = 3.8n
TF = 3.8n R1 C1 1.8
PW = 0.5u
PER = 1u 1MEG 15p
0
Comparison table CL = 15 pF, RL = 1 M
VCC = 1.8V, tr = tf = 3 ns Measurement Simulation %Error
tPLH (ns) 5.3 5.3208 0.392
tPHL (ns) 5.3 5.3079 0.149
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

12. Propagation Delay Time (VCC = 5 V)
Circuit simulation result
5.0V
Output
Input
2.5V
0V
0s 0.5us 1.0us
V(TPLH) V(V1:+)
Time
Evaluation circuit
U1
_
LO
G VCC
IN A
tplh
GND OUT Y
V1 = 0 V2
TC7SZ125
V2 = 5
TD = 0.2u V1
TR = 3.8n
TF = 3.8n R1 C1 5
PW = 0.5u
PER = 1u 500 50p
0
Comparison table CL = 50 pF, RL = 500 
VCC = 5 V, tr = tf = 3 ns Measurement Simulation %Error
tPLH (ns) 2.6 2.6444 1.708
tPHL (ns) 2.6 2.6279 1.073
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

13. Output enable time(tPZH) and Output disable time(tPHZ) (VCC = 1.8 V)
Circuit simulation result
2.0V
Output
Input
1.0V
0V
0s 0.5us 1.0us
V(TPHZ_TPZH) V(U1:GBAR)
Time
Evaluation circuit
U1
_
G VCC
HI IN A
tphz_tpzh
GND OUT Y
V1 = 0
TC7SZ125 V2
V2 = 1.8
TD = 0.2u V1
TR = 3.8n
TF = 3.8n C1 R1 R2
PW = 0.5u 1.8
PER = 1u 50p 500 500
0
Comparison table CL = 50 pF, RL = 500 
VCC = 1.8V, tr = tf = 3 ns Measurement Simulation %Error
tPZH (ns) 7 7.0535 0.764
tPHZ (ns) 5.4 5.4334 0.619
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

14. Output enable time(tPZH) and Output disable time(tPHZ) (VCC = 5 V)
Circuit simulation result
5.0V
Output
Input
2.5V
0V
0s 0.5us 1.0us
V(TPHZ_TPZH) V(U1:GBAR)
Time
Evaluation circuit
U1
_
G VCC
HI IN A
tphz_tpzh
GND OUT Y
V1 = 0
TC7SZ125 V2
V2 = 5
TD = 0.2u V1
TR = 3.8n
TF = 3.8n C1 R1 R2
PW = 0.5u 5
PER = 1u 50p 500 500
0
Comparison table CL = 50 pF, RL = 500 
VCC = 5 V, tr = tf = 3 ns Measurement Simulation %Error
tPZH (ns) 2.8 2.7773 -0.811
tPHZ (ns) 2.1 2.1849 4.043
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

15. Output enable time(tPZL) and Output disable time(tPLZ) (VCC = 1.8 V)
Circuit simulation result
2.0V
Output
Input
1.0V
0V
0s 0.5us 1.0us
V(TPZL_TPLZ) V(V1:+)
Time
Evaluation circuit
U1
_
G VCC
LO
IN A
tpzl_tplz R2
GND OUT Y
500
TC7SZ125 V3
V1 = 0
V2 = 1.8
TD = 0.2u V1 C1 R1 V2
TR = 3.8n 1.8
TF = 3.8n 50p 500
PW = 0.5u 3.6
PER = 1u
0
Comparison table CL = 50 pF, RL = 500 
VCC = 1.8 V, tr = tf = 3 ns Measurement Simulation %Error
tPZL (ns) 7 7.0213 0.304
tPLZ (ns) 5.4 5.4336 0.622
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

16. Output enable time(tPZL) and Output disable time(tPLZ) (VCC = 5 V)
Circuit simulation result
5.0V
Output
Input
2.5V
0V
0s 0.5us 1.0us
V(TPZL_TPLZ) V(V1:+)
Time
Evaluation circuit
U1
_
G VCC
LO
IN A
tpzl_tplz R2
GND OUT Y
500
V1 = 0
TC7SZ125 V3
V2 = 10
TD = 0.2u V1
TR = 3.8n
TF = 3.8n C1 R1 V2
PW = 0.5u 5
PER = 1u 50p 500
10
0
Comparison table CL = 50 pF, RL = 500 
VCC = 5 V, tr = tf = 3 ns Measurement Simulation %Error
tPZL (ns) 2.8 2.7927 -0.261
tPLZ (ns) 2.1 2.1048 0.229
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005