This device modeling report summarizes the simulation results for an operational amplifier component. Key specifications like output voltage swing, input offset voltage, slew rate, input bias current, open loop gain, and common mode rejection ratio are presented along with comparison tables showing good agreement between measurement and simulation results. Circuit diagrams and simulation waveforms provide additional details on the evaluation methodology.

1. Device Modeling Report
COMPONENTS: OPERATIONAL AMPLIFIER
PART NUMBER: MC35172
MANUFACTURER: STMicroelectronics
REMARK TYPE: (OPAMP)
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

2. Spice Model
OU T1 V+
-IN1 OU T2
-
+
+ IN 1 -IN2
-
+
V- + IN 2
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

3. Output Voltage Swing
Simulation result
20V
0V
-20V
-500mV -250mV 0V 250mV 500mV
V(Vout)
V_V1
Evaluation circuit
Rl oa d 10 k Vo ut U1
OU T1 V+
-IN1 OU T2
-
+
+ IN 1 -IN2
-
+
V- + IN 2
MC3 51 72
V+
V1 V-
0V dc 15 Vd c
-15 Vdc
0
Comparison table
Output Voltage Swing Measurement Simulation %Error
VOH (V) 14.200 14.199 -0.007
VOL (V) -14.000 -13.999 -0.007
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

4. Input Offset Voltage
Simulation result
20V
0V
-20V
-10mV -5mV 0V 5mV 10mV
V(Vout)
V_Vin
Evaluation circuit
Rl oa d 2k
U1
OU T1 V+
Vo ut
-IN1 OU T2
-
+
+ IN 1 -IN2
-
+
V- + IN 2
Vi n
Vi V+
MC3 51 72
VO FF = 0 VO FF = 0
VA MPL = 0 VA MPL = 0
FREQ = 0 FREQ = 0 V- 15 Vd c
AC = 0 AC = 0
DC = 0 DC = 0
-15 Vdc
0
Comparison table
Measurement Simulation %Error
Vos(mV)
1.000 1.008 0.790
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

5. Slew Rate
Simulation result
20V
0V
-20V
0s 50us 100us 150us 200us
V(Vout)
Time
Evaluation circuit
Vo ut U1
OU T1 V+
-IN1 OU T2
-
+
+ IN 1 -IN2
-
+
V- + IN 2
Vi V+
MC3 51 72
VO FF = 0 Vi n V1 = -1 4
VA MPL = 0 V2 = 14.2 15 Vd c
FREQ = 0 TD = 0 .1m
AC = 0 TR = 1 0n V-
DC = 0 TF = 10n
PW = 1 m -15 Vdc
PE R = 2m
0
Comparison table
Slew Measurement Simulation %Error
Rate(v/us) 2.000 2.041 2.050
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

6. Input current Ib, Ibos
Simulation result
30nA
25nA
20nA
15nA
10nA
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms
I(Vi) I(Vin)
Time
Evaluation circuit
Vo ut U1
OU T1 V+
-IN1 OU T2
-
+
+ IN 1 -IN2
-
+
V- + IN 2
Vi Vi n
VO FF = 0 VO FF = 0
MC3 51 72
VA MPL = 0 VA MPL = 0 V+
FREQ = 0 FREQ = 0
AC = 0 AC = 0
DC = 0 DC = 0 V- 15 Vd c
V1
-15 Vdc
1.0 079 m
0
Comparison table
Measurement Simulation %Error
Ib(nA) 20.000 20.017 0.085
Ibos(nA) 5.000 5.004 0.084
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

7. Open Loop Voltage Gain vs. Frequency, Av-dc, f-0dB
Simulation result
120
80
40
0
1.0Hz 100Hz 10KHz 1.0MHz 100MHz
DB(V(Vout)/V(Vin:+))
Frequency
Evaluation circuit
RL 2k Vo ut U1
OU T1 V+
-IN1 OU T2
-
+
+ IN 1 -IN2
-
+
V- + IN 2
Vi Vi n
VO FF = 0 V+
MC3 51 72
VA MPL = 0 VO FF = 0 V-
FREQ = 0 VA MPL = 0
AC = 0 FREQ = 0 15 Vd c
DC = 0 AC = 1 m -15 Vdc
DC = 1 .007 9m
0
Comparison table
Measurement Simulation %Error
f-0dB(MHz) 2.100 2.105 0.224
Av-dc(dB) 100.000 100.224 0.224
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

8. Common-Mode Rejection Voltage gain
Simulation result
20V
0V
-20V
0s 1.0s 2.0s 3.0s 4.0s
V(Vout)
Time
Evaluation circuit
Vo ut U1
OU T1 V+
-IN1 OU T2
-
+
+ IN 1 -IN2
-
V1
+
V- + IN 2
1.0 079 m
V+
MC3 51 72
V- 15 Vd c
V
VO FF = 0
VA MPL = 1 0 -15 Vdc
FREQ = 1
AC = 0
DC = 0
0
Common Mode Reject Ratio =20*LOG(102612.4365/(20.277/20))
= 100.1045 dB
CMRR Measurement Simulation %Error
(dB) 100.000 100.105 0.105
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008