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Teng Zhang
1565 W. 29th. Street ● Los Angeles, CA 90007 ● tengzhan@usc.edu ● (213)249-2511
QUALIFICATIONS
 Experience in both object-oriented programming and scripting. Knowledge of data structure, algorithm, OS,
database and computer architecture including Pipeline, CMT, MOSEI protocol, Tomasulo.
 Ready for new environments, teamwork, communication and collaboration.
 Dedicated to work and able to complete projects accurately and on time, based on technical specs.
Software: Visual Studio, Matlab, Cadence, Modelsim, NCSim, Design Compiler, ISE Design Tool, LTspice
Languages: C, C++, Perl, SQL, Verilog, VHDL, System Verilog, System C
EDUCATION
M.S. Electrical Engineering - University of Southern California GPA: 3.78 May. 2015
B.S. Electrical Engineering - Zhejiang University, P.R.C. GPA: 3.8 June 2013
Related Coursework
ZJU1048[C Programming Language & Lab.] ZJU1050[Comprehensive Practice on Programming]
ZJU2115[Principle of Microprocessors and Interface Technology]
EE457 [Computer Systems Organization] EE560 [Digital System Design -- Tools and Techniques]
EE557 [Computer Systems Architecture] CSCI570 [Analysis of Algorithms]
ACADEMIC PROJECT EXPERIENCE
ATPG and Fault Simulator Algorithms Implementation [C++, Visual Studio] Fall 2014
 Designed a preprocessor to read combinational circuits from given files and generate collapsed single
stuck-at-fault lists. Implemented two test pattern generators using D and PODEM algorithms, then generated test
vectors for listed faults individually.
 Finished fault simulation using parallel and deductive fault simulation methods, verified the correctness and fault
coverage for ATPG algorithms.
Image Distortion Correction Program Implementation [C++, Visual Studio] Spring 2013
 Programmed in C++ to implement image distortion correcting by mapping the distorted grid image coming from
camera shooting to ideal grid image. In order to do this, two images will be cut into triangles and affine
transformation is used to build mappings between two sets of coordinates.
 Finished the image reading, analyzing and modifying by using OpenCV library.
Battle City Game Design [C, Win-TC] Spring 2011
 Designed a game with the same rule as the famous Battle City. Implemented three types of tanks, five types of
terrain, seven types of power-ups and five different maps using C and changed player interface into Chinese.
General Purpose CPU Design [Cadence Virtuoso, 180nm tsmc, Perl] Spring 2014
 Finished the schematic and layout design of a general purpose 16-bit Multi-Cycle CPU, fulfilling logic and
arithmetic operations, memory operations and control flow operations.
 Optimized the area, delay and power of the layout design by using dynamic logic and clock gating, which made
the final parameter (Area * Delay * Power/um2
*ns*mw) to be 420276283.3.
 Implemented Instruction Fetch and Decode using Perl script by converting given benchmarks to Cadence vector
file. Generated expected golden results from inputs and generated real signal results from Cadence output file,
compared them and achieved automated result verification all using Perl. Got extra credit.
Tomasulo Processor RTL Design [Xilinx ISE, ModelSim, VHDL] Summer 2014
 Designed basic parts in VHDL, including Dispatch Unit, CFC, ROB, FRL, Issue Unit, Issue Queue, Branch
Prediction Buffer, Address Buffer, Store Buffer, and Load Store Queue.
 Combined different parts together and accomplished Tomasulo Processor design. Finished the behavioral test by
using varied instruction streams and a simple Uart protocol.
WORK EXPERIENCE
Scholarship Office Assistant: Zhejiang University Education Foundation Sep. 2011-Jan. 2012
 Contacted with scholarship candidates and updated information.
 Assisted in preparing for prize presentations of different scholarships.

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RESUME_Teng_Zhang

  • 1. Teng Zhang 1565 W. 29th. Street ● Los Angeles, CA 90007 ● tengzhan@usc.edu ● (213)249-2511 QUALIFICATIONS  Experience in both object-oriented programming and scripting. Knowledge of data structure, algorithm, OS, database and computer architecture including Pipeline, CMT, MOSEI protocol, Tomasulo.  Ready for new environments, teamwork, communication and collaboration.  Dedicated to work and able to complete projects accurately and on time, based on technical specs. Software: Visual Studio, Matlab, Cadence, Modelsim, NCSim, Design Compiler, ISE Design Tool, LTspice Languages: C, C++, Perl, SQL, Verilog, VHDL, System Verilog, System C EDUCATION M.S. Electrical Engineering - University of Southern California GPA: 3.78 May. 2015 B.S. Electrical Engineering - Zhejiang University, P.R.C. GPA: 3.8 June 2013 Related Coursework ZJU1048[C Programming Language & Lab.] ZJU1050[Comprehensive Practice on Programming] ZJU2115[Principle of Microprocessors and Interface Technology] EE457 [Computer Systems Organization] EE560 [Digital System Design -- Tools and Techniques] EE557 [Computer Systems Architecture] CSCI570 [Analysis of Algorithms] ACADEMIC PROJECT EXPERIENCE ATPG and Fault Simulator Algorithms Implementation [C++, Visual Studio] Fall 2014  Designed a preprocessor to read combinational circuits from given files and generate collapsed single stuck-at-fault lists. Implemented two test pattern generators using D and PODEM algorithms, then generated test vectors for listed faults individually.  Finished fault simulation using parallel and deductive fault simulation methods, verified the correctness and fault coverage for ATPG algorithms. Image Distortion Correction Program Implementation [C++, Visual Studio] Spring 2013  Programmed in C++ to implement image distortion correcting by mapping the distorted grid image coming from camera shooting to ideal grid image. In order to do this, two images will be cut into triangles and affine transformation is used to build mappings between two sets of coordinates.  Finished the image reading, analyzing and modifying by using OpenCV library. Battle City Game Design [C, Win-TC] Spring 2011  Designed a game with the same rule as the famous Battle City. Implemented three types of tanks, five types of terrain, seven types of power-ups and five different maps using C and changed player interface into Chinese. General Purpose CPU Design [Cadence Virtuoso, 180nm tsmc, Perl] Spring 2014  Finished the schematic and layout design of a general purpose 16-bit Multi-Cycle CPU, fulfilling logic and arithmetic operations, memory operations and control flow operations.  Optimized the area, delay and power of the layout design by using dynamic logic and clock gating, which made the final parameter (Area * Delay * Power/um2 *ns*mw) to be 420276283.3.  Implemented Instruction Fetch and Decode using Perl script by converting given benchmarks to Cadence vector file. Generated expected golden results from inputs and generated real signal results from Cadence output file, compared them and achieved automated result verification all using Perl. Got extra credit. Tomasulo Processor RTL Design [Xilinx ISE, ModelSim, VHDL] Summer 2014  Designed basic parts in VHDL, including Dispatch Unit, CFC, ROB, FRL, Issue Unit, Issue Queue, Branch Prediction Buffer, Address Buffer, Store Buffer, and Load Store Queue.  Combined different parts together and accomplished Tomasulo Processor design. Finished the behavioral test by using varied instruction streams and a simple Uart protocol. WORK EXPERIENCE Scholarship Office Assistant: Zhejiang University Education Foundation Sep. 2011-Jan. 2012  Contacted with scholarship candidates and updated information.  Assisted in preparing for prize presentations of different scholarships.