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20-42GHz x2

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20-42GHz x2

  1. 1. 1 10 100 A High Performance 20-42 GHz MMIC Frequency Multiplier with Low Input Drive Power and High Output Power Sushil Kumar and Henrik Morkner Avago Technologies, 350 W. Trimble Road, San Jose, CA 95131, USA Abstract A 20-42GHz output frequency GaAs MMIC frequency doubler chip has been developed that requires low input drive power and produces high output power with high fundamental & harmonic suppression without any external filter. This developed chip has an integrated broadband single ended-in to differential-out active Balun with impedance inverter and a broadband waveform shaping circuit. The unique topology of developed Balun helps to produce high voltage swing at differential outputs at low input drive power with excellent amplitude and phase balance over the band. The differential outputs of active Balun are connected to balanced common source FETs and drive the balanced FETs in push-push configuration to generate second harmonics and reject fundamental and higher (odd) order harmonics. This creates a broadband frequency doubler with overlapping input and output frequencies, high conversion efficiency with good fundamental and higher odd harmonic rejection without any external Filter. The doubler work from –9 to +7 dBm. The output power of doubler is +17 to +18dBm in most of the band at Pin=+3dBm. Fundamental suppression is better than 50dBc to 34GHz and minimum 30dBc in the entire band. 3rd and 4th harmonic rejections are also better than 25dBc in most of the band. The phase noise of doubler is –137dBc/Hz at 100 kHz offset (fout=24GHz). The input return loss of doubler is better than 20dB in most of the band and output return loss varies from 10-15dB over the band. It works at Vd =4.5V, Id=100-225mA. Index Terms – Frequency doubler, Active Balun, MMIC I. Introduction Frequency multipliers are essential component to generate a high frequency, low phase noise signal from a low frequency, high performance oscillator. Fig.1 shows an example of phase noise comparison of a high frequency signal generated using a high frequency oscillator and a low frequency oscillator combined with frequency multiplier to generate high signal. Normally multiple multipliers are used in a Tx/Rx chain to generate high frequency signal. So there is a growing demand for a single broadband frequency multipliers that covers all point-to-point radio system (allocated over 17.7 to 40 GHz range), local multipoint distribution system (LMDS; allocated over a frequency range from 22- 42 GHz in the world) and ISM bands. Use of a broadband single multiplier in place of several narrow band multipliers helps inventory and cost reduction for module vendors. The conventional multiplier designs are based on quarter wavelength reflector topology. This topology has several drawbacks like narrow band, bulky in size, poor conversion efficiency and high input drive power, expensive. Such doublers also need an external band pass filter to reject fundamental and other harmonics. In order to reduce MMIC chip size, a balanced device topology is used. This topology has inherent good fundamental and odd harmonic rejection capability. The bandwidth of such topology could be made quite large if proper Balun (for balanced feed to device) is designed. A passive Balun is used as a feed for such broadband doublers [2]. Passive Balun could be designed for excellent phase and amplitude balance over decade bandwidth. The only problem with such passive Balun is, it is lossy thus the doubler needs more input drive power and has high conversion loss. -120 -110 -100 -90 -80 -70 -60 0 10 20 Frequency [GHz] PhaseNoise@100KHzoffset VCO VCO+X4 This paper discusses a design technique of a frequency multiplier that uses an active single ended-in to differential-out Balun, balanced FETs as a doubler and a broadband 4-stage output Fig. (1): Comparison of Phase Noise of a fundamental VCO and a low frequency VCO combined with X4 Multiplier Proceedings of the 1st European Microwave Integrated Circuits Conference 2-9600551-8-7  2006 EuMA September 2006, Manchester UK533 Authorized licensed use limited to: Access Provided by Avago Technologies. Downloaded on July 14,2010 at 23:32:13 UTC from IEEE Xplore. Restrictions apply.
  2. 2. amplifier. This multiplier needs low input drive power has high conversion efficiency and fundamental & higher harmonics rejection. Also this is broadband and a compact size doubler. This doubler works at quite a broad input drive power range from –9 to +7dBm, which is 10-15dBm lower than previous reported work [1-2]. Also conversion loss is also ~8 dB better in most of the band (without output amplifier). The fundamental & higher harmonics rejection is also better [1-3] and chip size is small. II. Circuit Design The top simplified schematic of doubler design is shown in figure 2. 2fo match & filter network It consists of a differential amplifier circuit that acts as an active balun. The outputs of the balun feed the gates of balanced FETs. The Drain of the balanced FETs is connected together. Since the output signals from the Balun have equal amplitude and are anti-phase, this will generate anti-phase drain current in FETs at fundamental frequency & odd harmonics, thus all fundamental and odd harmonics will be cancelled out. The even harmonic drain currents are in phase and so are added in power. Node ‘S’ acts as a virtual ground. Input matching networks (M/N) is designed to provide good match at fundamental frequency. The main objective of output match is to provide as much suppression as possible for fundamental frequency and also to provide match at second harmonic (2H=2*f0) frequency. At the o/p of X2 there is a 4-satge 20-42GHz amplifier that produces ~18dBm Pout. The bandwidth, rejection of fundamental and higher harmonics doubler is mainly dominated by balun performance and to some extent on input & output match also. If balun provides perfect amplitude and phase balance over the desired band, there should not be a common mode at node ‘S’. Any imbalance from balun would develop a finite voltage at node ‘S’ [fig. (2)] and it would no longer be a virtual ground point. This will allow passing the fundamental and other odd harmonics to output port and degrade suppression and conversion loss. A conventional differential amplifier based active balun is shown in fig. 3. This balun has two major drawbacks; [A] It looses it amplitude and phase balance as frequency increases and hence not suitable for broadband [7] and high frequency application. [B] Output impedance (Zout) of this balun is quite high due to high drain impedance of FETs. So needs large output voltage to drive the balanced FETs with lower gate impedance (Zin). Vo2 Vo1 Zout Zin RFout 2fo match & Filter Network CS DF2 DF1 RFin AF1 AF2 T I/P match In order to overcome the drawbacks mentioned above. A new differential active Balun has been developed. It is shown in fig. (4), it consists of FETs AF1, AF2, AF3, AF4 and current source (CS) of fig.3 has been replaced with a resistor. PortP2 Nu m= RR R= 50 SR CC C= 1.0 C CC= 10 C CC=1.0 EE F E EE F E TempN Ug wModel=E EFE T EE F E EE F E TempN UgwMod el=E EFET PortP1 Num= C CC=1 0 LL1 RL=1 0 SR SR C=1.0 R=1 0 RR R=50 CC C=10 CC C= 10 EE F EEE F E Temp NUgw Mod el=E EFET PR PR C=1.0 R=1.0 EE FEEE FE Te mpN UgwModel= EEF ET RFin RFout AF3 AF4 Cs Rs AF1 AF2Vi VO2 VO2 VO AMP DF1 DF2 Frequency Doubler Zout Zin Zout<<Zin In conventional differential Balun (fig.3), the reason for amplitude and phase imbalance is gates of FETs ‘AF1’ and ‘AF2’ sees two different impedances. AF2 is directly grounded and AF1 sees some sort of network. As the frequency increases the effect of this mismatch shows up at Fig. (2): Simplified schematic of doubler MMIC Vg<Vp Active Balun X2 Amplifier S Fig. 3: Conventional Diff Amp Fig. (4): Detail schematic of developed Balun with Balanced FET 534 Authorized licensed use limited to: Access Provided by Avago Technologies. Downloaded on July 14,2010 at 23:32:13 UTC from IEEE Xplore. Restrictions apply.
  3. 3. Fig. 5a: Asymmetrical waveform at node Vo1 & Vo2 the output of ‘AF1’ and ‘AF2’ and causes amplitude and phase mismatch. To minimize this problem, a Cs-Rs network has been added to developed balun (fig.4) and it helps to minimize asymmetry in feed waveforms at AF1 and AF2. The simulated waveforms from the differential active balun at node ‘Vo1’ and ‘Vo2’ are shown in fig.(5). Fig.5a shows asymmetrical waveform without waveform shaping network (Cs-Rs). Fig.5b shows how Cs and Rs symmetries the waveform at Node ‘Vo1’ & ‘Vo2’. 20 40 60 80 100 120 140 160 1800 200 -2.5 -2.0 -1.5 -1.0 -0.5 -3.0 0.0 time, psec ts(HB.Vo1),V ts(HB.Vo2),V 20 40 60 80 100 120 140 160 1800 200 -1.5 -1.0 -2.0 -0.5 time, psec ts(HB.Vo1),V ts(HB.Vo2),V Another feature of this Balun is active impedance transforming FETs AF3 and AF4. The idea of using these FETs is to generate low output impedance (Zout). When the low differential output impedance of the Balun feeds the high impedance (Zin) gates of FETs DF1 and DF2, voltage at node VO1 and VO2 are increased significantly due to high impedance mismatch. The reason is the reflected voltage is added in phase and thus voltage swings at gates are increased without increasing input drive power. III. MMIC Process and CAD tools 0.15μm GaInAs process has been used for circuit fabrication. The ft of active device is 85 GHz. Si3N4 having capacitance 0.38-fF/μm2 forms MIM Capacitors. Resistors are formed by 150Ω/ bulk resistors and 50Ω/ Thin film resistor. The ground to chip is provided by thru substrate via. It has 27pH inductance. The process includes 100% on wafer MMIC test and verification of performance. Agilent’s ADS has been used for circuit simulation. Nonlinear EEHEMT model has been used for device large signal simulation. Momentum simulation has been performed for all spiral inductors and irregular shapes. The fabricated Chip is shown in fig. (6). IV. Measured Performance The measured output power of 2nd harmonic, fundamental (fin), 3rd and 4th harmonics of X2 are shown in fig. (7) for Pin=+3dBm. Pout of 2nd harmonic varies from +17 to +18dBm from 20- 42GHz. Fundamental suppression is >38dBc up to 36GHz. 3rd and 4th harmonic suppressions are also better than 25dBc in most of the band. The degradation in fundamental frequency suppression after 39GHz is caused by balun performance as its amplitude and phase balance degrades beyond 39GHz and also due to overlapping input and output frequencies (fin and 2*fin). The o/p amplifier also contribute to lower fundamental suppression after 36GHz as it adds 15dB or larger gain at fin≥18GHz (fout>36GHz). Dependence of 2nd harmonic output power with Pin=-2 to +4dBm step 2dBm and at Pin=+5dBm is shown in fig. (8). -50 -40 -30 -20 -10 0 10 20 18 20 22 24 26 28 30 32 34 36 38 40 42 44 Output Frequency (GHz) Pout.(dBm) 2H 1H 3H 4H Fig(7) Pout of 2H, Fin, 3H & 4H Vs O/P freq. (Fo) @ Pin=+3dBm Fig.(6) : Photograph of fabricated Chip 2475μm x 990μm x 100 μm Fig. 5b: Symmetrized waveform at node Vo1 & Vo2 (using waveform shaping network Cs-Rs) 535 Authorized licensed use limited to: Access Provided by Avago Technologies. Downloaded on July 14,2010 at 23:32:13 UTC from IEEE Xplore. Restrictions apply.
  4. 4. 0 2 4 6 8 10 12 14 16 18 20 18 20 22 24 26 28 30 32 34 36 38 40 42 44 Output Frequency (GHz) Pout.(dBm) Pin=-2 dBm Pin= 0 dBm Pin=+2 dBm Pin=+4 dBm Pin=+5 dBm Fig.9&10 are frequency doubler (X2) performance alone without any output amplifier. Fig. 9 shows phase noise of X2 only without output amplifier at fout=24GHz. At 100 kHz offset, the phase noise of doubler is -137dbc/Hz. Fig. (10) is measured spectrum plot at fin=12GHz of X2 alone. It indicates fundamental and other harmonics are suppression. -160 -140 -120 -100 -80 -60 -40 -20 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Offset Frequency [Hz] SSBPhaseNoise(dBc/Hz) Fout=24 GHz -80 -70 -60 -50 -40 -30 -20 -10 0 10.0 20.0 30.0 40.0 50.0 Frequency (GHz) Pout(dBm) Frequency Spectrum of 'X2' The I/O return losses are shown in fig. 11. The Input return loss is better than 20dB in most of the band and output return loss ranges from 10-15dB over the band. -30 -25 -20 -15 -10 -5 0 8 12 16 20 24 28 32 36 40 44 Frequency [GHz] S11&S22(dB) S11 S22 V. Conclusion A low input drive power, 18-42GHz-frequency doubler chip has been developed. The doubler has a unique differential active Balun with waveform shaping circuit and an impedance inverting FETs. The differential active balun helped to get a broadband, low input drive power doubler with decent fundamental and other higher harmonic suppression. Acknowledgement Authors are thankful to, Hue B Tran for doing all the measurement; Ed Chan for developing the VEE program to automate the measurement and Wai- Ling Wong for providing the needed technical test related guidance and support. Reference [1.] Hack et. al., “42GHz Active frequency doubler in SiGe bipolar technology”, 3rd Int. Conference Microwave and mmW technology proceedings, Aug. 2002. PP 54-57 [2.] S. Maas et. al., “A Broadband, planar, monolithic resistive frequency doubler”, IEEE, MTT-S, 1994. [3.] M. Schefer, “Integrated quadrupler circuit in coplanar technology for 60 GHz wireless applications”, IEEE, MTT-S, Vol.3, pp 1427- 1430, 2-7 June 2002 [4.] M. Jonsson et. al., “A New FET Frequency Multiplier”, IEEE, MTT-S, Vol.3, pp 1427-1430, June 1998, Baltimore, USA [5.] Takahiro H. et. al., “A Miniaturized Broadband Frequency Doubler”, IEEE, MTT-S , Dec. 1990, pp 819-822. [6.] H. Ma et. al., “Novel Active Differential Phase Splitters in RFIC for wireless applications”, IEEE RFIC symp., 1998, pp. 51-54 [7] H. Ma, “Novel Active Differential Phase Splitters in RFIC for wireless applications”, IEEE Radio Frequency Integrated Circuit symp., Baltimore, USA, June 1998, pp. 51-54 12 GHz 24 GHz 36GHz 48 GHz Fig.(10) : Frequency Spectrum of X2, fin=12GHz Fig.(11) : Plot of Input & Output Return LossFig(8) Pout Vs Fo at varying Pin Fig. (9) Phase Noise performance of X2 @Pin=+3dBm Input Output 536 Authorized licensed use limited to: Access Provided by Avago Technologies. Downloaded on July 14,2010 at 23:32:13 UTC from IEEE Xplore. Restrictions apply.

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