• Click to edit Master text styles  – Second level     • Third level         – Fourthg i t a l D e s i g n u s i n g V H D...
about Start Group• Click to edit Master text styles   Mahmoud Abdellatif  – Second level  Alaa Salah Shehata   Mohamed lev...
Outline• Click to edit Master Introduction to VHDL   – Second level      • Third level                       text styles  ...
• Click to edit Master Introduction to VHDL                       text styles   – Second level             ASIC and FPGA D...
What Is Digital Design !!  • Click to edit Master text stylesDigital hardware has experienced large expansion and improvem...
Designing with Boolean Equations• Click to edit Master text stylesIt would be hard to design any digital system without un...
Schematic based design• Click to edit Master text styles-Schematic based design expanded the     – Second levelcapabilitie...
Hardware Description Language [HDL]• Click to edit Master text stylesQuestion:     – Second levelHow do we know that we ha...
What is VHDL ?• Click toIntegrated Master text styles-Very High Speed                 edit Circuit Hardware Description La...
• Click to edit Master Introduction to VHDL                       text styles   – Second level             ASIC and FPGA D...
ASIC and FPGA Design Flow       Specifications         System Level                                 Design• Click to edit ...
ASIC and FPGA Design Flow• Click to edit Masteroftext styles designing the systemSpecification    is an set requirements b...
ASIC vs FPGA• Click to edit Master text stylesVerilog and VHDL are Hardware Description languages that are used to write p...
FPGAs• Click to edit Master text stylesField-Programmable Gate Arrays– Pre-fabricated silicon devices that comprise of an ...
VHDL vs VerilogVerilog and VHDL are Hardware Description languages that are used to• Click to edit Master text styles     ...
HDL vs Programming Languages                      HDL                               Programming Languages• Examples to edi...
VHDL Language Scope• Click to edit Master text stylesThere is two types of tools that deal with VHDL     – Second level-Si...
• Click to edit Master Introduction to VHDL                       text styles   – Second level             ASIC and FPGA D...
Library and Package  • Click to edit Master text stylesVHDL libraries allow you to store commonly used packages and entiti...
Design Units  • are two types ofedit units in VHDL text stylesThere      Click to design Master       – Not dependent upon...
EntityDefine ports (inputs and outputs) of the module• Click to edit Master text styles          i.e the interface of the ...
- <entity_name> Define the model name• Click to edit Master text styles- <port_name>            Define the port name      ...
Example 01• Click to edit Master text stylesEntity of 2-input AND Gate    – Second levelLIBRARY ieee;                     ...
Question !!System A is composed of system B,C and D.• Click to edit Master text stylesDetermine the entity of system A?   ...
Question !!System A is composed of system B,C and D.• Click to edit Master text stylesDetermine the entity of system A?   ...
Basic data types  VHDL i s s t r o n g l y t y p e d  • Click to BIT Master text styles             edit                  ...
Basic data types   • XClick to edit Master text styles                  Z          0                         1        U   ...
Basic data types  VHDL is strongly typed  • Click to BIT Master text styles             edit                              ...
Example 02• Click to edit Master text stylesEntity of 2-input AND Gate using STD_LOGIC    – Second levelLIBRARY ieee;     ...
ArchitectureDescribe the operation (relations between inputs and outputs) of the module• Click to edit Master text styles ...
Example 032-input AND Gate• Click to edit Master text stylesLIBRARY ieee;    – Second levelUSE ieee.std_logic_1164.all;   ...
Example 04              N-bits 2-input AND Gate              • Click to edit Master text stylesPackagesLibraries          ...
• Click to edit Master Introduction to VHDL                       text styles   – Second level             ASIC and FPGA D...
Demo 01                                    ModelSim Setup                             Using Modelsim SE and Xilinx ISE• Cl...
Summary• VHDL is StronglyeditHardware Description Language.-  Click to typed Master text styles-   There are two basic des...
Time for Your Questions• Click to edit Master text styles  – Second level     • Third level        – Fourth level         ...
Download Session 01 Files• Click to edit Master text stylesRead Session-1 Notes carefully to be ready for the next session...
Take Your Notes                                       Print the slides and take your notes here---------------------------...
Take Your Notes                                       Print the slides and take your notes here---------------------------...
See You Next Session .. Don’t miss• Click to edit Master text styles                     Thank  – Second level     • Third...
Upcoming SlideShare
Loading in …5
×

Session 01 v.3

801 views

Published on

Published in: Technology, Design
1 Comment
0 Likes
Statistics
Notes
  • there are some errors in session
    slide 23 : no need to write first 2 lines
    Slide 31 :
    ARCHITECTURE behave OF AND_GATE IS
    on one line :)
    ‘Z’,’1’,’0’ For synthesis
    All For Simulation
       Reply 
    Are you sure you want to  Yes  No
    Your message goes here
  • Be the first to like this

No Downloads
Views
Total views
801
On SlideShare
0
From Embeds
0
Number of Embeds
99
Actions
Shares
0
Downloads
69
Comments
1
Likes
0
Embeds 0
No embeds

No notes for slide
  • Also Called Digital Logic Design
  • http://www.scribd.com/doc/7304040/Comparison-of-VHDL-Verilog-and-SystemVerilog
  • Session 01 v.3

    1. 1. • Click to edit Master text styles – Second level • Third level – Fourthg i t a l D e s i g n u s i n g V H D L D i level Session One » Fifth level Introduced by Cairo-Egypt Version 03 – June 2012
    2. 2. about Start Group• Click to edit Master text styles Mahmoud Abdellatif – Second level Alaa Salah Shehata Mohamed level • Third Salah Mohamed Talaat – Fourth level » Fifth level start.courses@gmail.com www.slideshare.net/StartGroup www.facebook.com/groups/start.group www.startgroup.weebly.com + 02 0122-4504158 M.A www.youtube.com/StartGroup2011 + 02 0128-0090250 A.S Session One 2
    3. 3. Outline• Click to edit Master Introduction to VHDL – Second level • Third level text styles ASIC and FPGA Design flow How to Read VHDL Code 1 – Fourth level Demo no.1 Using ModelSim SE and Xilinx ISE » Fifth level Session One 3
    4. 4. • Click to edit Master Introduction to VHDL text styles – Second level ASIC and FPGA Design flow • Third level How to Read VHDL Code – Fourth level Demo no.1 Using ModelSim SE and Xilinx ISE » Fifth level Session One 4
    5. 5. What Is Digital Design !! • Click to edit Master text stylesDigital hardware has experienced large expansion and improvement in the past 40 years. Since itsintroduction, the number of transistors in a single chip has grown exponentially, and a silicon chip – Second levelnow contains hundreds of millions of transistors. • Third levelOn Digital world, based on logic, all things are 1 or 0 based on logic basics, all analogue worldshould be quantized to levels "Digits ”. – Fourth levelApplications of digital hardware level » Fifth Digital Computational Circuits *ALUs, Dividers, Multipliers…..+ Digital Communications blocks Digital Control Digital Interfaces *USB, PS2, …..+ Digital Signal Processing [DSP] Session One 5
    6. 6. Designing with Boolean Equations• Click to edit Master text stylesIt would be hard to design any digital system without understanding the basic building blocksas gates and flip-flops. – Second levelBoolean equations are impractical for large design containing hundreds of flip flops because itcould result in a huge number of logical equations. • Third level – Fourth level » Fifth level X= A.B Session One 6
    7. 7. Schematic based design• Click to edit Master text styles-Schematic based design expanded the – Second levelcapabilities of Boolean equations.-Delays and area considerations are important • Thirdand take place here. level – Fourth level-The major drawback of traditional designmethods is the manual translation of design » Fifth leveldescription into a set of logical equations.-This step can be entirely eliminated withhardware description languages (HDLs). Session One 7
    8. 8. Hardware Description Language [HDL]• Click to edit Master text stylesQuestion: – Second levelHow do we know that we have not made a mistakewhen we manually draw a schematic and connect • Third levelcomponents to implement a function?Answer: – Fourth levelBy describing the design Fifth level [such as » in a high-level(c, basic…)+ language, we can simulate our designbefore we manufacture it. This allows us to catchdesign errors, i.e., that the design does not work aswe thought it would.• Simulation guarantees that the design behaves as itshould.HDL is short for Hardware Description Language Session One 8
    9. 9. What is VHDL ?• Click toIntegrated Master text styles-Very High Speed edit Circuit Hardware Description Language – Second level developed by the U.S. Department of Defense -Early 1980s : It was • Third level -1987 : IEEE Std 1076 - 87 -1993 : Added some new features and became IEEE Std 1076 – 93 -1999– An extension to the language called VHDL – AMS : Fourth level -2008: IEEE» Fifth level (New features) Std 1076 – 2008 Session One 9
    10. 10. • Click to edit Master Introduction to VHDL text styles – Second level ASIC and FPGA Design flow • Third level How to Read VHDL Code – Fourth level Demo no.1 Using ModelSim SE and Xilinx ISE » Fifth level Session One 10
    11. 11. ASIC and FPGA Design Flow Specifications System Level Design• Click to edit Master text styles – Second level • Third level Function RTL Description – Fourth level Verification » Fifth level Gate Level Synthesis Simulation Place &Route Fabrication Configuration ASIC FPGA Session One 11
    12. 12. ASIC and FPGA Design Flow• Click to edit Masteroftext styles designing the systemSpecification is an set requirements beforeRTL Description Register-Transfer Level (RTL) – Second level Designing using HDL which should be synthesizable • ThirdFunction Verification level Does this proposed design do what is intended? – Fourth level Functionality of your RTL TestSynthesis » Fifth level Convert RTL description into a H/W. You need to Verify that your RTL can be converted into hardwarePlacement Deciding where to place all electronic components.Routing Wiring the placed componentsThis last two steps depend on the rules and limitations of the manufacturing process. Session One 12
    13. 13. ASIC vs FPGA• Click to edit Master text stylesVerilog and VHDL are Hardware Description languages that are used to write programs forelectronic that do not share a computer’s basic architecture. – Second level FPGAs ASICs • Third level Programmable Gate Array Field Application Specific Integrated Circuit – Fourth level Re-Design CAN reprogrammable integrated CANNOT specific application » Fifth level circuit Main Purpose Design and Test and Implementation Implementation Area Wastes material Little wastes material Low Volume Better Expensive Production Session One 13
    14. 14. FPGAs• Click to edit Master text stylesField-Programmable Gate Arrays– Pre-fabricated silicon devices that comprise of an array of uncommitted circuit elements(logic blocks) and interconnect resources. – Second level– An IC designed to be configured by end-user after manufacturingImplement• Third level that ASIC can perform any logical function – Fourth levelApplications: – DSP » Fifth level – Device controllers – Medical imaging Session One 14
    15. 15. VHDL vs VerilogVerilog and VHDL are Hardware Description languages that are used to• Click to edit Master text styles Why do we Usewrite programs for electronic that do not share a computer’s basic VHDL !!architecture mainly FPGAs. – Second level Verilog VHDL History • Third level on C Based Older based on Pascal and Ada Data Types very simple – Fourth level strongly typed allows creating complex data types case sensitivity » Fifth sensitive case level case insensitive Session One 15
    16. 16. HDL vs Programming Languages HDL Programming Languages• Examples to edit Master text styles JAVA, ….. Click VHDL, Verilog, System C C, C#, – Second level Purpose Hardware Software [Digital Logic] [Binary Executable] • Third Development level Compile for Simulation Only compile – Fourth level for Hardware Synthesis Debugging » Fifth level and see waveforms Simulation Execute & See results text or graphic Statements Concurrent and Sequential Sequential Only Session One 16
    17. 17. VHDL Language Scope• Click to edit Master text stylesThere is two types of tools that deal with VHDL – Second level-Simulation (Used all programming languagecapabilities ) • Third usingto test the logic designlevel simulation models “AllLanguage syntax used’’ – Fourth level-Synthesis (Hardware)» Fifth levelto convert codes to hardware “pare of Languagesyntax used” IEEE 1076 IEEE 1076 Synthesis MODELING Session One 17
    18. 18. • Click to edit Master Introduction to VHDL text styles – Second level ASIC and FPGA Design flow • Third level How to Read VHDL Code – Fourth level Demo no.1 Using ModelSim SE and Xilinx ISE » Fifth level Session One 18
    19. 19. Library and Package • Click to edit Master text stylesVHDL libraries allow you to store commonly used packages and entities that you can use in your VHDLfiles.Library and Packages define special types used in a project. – Second level • Third level – LIBRARY ieee; Fourth level USE ieee.std_logic_1164.all; USE ieee………… » Fifth level .. Session One 19
    20. 20. Design Units • are two types ofedit units in VHDL text stylesThere Click to design Master – Not dependent upon other design units–Primary Second level • Third level Entity (Interface) How the system will communicate with the outside world ? – Fourth level » Fifth level–Secondary Depends on primary design unit Architecture (Function ) –What the system should do ?-No secondary can exist as stand-alone—without the primary-Whenever the primary design unit changes, the secondary design must be reanalyzed Session One 20
    21. 21. EntityDefine ports (inputs and outputs) of the module• Click to edit Master text styles i.e the interface of the blockEntity Declaration – Second levelENTITY architecture_name ISPORT( • Third level port_name : mode type; – Fourth mode port_name : level type; port_name Fifth level type » : mode);END entity_name; Session One 21
    22. 22. - <entity_name> Define the model name• Click to edit Master text styles- <port_name> Define the port name – VHDL is case Insensitive ----- Important of the port with Underscore _ or number - - Second port name or entity name Note Don’t start the level • Third level- <mode> Define the port direction IN – Fourth levelfrom it : Only read OUT » Fifth level : Only write on it INOUT : read from or write on it (controlled by another signal)<type> Define the port data type --------------------------------------------------------------------------------------------- Last port has no semicolon ;- Line Comments started by - -- Comma , can separate ports with the same type and mode - A,b : in bit ; 22
    23. 23. Example 01• Click to edit Master text stylesEntity of 2-input AND Gate – Second levelLIBRARY ieee; AUSE ieee.std_logic_1164.all; • Third level AND_GATE C B – FourthENTITY AND_GATE IS levelPORT ( » Fifth level a : in BIT; b : in BIT; C : out BIT );END ENTITY AND_GATE ; Session One 23
    24. 24. Question !!System A is composed of system B,C and D.• Click to edit Master text stylesDetermine the entity of system A? – Second level • Third level – Fourth level » Fifth level Session One 24
    25. 25. Question !!System A is composed of system B,C and D.• Click to edit Master text stylesDetermine the entity of system A? – Second level • Third level – Fourth level » Fifth level Entity A Session One 25
    26. 26. Basic data types VHDL i s s t r o n g l y t y p e d • Click to BIT Master text styles edit STD_LOGIC – Second level 0 1 0 1 H L U • Third level – Fourth level Default X W Z - Default value » Fifth level valueBIT_VECTOR :1D-array each element of the BIT type STD_LOGIC_VECTOR : 1D-array each element of the STD_LOGIC typeExample: Example: a : in BIT; a : in STD_LOGIC; b : in BIT_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); c : in BIT_VECTOR (0 to 3); c : in STD_LOGIC_VECTOR(0 to 3); Session One 26
    27. 27. Basic data types • XClick to edit Master text styles Z 0 1 U – Second levelUnknown High Strong Strong UnIitialized • ThirdImpedanceMULTIPLE DEVICE More than level Zero One Default valuevalue assigned in same signal – Fourth level W - » Fifth level H L Weak Don’t Weak Weak Unknown care One Zero To define std_logic data type LIBRARY ieee; USE ieee.std_logic_1164 .all; Session One 27
    28. 28. Basic data types VHDL is strongly typed • Click to BIT Master text styles edit STD_LOGIC – Second level 0 1 0 1 H L U • Third level – Fourth level Default X W Z - Default value » Fifth level valueBIT_VECTOR : Use std_logic1D-array each element of the BIT type STD_LOGIC_VECTOR : 1D-array each element of the STD_LOGIC typeExample: Example:a : in BIT; a : in STD_LOGIC;b : in BIT_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0);c : in BIT_VECTOR (0 to 3); c : in STD_LOGIC_VECTOR(0 to 3); Session One 28
    29. 29. Example 02• Click to edit Master text stylesEntity of 2-input AND Gate using STD_LOGIC – Second levelLIBRARY ieee; AUSE ieee.std_logic_1164.all; • Third level AND_GATE C B – FourthENTITY AND_GATE IS levelPORT ( » Fifth level a : in STD_LOGIC; b : in STD_LOGIC; C : out STD_LOGIC );END ENTITY AND_GATE ; Session One 29
    30. 30. ArchitectureDescribe the operation (relations between inputs and outputs) of the module• Click to edit Master text styles i.e the Body of the block – Second levelArchitecture Declaration • Third levelARCHITECTURE architecture_name OF entity_name IS --architecture declaration discussed laterBEGIN – Fourth level --architectureFifth level » bodyEND architecture_name ;Non-Blocking Assignment <=To assign operations on inputs into an output the non-blocking assignment is used -the LHS -> Outputs only as we write on it -the RHS -> Inputs only as we read from it C <= A and B ; C <= “01010..0”;--can make operations on RHS -- on std_logic_vector C <= „1‟; or c <= „0‟; to C(1) <= „1‟;--assign values on std_logic C(2downto 1 ) <= „1‟; Session One 30
    31. 31. Example 032-input AND Gate• Click to edit Master text stylesLIBRARY ieee; – Second levelUSE ieee.std_logic_1164.all; A • Third ISENTITY AND_GATE level AND_GATE CPORT ( B a : – Fourth level in STD_LOGIC; b : in STD_LOGIC; » Fifth level C : out STD_LOGIC );END ENTITY AND_GATE ;ARCHITECTURE behave OF AND_GATEISBEGIN c <= a and b; --non blocking assignmentEND behave; Session One 31
    32. 32. Example 04 N-bits 2-input AND Gate • Click to edit Master text stylesPackagesLibraries LIBRARY ieee; – Second level & USE ieee.std_logic_1164.all; A • AND_GATE IS ENTITY Third level AND_GATE C (input/output ports) B Interface definition PORT ( – Fourth level a : in std_logic_vector (3 downto 0); b : in Fifth level » std_logic_vector (3 downto 0); C : out std_logic_vector (3 downto 0) ); END ENTITY AND_GATE ; ARCHITECTURE behave OF AND_GATE IS Functional/behavioral Implementation BEGIN c <= a and b; --non blocking assignment END behave; Session One 32
    33. 33. • Click to edit Master Introduction to VHDL text styles – Second level ASIC and FPGA Design flow • Third level How to Read VHDL Code – Fourth level Demo no.1 Using ModelSim SE and Xilinx ISE » Fifth level Session One 33
    34. 34. Demo 01 ModelSim Setup Using Modelsim SE and Xilinx ISE• Click to edit Master text stylesInstallation StepsWriting code that describe the Entity and Architecture of 2-XOR Gate . – Second levelSimulating it on Modelsim and using Xilinx ISE synthesis tool. • Third levelTools : Modelsim SE / Xilinx ISE – Fourth levelGoal : Be familiar with tools before using it.Code : attached. » Fifth level A XOR C B Session One 34
    35. 35. Summary• VHDL is StronglyeditHardware Description Language.- Click to typed Master text styles- There are two basic design units to build your model – Second level - Entity : Define your model interface. - Architecture : Define operation of this model.- • Third level ASIC and FPGA design flow – Fourth level - Specifications - RTL » Fifth level - Verification (modeling) - Synthesis (hardware) - Gate Level Simulation - Place and Route - Configuration Session One 35
    36. 36. Time for Your Questions• Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level Session One 36
    37. 37. Download Session 01 Files• Click to edit Master text stylesRead Session-1 Notes carefully to be ready for the next session’s QUIZ –Demo_1 www.startgroup.weebly.com/vhdl-examples.html Second level • Third level Download tools : – Fourth level • Xilinx ISE WebPACK (Free) http://www.xilinx.com/support/download/index.htm » Fifth level • ModelSim SE http://model.com/content/modelsim-se-downloads-support Session One 37
    38. 38. Take Your Notes Print the slides and take your notes here---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- • Click to edit Master text styles------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ – Second level------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ • Third level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- – Fourth level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- » Fifth level----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    39. 39. Take Your Notes Print the slides and take your notes here---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- • Click to edit Master text styles------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ – Second level------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ • Third level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- – Fourth level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- » Fifth level----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    40. 40. See You Next Session .. Don’t miss• Click to edit Master text styles Thank – Second level • Third level – Fourth level You » Fifth level

    ×