Chap 3

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  • Look over examples 3-11 – 3-13, 3-17, 3-18
  • Explain using TT with opposite polarity don’t cared.
  • NAND AND NOR
  • Chap 3

    1. 1. Lecture No. 3 <ul><li>Computer Logic Design </li></ul><ul><li>Logic Gates </li></ul>
    2. 2. Logic Gates <ul><li>Logic Gates </li></ul><ul><ul><li>Basic building blocks of the digital circuits </li></ul></ul><ul><ul><li>Control flow of information </li></ul></ul><ul><ul><li>Represent Logical Operations (Functions) </li></ul></ul><ul><li>Fundamental Gates </li></ul><ul><ul><ul><li>AND, OR, NOT </li></ul></ul></ul><ul><li>Characteristics </li></ul><ul><ul><ul><li>Operation of the gate (what it does) </li></ul></ul></ul><ul><ul><ul><li>Function/truth table </li></ul></ul></ul><ul><ul><ul><li>Timing diagram </li></ul></ul></ul><ul><ul><ul><li>Application example </li></ul></ul></ul>
    3. 3. AND Gate <ul><li>AND Gate </li></ul><ul><ul><li>Standard logical symbol (ANSI/IEEE Standard 91-1984) </li></ul></ul><ul><ul><li>Where F is the output and A,B,C……,N are the inputs of the gate </li></ul></ul><ul><ul><li>Performs logical multiplication </li></ul></ul><ul><ul><li>The output is HIGH only when all the inputs are HIGH </li></ul></ul>
    4. 4. AND Gate <ul><li>The logical operation of a gate can be expressed with a table that lists all input combinations with the corresponding outputs, known as truth table </li></ul><ul><li>Truth table for a two input AND gate </li></ul>Input Output A B F 0 0 0 0 1 0 1 0 0 1 1 1
    5. 5. AND Gate <ul><li>Timing Diagram - a graph that accurately displays the relationship of two or more waveforms with respect to each other on a time basis </li></ul><ul><ul><li>Graphical representation of AND gate operation </li></ul></ul>
    6. 6. AND Gate <ul><li>Application example of AND gate </li></ul><ul><ul><li>Device (Stop-watch) enable/disable switch </li></ul></ul><ul><ul><li>When the input B is set to HIGH (enabled), the clock signal is applied to the counter </li></ul></ul>
    7. 7. OR Gate <ul><li>Standard logical symbol </li></ul><ul><li>Performs Boolean Addition </li></ul><ul><li>The output is HIGH when one or more inputs are HIGH </li></ul>
    8. 8. OR Gate <ul><li>Truth table for a two input OR gate </li></ul>Input Output A B F 0 0 0 0 1 1 1 0 1 1 1 1
    9. 9. OR Gate <ul><li>Timing diagram of the OR-Gate </li></ul>
    10. 10. OR Gate <ul><li>OR gate application example </li></ul><ul><ul><li>Car door alarm system </li></ul></ul><ul><ul><li>When all the doors are closed, 0000 is applied to the input of the OR gate </li></ul></ul><ul><ul><li>When one or more doors are open, the output of OR gate is 1, which activates the alarm </li></ul></ul>
    11. 11. NOT Gate <ul><li>The standard logical symbol </li></ul><ul><li>Performs the inversion or complementation </li></ul><ul><li>Changes one logic level to the opposite logic level </li></ul><ul><li>The bubble shows the negation </li></ul>
    12. 12. NOT Gate <ul><li>Truth table for a NOT Gate </li></ul>Input Output A F 0 1 1 0
    13. 13. NOT Gate <ul><li>Timing diagram of NOT-Gate </li></ul>
    14. 14. NOT Gate <ul><li>NOT gate application example </li></ul><ul><ul><li>1’s complement </li></ul></ul>
    15. 15. NAND Gate <ul><li>Contraction of NOT-AND </li></ul><ul><li>Standard logic symbol </li></ul><ul><li>Output is LOW only when all inputs are HIGH </li></ul><ul><li>Bubble indicates ACTIVE LOW output </li></ul><ul><li>Output level is opposite to that of the AND gate </li></ul>E
    16. 16. NAND Gate <ul><li>The truth table for a two input NAND gate </li></ul>Input Middle Output Output A B E F 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0
    17. 17. NAND Gate <ul><li>Timing diagram of NAND gate </li></ul>
    18. 18. NAND Gate <ul><li>NAND gate application example </li></ul><ul><ul><li>Device Failure Alarm System </li></ul></ul><ul><ul><li>When all the fans are working, the input to the NAND gate is 111 and the output is 0 </li></ul></ul><ul><ul><li>If any one of the fan stops working, the output of the NAND gate becomes 1, which activates the alarm </li></ul></ul>
    19. 19. NAND Gate as Negative-OR <ul><li>The truth table for a two input NAND gate looks awfully similar to an OR gate with the inputs inverted. </li></ul>Input NAND Output A B F 0 0 1 0 1 1 1 0 1 1 1 0 Input OR Output A B F 1 1 1 1 0 1 0 1 1 0 0 0
    20. 20. NAND Gate as Negative-OR Bubble signifies ACTIVE LOW INPUT
    21. 21. NAND Gate as a Universal Gate <ul><li>NAND gate can be used to perform all the fundamental gate operations (NOT, AND, OR) </li></ul><ul><ul><li>Universal NAND gate </li></ul></ul>
    22. 22. NAND as NOT Gate Join all the input pins of the NAND gate together Input Output A B F 0 0 1 0 1 1 1 0 1 1 1 0
    23. 23. NAND as AND Gate <ul><li>Using NAND gate to perform the AND gate operation </li></ul><ul><li>Remember NAND is NOT-AND. What if we inverse this one more level? NOT-(NOT-AND) = AND </li></ul><ul><li>Accomplished by applying a NOT operation (implemented through NAND gate) to the output of the NAND gate </li></ul>
    24. 24. NAND as OR Gate <ul><li>Using NAND gate to perform the OR gate operation </li></ul><ul><ul><li>Can we form NOR gate as well? </li></ul></ul>
    25. 25. NOR Gate <ul><li>Contraction of NOT-OR </li></ul><ul><li>The standard logic symbol </li></ul><ul><li>Produces a LOW output when one or more of its input is HIGH </li></ul><ul><li>Bubble indicates ACTIVE LOW output </li></ul><ul><li>The output logic is opposite to that of the OR gate </li></ul>
    26. 26. NOR Gate <ul><li>Truth table for a two input NOR gate </li></ul>Input Output A B F 0 0 1 0 1 0 1 0 0 1 1 0
    27. 27. NOR Gate <ul><li>Timing diagram of a NOR gate </li></ul>
    28. 28. NOR Gate <ul><li>Application as Washing Machine Controller </li></ul><ul><ul><li>If the machine lid is open or the water in the tub is below certain level or the machine is overloaded (weight of water and clothes in the tub is above certain limit), the output of corresponding sensor is set to 1, producing a 0 at the NOR gate output that switches the machine off </li></ul></ul>
    29. 29. NOR Gate as Negative-AND <ul><li>The truth table for a two input NOR gate looks awfully similar to an AND gate with the inputs inverted. </li></ul>Input NOR Output A B F 0 0 1 0 1 0 1 0 0 1 1 0 Input AND Output A B F 1 1 1 1 0 0 0 1 0 0 0 0
    30. 30. NOR Gate as Negative-AND Bubble signifies ACTIVE LOW INPUT
    31. 31. NOR Gate as a Universal Gate <ul><li>NOR gate can be used to perform all the fundamental gate operations (NOT, AND, OR) </li></ul><ul><ul><li>Universal NOR gate </li></ul></ul>
    32. 32. NOR as NOT Gate Join all the input pins of the NOR gate together Input Output A B F 0 0 1 0 1 0 1 0 0 1 1 0
    33. 33. NOR as OR Gate <ul><li>Using NOR gate to perform the OR gate operation </li></ul><ul><li>Remember NOR is NOT-OR. What if we inverse this one more level? NOT-(NOT-OR) = OR </li></ul><ul><li>Accomplished by applying a NOT operation (implemented through NOR gate) to the output of the NOR gate </li></ul>
    34. 34. NOR as AND Gate <ul><li>Using NOR gate to perform the AND gate operation </li></ul><ul><ul><li>Can we form NAND gate as well? </li></ul></ul>
    35. 35. Review <ul><li>The output of a logic gate is used to activate an alarm whenever at least one of its inputs is LOW. Name the gate? </li></ul><ul><li>Name the following gate? </li></ul><ul><li>Name the following gate? </li></ul>
    36. 36. XOR Gate <ul><li>Exclusive OR (XOR for short) </li></ul><ul><ul><li>Standard logic symbol </li></ul></ul><ul><ul><li>This gate has only two inputs </li></ul></ul><ul><ul><li>Logical expression </li></ul></ul><ul><ul><li>The output is HIGH only when the two the inputs are at opposite logic level </li></ul></ul>
    37. 37. XOR Gate <ul><li>The truth table for XOR Gate </li></ul>Input Output A B F 0 0 0 0 1 1 1 0 1 1 1 0
    38. 38. XOR Gate <ul><li>Timing diagram of XOR gate </li></ul>
    39. 39. XOR Gate <ul><li>Application example of XOR gate </li></ul><ul><ul><li>Detecting odd parity </li></ul></ul><ul><ul><li>Applying 0011 at the input A, B, C and D respectively generates 0 at the output of XOR gate 1, XOR gate 2 and XOR gate 3, indicating that number of 1s are not odd </li></ul></ul><ul><ul><li>Applying 1011at the input generates a 1 at the output of XOR gate 3 indicating odd number of 1s </li></ul></ul>
    40. 40. XNOR Gate <ul><li>Exclusive-NOR (XNOR for short) </li></ul><ul><ul><li>Standard logic symbol </li></ul></ul><ul><ul><li>This gate has only two inputs </li></ul></ul><ul><ul><li>Logical expression </li></ul></ul><ul><ul><li>The output is LOW only when the two inputs are at opposite logic level </li></ul></ul>
    41. 41. XNOR Gate <ul><li>Truth table for XNOR gate </li></ul>Input Output A B F 0 0 1 0 1 0 1 0 0 1 1 1
    42. 42. XNOR Gate <ul><li>Timing diagram of XNOR gate </li></ul>
    43. 43. XNOR Gate <ul><li>Application example of XNOR gate </li></ul><ul><ul><li>Detecting even parity </li></ul></ul><ul><ul><li>Applying 1011 at the input A, B, C and D respectively generates 1 at the output of XOR gate 1, a 0 at the output of XOR gate 2 and a 0 at the output of XNOR gate 3, indicating that the number of 1s in the input sequence are not even </li></ul></ul><ul><ul><li>Applying 0011 generates 1 at the XNOR gate output, indicating even number of 1s </li></ul></ul>
    44. 44. Summary of logic gates <ul><li>Fundamental logic gates </li></ul><ul><ul><li>AND </li></ul></ul><ul><ul><li>OR </li></ul></ul><ul><ul><li>NOT </li></ul></ul><ul><li>Universal gates </li></ul><ul><ul><li>NAND </li></ul></ul><ul><ul><li>NOR </li></ul></ul><ul><li>Other gates </li></ul><ul><ul><li>XOR </li></ul></ul><ul><ul><li>XNOR </li></ul></ul><ul><li>Standard logic symbol </li></ul><ul><li>Logical/Boolean expression </li></ul><ul><li>Truth table </li></ul><ul><li>Application example </li></ul>

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