1. 1668 McGregor Way Home (408) 252-6687
San Jose, CA 95129 Cell (408) 386-8381
E-mail sang_job2828@sbcglobal.net
Soo T. Ang (ST)
OBJECTIVE:
A Staff Test Engineer that matches my expansive experience in high speed test development in
specialty Synchronous QDR/DDR SRAM, SDRAM, Flash, ASIC Logic or USIM devices,
product and applications engineering along with my hands-on problem solving skills on various
test systems.
EXPERIENCE:
• Extensive hands-on experience on high speed test development and product & design debug
and validations. Worked in various start-ups.
• Familiar with final product development from product/test engineering management through
program specific implementation for complete test coverage, thorough device checkout and
characteristic validations, failure modes and effect analysis, and production flow and test
screen for solid device performance in applications.
• Contributor in high speed testing and understand device and effects of test hardware fixture
design and production transfer to subcontractor environment.
• Worked with subcontractors overseas in all aspect of engineering transfer relating to devices
manufacturing and production.
Marvell Technology Group Santa Clara, CA 2008 - Present
Sr. Staff Test Engineer Test Chips validation and debug of in-house designed memory IP’s on
Advantest T5781ES.
Spansion LLC Sunnyvale, CA Oct 05 - 2008
Member of Technical Staff Test Engineer (continuing career in Flash test development)
Develop characterization program and debug for embedded MirrorBitTM
ORNAND and NOR
Flash. Wrote from scratch Flash manufacturing and format programs via ISO7816-3 and MMC
4.2 protocols for HD-SIMTM
Smart Card Module on Verigy V5000 testers replacing ISO card
readers and PC systems and tools. Work on conversion of on-chip test controller’s logic
VCD/WGL files to V5000 vectors and device debug supporting design on MBIST, Scan Chains
and functional vectors with BCS(nanoisi) conversion and Verigy IDE waveform tools.
NexFlash (Merger into Winbond America) San Jose, CA Mar 05 – Oct 05
Serial Flash Test/Product Engineering
Worked on Serial Flash products and oversaw product & test development in-house and
engineered operation and production supports in subcontractors overseas.
ISSI Semiconductor, Inc. Santa Clara, CA Nov 94 – Feb 05
SyncSRAM/SDRAM Test Engineering & DRAM Product Engineering:
• Had developed software and hardware fixtures for testing SSRAMs, SDRAMs, SGRAMs,
SigmaRAM, QDR and Cache Modules on Advantest T5361/T5382A/T5334/T5581/T5592,
Megatest GII and HP82000 Systems for final and wafer sort tests. Support design in devices
debug and characterizations, full functionality checkout and evaluations, and resolving
applications specific issues.

2. • Manage test and product (SDRAM) engineering and related activities for product
development to support design debug and applications issue resolution, device yield
improvement and failure mode analysis, production overall flow and cost reduction.
• Involved in hands-on Sync./ZBT/QDR SRAMs and SigmaRAM final test software and
hardware development.
Pericom Semiconductor, Corp. Santa Clara, CA Nov 93 – Nov 94
Staff Test Engineer:
Developed software and hardware interfaces for testing FCT logic and wide bus devices, bus
switches, clock generators and token ring hub chip on HP82000 Systems for final and wafer sort
tests. Support design in bench characterizations and evaluations on clock generators. Designed
external clock counter and interfaced to HP82000 for simple and fast test enhancing throughput.
Quality Semiconductor, Inc. (QSI) Santa Clara, CA Apr 90 – Nov 93
Test Engineering Supervisor:
Took charge of test engineering in test development for FCT logic, CMOS SRAM and specialty
memory, FIFO, ASIC products (JTAG) on TSSI tool, Ando 9034/9047, MCT 2020, and EPRO
142A Test Systems. Performed devices debug, characterizations and production sustaining
functions. Key contributor for product and test development, and implementation before the
company went IPO.
Aspen Semiconductor, Inc. (Cypress’s subsidiary) Jan 89 – Apr 90
Senior Test Engineer:
Developed BiCMOS TTL & ECL SRAM final test on Advantest T5361/T3340 including device
characterizations and debug, and production sustaining. Worked on sort and laser repair
redundancy on Teradyne Systems M118.
Integrated Device Technology, Inc. Salinas/Santa Clara, CA Feb 88 – Jan 89
Senior Test Engineer:
Responsible for writing characterization and production software on Sentry S90 Memory Test
Systems to support design and final test of BiCMOS and high speed CMOS SRAMs. Also
evaluations on testers and related hardware for solutions to accurately testing the high speed
memory devices.
Fairchild Semiconductor Corp. Singapore/Puyallup, WA Nov 80 – Feb 88
Senior Test Engineer:
Generated characterization programs, data reduction software tool on PC using DBASE II, and
production test program on Xincom 5551/5580/81/82/88, Advantest T3331B and Sentry S90
Test Systems to support design and final test of MOS DRAMs, Bipolar TTL/ECL SRAMs,
CMOS SRAMs, PROM and BiCMOS Modules.
Key contributor for parallel testing on Xincom 5582 Test Systems. Found Xincom 5588 System
hardware faults on phase cards related to design, and incorporated manual deskew procedure to
compensate for system auto-calibration discrepancies.
Instrumental in the custom-built 50 ohm termination TTL head on Xincom 5588 with factory in
order to resolve transmission reflection problem for high speed testing.
Texas Instruments Singapore Jul 75 – Sep 77
Maintenance Engineering:
Responsible for repairs and maintenance of computerized controlled test systems, tester
hardware, handlers, and computer peripherals for final test of PMOS LSI devices.
EDUCATION:

3. Bachelor of Science in Computer Science 1980, Major in Computer Science and Engineering
University of Manchester, Manchester, England
Associate Degree in Electronic Engineering, Polytechnic of Singapore 1975
REFERENCES available upon request