The document provides a detailed description of the 80386dx microprocessor, highlighting its architecture, pin functions, and various control signals. It explains how the microprocessor manages memory addresses, data transfers, and interrupt handling through its pin configurations. Additionally, it covers aspects such as bus arbitration, co-processor signaling, and clock timing relevant to the operation of the 80386dx.

1. Pin Description of
80386dx.
Introduction to 80386dx Architecture.

2. Introduction to the
80386 Microprocessor
• the 80386DX is packaged in a 132-pin PGA.
• 80386DX addresses 4G bytes of memory
through its 32-bit data bus and 32-bit
address.

5. Function of each
80386dx group of pins:
• A31 to A2 - Address bus
connections address any
of the 4G bytes memory
locations in the 80386
memory system.
• A0 - A1 are encoded in
the Bus Enable BE0-BE3
to select any or all of
the four bytes in a 32-bit
wide memory location.

6. Bank Enable Signals
(BE3 - BE0)
• These signals select the access of a
byte, word, or double word of data.
• These signals are generated
internally by the microprocessor
from address bits A1 and A0.
• The 32- bit data bus supported by
80386 and the memory system of
80386 can be viewed as a 4- byte
wide memory access mechanism.
The 4 byte enable lines BE
0
to BE
3
,
may be used for enabling these 4
blanks. Using these 4 enable signal
lines, the CPU may transfer 1 byte /
2 / 3 / 4 byte of data simultaneously.

7. Data Bus (D31 - D0)
• Data bus connections
transfer data between
microprocessor and its
memory and I/O system.
• These 32 lines act as
bidirectional data bus
during different access
cycles.

8. Bus Cycle Definition
Pins
• M/IO -
a)This output pin
differentiates between
memory & I/O cycles.
b)The pin selects a memory
device when at logic 1 and an
I/O device in case of logic 0.
• W/R -
a) This pin distinguishes the
read and write cycles from
one another.
b) It indicates that the
current bus cycle is a write
when at logic 1 and a read at
logic 0.

9. Bus Cycle Definition
Pins• D/C - Data/Control Pin
a) This pin distinguishes a data
transfer cycle from a machine
control cycle.
b) Indicates that the data bus
contains data for or from
memory of I/O when at logic 1.
c) At logic 0, microprocessor is
halted or executes an interrupt
acknowledge.
• LOCK - this pin enables the
CPU from preventing other bus
masters from gaining control of
the system bus.

10. Bus Control Pins
• ADS - Address Data Strobe.
a) The address status output pin
indicates that the address bus
and bus cycle definition pins are
carrying the respective valid
signals.
b) This signal becomes active
whenever the 80386 has issued a
valid memory or I/O address.
• NA - Next Address causes the
80386 to output the address of
the next instruction or data in
the current bus cycle.This pin is
used for pipelining the address.

11. Bus Control Pins
• BS16 - Bus Size 16 pin selects either
a 32 bit data bus (BS16 = 1) or a 16
bit data bus (BS16 = 0)
a) In most cases, 80386DX is
operated on 16 bit data bus.
b)The bus size16 input pin allows
the interfacing of 16 bit devices with
the 32 bit wide 80386 data bus.
• READY - The ready signals indicates
to the CPU that the previous bus
cycle has been terminated and the
bus is ready for the next cycle.The
signal is used to insert WAIT states
in a bus cycle and is useful for
interfacing of slow devices with
CPU.

12. Interrupts
• Interrupt is a signal to the processor
emitted by hardware or software
indicating an event that needs
immediate attention.
• An interrupt alerts the processor to a
high-priority condition requiring the
interruption of the current code the
processor is executing.
• The processor responds by suspending
its current activities, saving its state, and
executing a small program called an
interrupt handler (or interrupt service
routine, ISR) to deal with the event.
• This interruption is temporary, and
after the interrupt handler finishes, the
processor resumes execution of the
previous thread.

13. Interrupt Pins
• INTR - An Interrupt Request is used
by external circuitry to request an
interrupt.
This interrupt pin is a maskable
interrupt, that can be masked using
the IF of the flag register.
• NMI - A Non-Maskable interrupt
requests a non-maskable interrupt
as it did not in the earlier versions
of the microprocessor.
• RESET - A high at this input pin
suspends the current operation and
restart the execution from the
starting location. (location for
80386dx is FFFFFFF0H.)

14. Bus Arbitration Pins
• HOLD -The bus hold input pin
enables the other bus masters to
gain control of the system bus if it
is asserted.
Hold requests a DMA action.
- Direct memory access (DMA) is
a feature of modern computers
that allows certain hardware
subsystems within the computer
to access system memory
independently of the central
processing unit (CPU).
• HLDA - Hold Acknowledge
indicates that the 80386 is
currently in hold condition.

15. Co-process or Signaling
• BUSY - The busy input signal
indicates to the CPU that the
coprocessor is busy with the
allocated task.
This input is used by the WAIT
instruction.
• ERROR - Indicates to the
microprocessor that an error is
detected by the coprocessor
while executing an instruction.
• PEREQ - The Coprocessor
Request asks the 80386 to
relinquish control and is a direct
connection to the 80387
arithmetic coprocessor.

16. Clock Times 2 & Power
Connections
• CLK2 :This input pin provides
the basic system clock timing
for the operation of 80386.
- Clock Times 2 is driven by a
clock signal that is twice the
operating frequency of the
80386.
• VCC:These are system
power supply lines.
• VSS:These return lines for
the power supply.

17. References
• The 80386 and 80486 Microprocessor - Barry B. Brey.
• NPTEL Introduction to 80386 Architecture PDF.
• Wikipedia - for some definitions and 80386DX Image.