Brief overview of benefits of using sigma delta ADC for implantable medical. This discussion is focused on cardiac sensing applications.

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Sigma Delta Converters for
Implantable Cardiac Sensing applications
November 25, 2015.
Sigma Delta ADC
The sigma delta (ΣΔ) ADC has found ubiquitous use in many industrial and commercial
applications. However, it has not made many inroads into implantable medical device
(IMD) design. One of the reasons ΣΔ’s are not used extensively is on account of their
higher current consumption in comparison to the Successive Approximation (SAR)
converters.
With the rapid miniaturization of IMD sizes, and the availability of smaller process
corners, other criteria become equally important for the signal chain. As our frame of
reference shifts, a re-evaluation of the benefits and tradeoffs becomes a useful exercise.
In the following sections we will see that the ΣΔ ADC provides some very interesting
benefits. These features if utilized properly will yield a signal chain that is very
comparable in power consumption to that obtained using a SAR converter. Moreover, the
ΣΔ ADC also provides other benefits such as ability to shrink the size of passives and
reduced dependence on process matching the likes of which cannot be ignored easily.
For those readers that are unfamiliar with the operation of the ΣΔ converter, the following
application note from Intersil [1] introduces many concepts of the ΣΔ modulation in an
easy to read manner.
This white paper explores the use of ΣΔ converters for intra cardiac sensing applications.
Although cardiac sensing has been around since the advent of the IMD’s, shrinking
device sizes and current budgets force the industry to continually seek newer ways of
achieving the same goal.
Most of the signal content of the cardiac signals is typically between a few Hz to about
40 Hz. The following picture provides a spectral plot of the various frequencies and the
physiologies causing those spectra. This picture is available in [2] which is a very nice
introduction to signal processing for 12-lead EKG’s.

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Fig.1: Relative power spectra of QRS complex, P &T waves, muscle noise and motion artifacts based on
an average of 150 beats (from [2])
In the industry, it is not uncommon to find sense chains that sample the ECG’s at a rate
anywhere between 200 to 500 samples per second. These are Nyquist converters that
predominantly use a SAR converter as the ADC.
Typical resolutions range from 8-bits to 12-bits. The lower 8-bit converters might be
sufficient for heart rate detection while the higher resolution converters are needed for
diagnostic viewing of the waveform and other morphological analysis such as p-wave
detection.
The following exercise shows the resolutions theoretically possible from a ΣΔ converter
using a sampling frequency of 4 KHz. Theoretical limits are based on the quantization
noise limits that are necessary to ensure desired resolution. [3]
With 40 Hz bandwidth and 4 KHz sampling, the OSR = (4000)/ (2x40) = 50.
Single Stage ΣΔ Converter:
SNRMAX = 6.02N + 1.76 -5.17 +30 log (OSR)
With N = 1 bit and OSR = 50, we get SNRMAX =53.6 dB
For proper operation, an 8-bit converter would need an SNR of 54 dB. This is assuming
that there are 255 levels of quantization and quantization noise from the converter is one
half of one lsb (i.e. 0.5 * (1/255))
SNRNEEDED = 20log [1/ (0.5* (1/(28
-1))) ] = 54 dB
In comparison an 8-bit Nyquist converter provides an SNR of:

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SNRMAX = 6.02N + 1.76 = 6.02(8)+1.76 = 50 dB
Two-stage ΣΔ Converter:
SNRMAX = 6.02N + 1.76 -12.9 +50 log (OSR)
With N – 1 bit and OSR = 50, we get SNRMAX =80 dB
For proper operation, a 12-bit converter would need an SNR of 78 dB. This is assuming
that there are 4095 levels of quantization and quantization noise from the converter is one
half of one lsb (i.e. 0.5 * (1/4095))
SNRNEEDED = 20log [1/ (0.5* (1/(212
-1))) ] = 78 dB
In comparison a 12-bit Nyquist converter provides an SNR of:
SNRMAX = 6.02N + 1.76 = 6.02(12)+1.76 = 74 dB
Table 1: Performance summary of ΣΔ converter from calculations above
CONVERTER
RESOLUTION
SNR NEEDED FOR
OPERATION
THEORETICAL LIMIT
OF SNR FROM ΣΔ
CONVERTER
THEORETICAL LIMIT
OF SNR FROM NYQUIST
CONVERTER
8-bit 54 dB 53.6 dB (Single stage) 50 dB
12-bit 78 dB 80 dB (Two stage) 74 dB
This simple exercise shows that with clock frequencies around 4 KHz, it is possible to
build ΣΔ converters that provide resolutions similar to nyquist converters. Actual
realizations might want to slightly increase the sampling frequency to ensure some
margin.
The 4 KHz sampling was chosen because signal chains that use nyquist sampling, need
clocks that are at least that frequency. For.e.g, 500 samples per second x 8 bits per sample
= 4000 Hz. (One clock per bit for SAR ADC conversion)
This exercise also shows that, in comparison to nyquist converters we get an additional 4-
6 dB improvement in SNR. This is on account of the noise shaping characteristics of the
ΣΔ converter.
For applications that require higher frequency content, it is possible to trade-off the
bandwidth for resolution. For e.g if the bandwidth of interest is 100 Hz, the two stage
modulator operating at 4 KHz is still able to provide 10 bit resolution.
Decimator design:
It is very common among signal chains suing a SAR converter to have the decimator
implemented as an analog block. This block typically has an operational amplifier (OTA)
along with sampling and feedback capacitors that accumulate the signal. The signal is
accumulated and down sampled by a fixed ratio before being sampled by the ADC.
The ΣΔ converter on the other hand, implements a digital decimator that takes the 1-bit
output from the comparator as its input. It produces an output that has the desired number
of bits needed for the system.

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With the advent of Cascaded Integrator Comb (CIC) filters, the design of this digital
decimator can be accomplished without the need for multipliers. Low pass filters of
desired characteristics can be obtained just by the use of addition and down sampling
operations. This advent greatly simplifies the digital design and allows for reduced power
consumption.
In a classical paper that outlines this approach, Hogenauer describes the theory behind
this approach [4]. Further simplification has been achieved since the time his work was
introduced. A simple explanation that is readily adopted for implementation is found in
the work done by Lyons [5].
For signal chains processing cardiac signals, the digital decimator can be implemented in
few tens of nano amps. Further, as technologies scale, this current is more likely to
reduce. In comparison, much larger currents are required just to bias the OTA’s that are
used in the analog decimators.
Oversampling conversion
The ΣΔ converter is an oversampled converter requiring the sampling frequency to be
higher than the nyquist frequency for its operation. An interesting side benefit of this
approach is the ability to relax the front end anti-aliasing filter (AAF) passives.
Apart from reducing component sizes, it begins to open the possibility of absorbing some
of the passive components within the integrated circuit (IC) itself. This might be a big
benefit to new products like the leadless pacemaker where real estate on the module is
very limited.
For purposes of illustration, assuming we want a decade of separation between the
sampling frequency and the AAF pole, a sampling frequency of 4 KHz requires an AAF
pole at 400 Hz. This pole could be realized using a 10 MΩ resistor and a 40 pF capacitor.
While these values are not used commonly in an IC, they are definitely within the realm
of an integrated realization.
Suitable margins in sampling frequency and/or circuit techniques for resistor realization
can further reduce the area impact on the IC.
Fully differential design
The ΣΔ design yields itself very well to fully differential design. The work done by Boser
and Wooley [6] provides many implementation level details and draws attention to the
design considerations. While fully differential designs provide many benefits, one of the
most relevant benefits to IMD signal chains is to further reduce the effect of matching
imperfections. By representing the signal on a positive and a negative signal path, any
mismatch on any one signal path to a first degree is cancelled by the same mismatch
occurring on the other signal path. Other nonlinearities such as clock feedthrough and
switch charge injection are also diminished on account of the same reason.

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Fig.2: Second Order ΣΔ modulator implementation (from [6])
A single temperature insensitive voltage reference that is generally available within the
system is sufficient to establish the common mode of the signal chain. The positive and
negative references shown above are centered about the system reference voltage. The
input range of the ΣΔ converter is contained within the positive and negative references.
Although many fully differential designs are realized with both a positive and a negative
reference, the ΣΔ converter is able to use charge based references. In the following
circuit, capacitors that are switched to ‘VREF’ are adding or removing a fixed amount of
charge from the integrators. The integrator creates voltages equivalent to the injected
charge [7].
Thus the need for a separate circuit to generate positive and negative references is
circumvented by suitable circuit techniques within the modulator itself.

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Fig.3: Single stage of differential architecture (from [7])
Reduced dependence on process matching
One of the biggest benefits of a ΣΔ converter in comparison to its SAR counterpart is its
reduced dependence on process matching. SAR converters use binary weighted capacitor
DAC’s. In order to reduce the area impact, most SAR architectures use two capacitor
DAC’s. The second DAC is considered a sub-DAC and its operation is voltage divided to
the main DAC by a single unit sized capacitor.
On account of these architectural choices, capacitor matching is very important in a SAR
ADC. Capacitors at one end of the cap DAC have to match very closely with those at the
other end of the DAC. Typically the SAR design takes at least one additional tape-out
before design can be finalized. Designers most often do not have the matching
characteristics of their specific design until the first version is characterized.
A ΣΔ converter on the other hand is a single bit converter. Only the sampling capacitor
and the feedback capacitor on the integrator need to match closely with each other. They
can be placed right next to each other in the physical design. Thus the critical components
are not exposed to a large area of the IC where variations can begin to play a role.

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This reduced dependence on process matching is a powerful asset. It greatly increases the
possibility of design success at the first attempt. Further it makes the design easily
portable to other technology nodes. Also during the lifetime of the device, the yield is not
likely to be impacted on account of matching related issues from the ADC.
Power of feedback:
In a ΣΔ converter, the modulator is in a feedback loop along with the comparator. This
feedback loop provides a powerful way of compensating for many nonlinearities that
exist in the analog portions. Nonlinearities such as comparator offset and integrator offset
do not heavily impact the performance.
Boser [6] explains that due to the feedback, the comparator offset is stored in the second
integrator. Their work quantifies that a comparator hysteresis of as much as 5% of the
input range does not affect the performance of the converter.
This aspect of the ΣΔ converter allows one to greatly simplify the design of the
comparator. It is not uncommon to find comparator designs that altogether do away with
the need for a preamplifier and auto zeroing schemes. Comparison is achieved by just
using of dynamic CMOS latch architectures [8]
Normally, these dynamic latches are preceded by a preamplifier stage to mitigate the
large input offset. However, since the offset is stored in the feedback loop of the ΣΔ
modulator, the latch can be directly connected to the modulator.
The dynamic latches have zero static current consumption and are very attractive option
for IMD sense chains.
Fig.4: Dynamic latch (from [8])
Programmable resolution
It is very easy to switch the ΣΔ converter from a single stage converter to a two stage
converter. All that is required is a multiplexer that routes the signals from the

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modulator(s) to the comparator. No changes are needed in the decimator. But it provides
some very interesting flexibility.
This provides a new way of adapting the hardware to rate sensing mode or for other
modes where morphology needs to be preserved. The majority of the time the converter
could operate in a rate sensing mode and could enter the high resolution mode on an as
needed basis.
This could have a big impact on the average current consumption of the sense chain since
the rate sensing mode is likely to be used most of the time. A single stage converter uses
only one modulator and its current consumption is almost half of the two stage converter.
Summary
Many benefits of using the ΣΔ converter were analyzed. Historically ΣΔ converters have
not found wide adoption in the IMD industry for cardiac sensing due to higher current
consumption concerns. However, it was shown that the ΣΔ converter provides the
following benefits that greatly save current consumption:
• The use of CIC filters for implementing digital decimators
• Simplification in the comparator design that does away with the need for pre-
amplifiers
• Flexibility to switch to a lower current low resolution mode for rate response
detection resulting in lower average currents.
• Charge based internal references that do away with the need for separate reference
circuits needed for fully differential operation.
Moreover the ΣΔ converter provides the following additional benefits that are very
attractive:
• Ability to reduce size of external passives used for the AAF. Opens up the
possibility of absorbing the passives into the IC: saving module real-estate.
• Greatly reduced dependence on process matching resulting in high probability of
first time design success.
In lieu of these features, it is summarized that all or some combination of these
techniques can be adopted to realize a design that compares very well to traditional SAR
converters
References
[1] A brief introduction to Sigma Delta Conversion
Application Note. Intersil. AN9504, May 1995
Author: David Jarman
[2] http://www.ems12lead.com/2014/03/10/understanding-ecg-filtering/
[3] Analog Integrated Circuit Design
David A. Johns, Ken Martin
Pages 451, 542 and 544.
[4] An Economical Class of Digital Filters for Decimation and Interpolation
Eugene B. Hogenauer

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IEEE Transactions on Acoustics, Speech, and Signal Processing
VOL. ASSP-29, NO.2, APRIL 1981
[5] Reducing power consumption in CIC filter algorithm designs
Richard Lyons – September 04, 2012
Appears in: embedded.com
[6] The Design of Sigma-Delta Modulation Analog-to-Digital Converters
Bernhard E. Boser and Bruce A. Wooley
IEEE JSSC, VOL.23 NO.6, December 1988.
[7] Oversampling Converters
Paul Ferguson, Jr. et. al (Analog Devices)
ISSCC91/SESSION 4/PAPER WP 4.4
[8] Design Techniques for High-Speed, High-Resolution Comparators
Behzad Razavi and Bruce Wooley
IEEE JSSC, VOL.27, NO. 12, December 1992.
Contact
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